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* Use getTargetDefines() virtual function in MipsTargetInfoBase successorsSimon Atanasyan2012-08-291-14/+12
| | | | | | | to define all macros for MIPS targets. Remove redundant virtual function getArchDefines(). Two virtual functions for this task are really too much. llvm-svn: 162853
* Factor out MIPS macro definitions common for all MIPS targets.Simon Atanasyan2012-08-291-12/+4
| | | | llvm-svn: 162852
* Define _MIPS_ARCH and _MIPS_ARCH_<cpu name> macros for MIPS targets.Simon Atanasyan2012-08-291-0/+3
| | | | | | The patch suggested by Logan Chien. llvm-svn: 162840
* Remove FIXME, the constraints contain more options than theEric Christopher2012-08-161-1/+0
| | | | | | current available documentation. llvm-svn: 162065
* Add a missing 'break' to ensure that we reject inline assemblyEric Christopher2012-08-161-1/+1
| | | | | | constraints we don't recognize. llvm-svn: 162064
* Frontend: define _LP64 in a target-independent wayDylan Noblesmith2012-08-101-6/+0
| | | | | | | | | | | | | | Instead of adding it to each individual subclass in Targets.cpp, simply check the appropriate target values. Where before it was only on x86_64 and ppc64, it's now also defined on mips64 and nvptx64. Also add a bunch of negative tests to ensure it is *not* defined on any other architectures while we're here. llvm-svn: 161685
* clang support for Bitrig (an OpenBSD fork); patch by David Hill.Eli Friedman2012-08-081-0/+53
| | | | llvm-svn: 161546
* Revert part of r161175 which was wrong for OpenBSD's PowerPC target.Hans Wennborg2012-08-081-1/+0
| | | | | | Contributed by Brad Smith <brad@comstyle.com> llvm-svn: 161481
* Add OpenBSD arch targets for powerpc, arm, mips64, mips64el and sparc.Hans Wennborg2012-08-021-1/+13
| | | | | | Contributed by Brad Smith <brad@comstyle.com> llvm-svn: 161175
* TLS is not supported on OpenBSDHans Wennborg2012-08-011-0/+1
| | | | | | | This fixes PR13502 and adds a test to keep track of which targets support TLS and which do not. llvm-svn: 161124
* Add a per target max vector alignment field (e.g., 32-byte alignment for x86 ↵Chad Rosier2012-07-131-0/+2
| | | | | | | | | | due to AVX). Currently, if no aligned attribute is specified the alignment of a vector is inferred from its size. Thus, very large vectors will be over-aligned with no benefit. Target owners should set this target max. llvm-svn: 160209
* Fix handling of curly braces in NVPTX inline asmJustin Holewinski2012-07-111-0/+1
| | | | | | | | Fixes bug 13322 Patch by Dmitry Mikushin llvm-svn: 160050
* Wire up -mrdrnd for X86.Benjamin Kramer2012-07-071-4/+27
| | | | | | | For some reason GCC decided to call the feature rdrnd instead of rdrand, which requires translating it for LLVM. llvm-svn: 159897
* Remove unreachable default case to pacify clang's -Wcovered-switch-default.Benjamin Kramer2012-07-061-1/+0
| | | | llvm-svn: 159829
* MIPS: Define __mips_dsp_rev / __mips_dspr2 / __mips_dsp macrosSimon Atanasyan2012-07-051-0/+23
| | | | | | if -mdsp or -mdspr2 options are provided. llvm-svn: 159774
* MIPS: Add -mdsp/-mno-dsp and -mdspr2/-mno-dspr2 command line options support.Simon Atanasyan2012-07-051-1/+1
| | | | llvm-svn: 159769
* MIPS: Define __mips16 macro if -mips16 option is provided.Simon Atanasyan2012-07-051-0/+8
| | | | llvm-svn: 159753
* MIPS: Replace the pair of boolean flags by enumeration to hold selected ↵Simon Atanasyan2012-07-051-24/+26
| | | | | | float ABI. llvm-svn: 159752
* MIPS: Add -mips16 / -mno-mips16 command line support.Simon Atanasyan2012-07-051-1/+2
| | | | llvm-svn: 159747
* Add additional architecture defines for PPC targets.Hal Finkel2012-07-031-9/+49
| | | | | | Patch by Andy Gibbs. llvm-svn: 159665
* Support MIPS DSP Rev1 intrinsics. Simon Atanasyan2012-06-281-1/+10
| | | | | | This patch was reviewed in the llvm-commits list by Jim Grosbach. llvm-svn: 159366
* Explicitly build __builtin_va_list.Meador Inge2012-06-161-42/+30
| | | | | | | The target specific __builtin_va_list types are now explicitly built instead of injecting strings into the preprocessor input. llvm-svn: 158592
* Add PPC support for translating gcc-style -mcpu options into LLVM ↵Hal Finkel2012-06-111-0/+49
| | | | | | | | | | | | | | -target-cpu options. This functionality is based on what is done on ARM, and enables selecting PPC CPUs in a way compatible with gcc's driver. Also, mirroring gcc (and what is done on x86), -mcpu=native support was added. This uses the host cpu detection from LLVM (which will also soon be updated by refactoring code currently in backend). In order for this to work, the target needs a list of valid CPUs -- we now accept all CPUs accepted by LLVM. A few preprocessor defines for common CPU types have been added. llvm-svn: 158334
* Add XOP feature flag.Craig Topper2012-06-091-8/+28
| | | | llvm-svn: 158284
* Mips: Define __mips_hard_float macro additional to __mips_single_floatSimon Atanasyan2012-06-051-6/+7
| | | | | | when single float ABI is selected. llvm-svn: 157996
* Make disabling SSE levels also disable AVX and FMA.Craig Topper2012-06-031-6/+13
| | | | llvm-svn: 157907
* Make AES and PCLMUL features imply SSE2 as that's needed to get the right ↵Craig Topper2012-06-031-3/+4
| | | | | | types defined. llvm-svn: 157906
* Add fma feature flag for Intel FMA instructions.Craig Topper2012-06-031-2/+21
| | | | llvm-svn: 157904
* Add builtin for pclmulqdq instruction.Craig Topper2012-05-311-4/+22
| | | | llvm-svn: 157733
* SSE4A should not imply LZCNT and POPCNT. FMA4 should imply SSE4A. Add ↵Craig Topper2012-05-301-3/+5
| | | | | | missing break at the end of btver1 feature list. llvm-svn: 157680
* Define __SSE4A__ when targeting new AMD CPUs.Benjamin Kramer2012-05-291-1/+11
| | | | | | This doesn't really fit the existing SSELevel so it gets an extra flag. llvm-svn: 157630
* Sparc is bigendian.Roman Divacky2012-05-291-1/+0
| | | | llvm-svn: 157626
* Replace PTX back-end with NVPTX back-end in all places where Clang caresJustin Holewinski2012-05-241-140/+30
| | | | | | NV_CONTRIB llvm-svn: 157403
* Teach Clang about the NVPTX backend.Peter Collingbourne2012-05-201-0/+98
| | | | llvm-svn: 157173
* CUDA: add CodeGen support for global variable address spaces.Peter Collingbourne2012-05-201-2/+8
| | | | | | | | | Because in CUDA types do not have associated address spaces, globals are declared in their "native" address space, and accessed by bitcasting the pointer to address space 0. This relies on address space 0 being a unified address space. llvm-svn: 157167
* Hexagon V5 FP support.Sirish Pande2012-05-101-2/+11
| | | | llvm-svn: 156567
* Enable AVX on AMD Bulldozer processors.Craig Topper2012-05-011-1/+1
| | | | llvm-svn: 155900
* Define __ANDROID__ macro on -androideabi targets.Evgeniy Stepanov2012-04-261-0/+2
| | | | llvm-svn: 155632
* Enable AVX/AVX2 for Sandy Bridge, Ivy Bridge, and Haswell CPUs.Craig Topper2012-04-261-4/+2
| | | | llvm-svn: 155624
* OpenBSD: Remove incorrect -pthread preprocessor define _POSIX_THREADS and ↵Chris Lattner2012-04-251-1/+1
| | | | | | | | | | replace with _REENTRANT. Also remove undef _POSIX_THREADS in phread.h. Patch by Brad Smith! llvm-svn: 155535
* Revert r155363, due to the underlying patches in LLVM causing regressionChandler Carruth2012-04-231-11/+2
| | | | | | test suite failures. llvm-svn: 155371
* Hexagon V5 (floating point) support in cfe.Sirish Pande2012-04-231-2/+11
| | | | llvm-svn: 155363
* Revert some Hexagon builtin commits to match reverts done to LLVM inChandler Carruth2012-04-181-11/+2
| | | | | | | | | | | | | | | | | | | r155047. See the LLVM log for the primary motivation: http://llvm.org/viewvc/llvm-project?rev=155047&view=rev Primary commit r154828: - Several issues were raised in review, and fixed in subsequent commits. - Follow-up commits also reverted, and which should be folded into the original before reposting: - r154837: Re-add the 'undef BUILTIN' thing to fix the build. - r154928: Fix build warnings, re-add (and correct) header and license - r154937: Typo fix. Please resubmit this patch with the relevant LLVM resubmission. llvm-svn: 155048
* MIPS: Followup to r154606. Expand list of accepted MIPS target features in ↵Simon Atanasyan2012-04-181-1/+4
| | | | | | the MipsTargetInfoBase::setFeatureEnabled() routine. llvm-svn: 154998
* Hexagon V5(Floating Point) support.Sirish Pande2012-04-161-2/+11
| | | | llvm-svn: 154828
* MIPS: Initialize MIPS CPU's name by default value.Simon Atanasyan2012-04-121-3/+6
| | | | | | | Otherwise MipsTargetInfoBase::getDefaultFeatures() might return an invalid features set with an empty feature name. llvm-svn: 154606
* Move some MIPS target macro definitions from class Mips32TargetInfoBaseSimon Atanasyan2012-04-051-4/+4
| | | | | | | to the base class MipsTargetInfoBase. These macros are applicable for both 32/64-bits targets. llvm-svn: 154116
* [driver] Create a new -mfpmath= option, which is used to control whether clangChad Rosier2012-04-041-1/+2
| | | | | | | | | | | uses Neon instructions for single-precision FP. -mfpmath=neon is analogous to passing llc -mattr=+neonfp. -mfpmath=[vfp|vfp2|vfp3|vfp4] is analogous to passing llc -mattr=-neonfp. rdar://11108618 llvm-svn: 154046
* Add more constraint registers for mips.Eric Christopher2012-04-031-0/+3
| | | | | | Patch by Jack Carter. Testcase cleanup by me. llvm-svn: 153921
* ARM backend knows about cortex-m4. The front end should too.Jim Grosbach2012-03-291-0/+1
| | | | llvm-svn: 153678
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