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* Implement target-specific __attribute__((aligned)) valueUlrich Weigand2015-04-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GCC construct __attribute__((aligned)) is defined to set alignment to "the default alignment for the target architecture" according to the GCC documentation: The default alignment is sufficient for all scalar types, but may not be enough for all vector types on a target that supports vector operations. The default alignment is fixed for a particular target ABI. clang currently hard-coded an alignment of 16 bytes for that construct, which is correct on some platforms (including X86), but wrong on others (including SystemZ). Since this value is ABI-relevant, it is important to get correct for compatibility purposes. This patch adds a new TargetInfo member "DefaultAlignForAttributeAligned" that targets can set to the appropriate default __attribute__((aligned)) value. Note that I'm deliberately *not* using the existing "SuitableAlign" value, which is used to set the pre-defined macro __BIGGEST_ALIGNMENT__, since those two values may not be the same on all platforms. In fact, on X86, __attribute__((aligned)) always uses 16-byte alignment, while __BIGGEST_ALIGNMENT__ may be larger if AVX-2 or AVX-512 are supported. (This is actually not yet correctly implemented in clang either.) The patch provides a value for DefaultAlignForAttributeAligned only for SystemZ, and leaves the default for all other targets at 16, which means no visible change in behavior on all other targets. (The value is still wrong for some other targets, but I'd prefer to leave it to the target maintainers for those platforms to fix.) llvm-svn: 235397
* R600: Add GCC reg namesTom Stellard2015-04-141-4/+60
| | | | llvm-svn: 234892
* Add Clang support for -mdirect-move on PPCNemanja Ivanovic2015-04-111-1/+12
| | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D8930 This just adds a front end option to let the back end know the target has PPC direct move instructions. llvm-svn: 234683
* Use 'override/final' instead of 'virtual' for overridden methodsAlexander Kornienko2015-04-111-15/+14
| | | | | | | | | | | | | | | | | | | | Summary: The patch is generated using clang-tidy misc-use-override check. This command was used: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py \ -checks='-*,misc-use-override' -header-filter='llvm|clang' -j=32 -fix Reviewers: dblaikie Reviewed By: dblaikie Subscribers: klimek, cfe-commits Differential Revision: http://reviews.llvm.org/D8926 llvm-svn: 234678
* Create the correct profiling symbol on NetBSD.Joerg Sonnenberger2015-04-101-0/+1
| | | | llvm-svn: 234636
* Create correct platform-specific target for NetBSD PPC64LE.Joerg Sonnenberger2015-04-101-0/+2
| | | | llvm-svn: 234629
* Add Clang support for remaining integer divide and permute instructions from ↵Nemanja Ivanovic2015-04-091-1/+26
| | | | | | | | | | | ISA 2.06 This patch corresponds to review: http://reviews.llvm.org/D8398 It adds some builtin functions to access the extended divide and bit permute instructions. llvm-svn: 234547
* [ARM] add support for Cortex-R4/R4FJaved Absar2015-04-091-3/+3
| | | | | | | | Adds ARM Cortex-R4 and R4F support and tests in Clang. Though Cortex-R4 support was present, the support for hwdiv in thumb-mode was not defined or tested properly. This has also been added. llvm-svn: 234488
* Set the type of ptrdiff_t to signed on NVPTX targetsEli Bendersky2015-04-011-4/+6
| | | | | | | It was unsigned before, which is unlike any other target and also doesn't make much sense. llvm-svn: 233836
* Set NVPTX64 target's size_t to match other 64-bit targetsEli Bendersky2015-04-011-2/+2
| | | | llvm-svn: 233830
* Fix data layout mismatch between LLVM and Clang for i686-pc-windows-msvc-elfReid Kleckner2015-04-011-1/+4
| | | | | | | | Do the same thing as win64. If we're not using COFF, use the ELF manglings. Maybe if we are targetting *-windows-msvc-macho, we should use darwin manglings, but I don't need to stir that pot today. llvm-svn: 233819
* [SystemZ] Add header files to Makefile / module.modulemapUlrich Weigand2015-04-011-1/+2
| | | | | | | | | | This should fix build-bot failures after r233804. The patch also adds a "systemz" feature, and renames the "transactional-execution" feature to "htm", since it turns out "-" is not a legal character in module feature names. llvm-svn: 233807
* [SystemZ] Support transactional execution on zEC12Ulrich Weigand2015-04-011-6/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The zEC12 provides the transactional-execution facility. This is exposed to users via a set of builtin routines on other compilers. This patch adds clang support to enable those builtins. In partciular, the patch: - enables the transactional-execution feature by default on zEC12 - allows to override presence of that feature via the -mhtm/-mno-htm options - adds a predefined macro __HTM__ if the feature is enabled - adds support for the transactional-execution GCC builtins - adds Sema checking to verify the __builtin_tabort abort code - adds the s390intrin.h header file (for GCC compatibility) - adds s390 sections to the htmintrin.h and htmxlintrin.h header files Since this is first use of target-specific intrinsics on the platform, the patch creates the include/clang/Basic/BuiltinsSystemZ.def file and hooks it up in TargetBuiltins.h and lib/Basic/Targets.cpp. An associated LLVM patch adds the required LLVM IR intrinsics. For reference, the transactional-execution instructions are documented in the z/Architecture Principles of Operation for the zEC12: http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/download/DZ9ZR009.pdf The associated builtins are documented in the GCC manual: http://gcc.gnu.org/onlinedocs/gcc/S_002f390-System-z-Built-in-Functions.html The htmxlintrin.h intrinsics provided for compatibility with the IBM XL compiler are documented in the "z/OS XL C/C++ Programming Guide". llvm-svn: 233804
* Add sm_37 target to Clang for NVPTXEli Bendersky2015-03-311-0/+5
| | | | | | Support for this target was added in LLVM r233575 and r233583 llvm-svn: 233715
* Add driver support for Native Client SDKDerek Schuff2015-03-301-2/+4
| | | | | | | | | | | | | | Add Tool and ToolChain support for clang to target the NaCl OS using the NaCl SDK for x86-32, x86-64 and ARM. Includes nacltools::Assemble and Link which are derived from gnutools. They are similar to Linux but different enought that they warrant their own class. Also includes a NaCl_TC in ToolChains derived from Generic_ELF with library and include paths suitable for an SDK and independent of the system tools. Differential Revision: http://reviews.llvm.org/D8590 llvm-svn: 233594
* [SystemZ] Fix definition of IntMaxType / Int64TypeUlrich Weigand2015-03-301-0/+2
| | | | | | | | Like on other 64-bit platforms, Int64Type should be SignedLong on SystemZ, not SignedLongLong as per default. This could cause ABI incompatibilities in certain cases (e.g. name mangling). llvm-svn: 233544
* [mips] Add support for 'ZC' inline assembly memory constraint.Daniel Sanders2015-03-301-0/+21
| | | | | | | | | | | | | | Summary: Also add tests for 'R' and 'm'. Reviewers: atanasyan Reviewed By: atanasyan Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D8449 llvm-svn: 233542
* Make the msse4/mno-sse4 flags aliases of the maximum sse valuesEric Christopher2015-03-251-5/+0
| | | | | | | | | | | | | they enable/disable. This fixes two things: a) sse4 isn't actually a target feature, don't treat it as one. b) we weren't correctly disabling sse4.1 when we'd pass -mno-sse4 after enabling it, thus passing preprocessor directives and (soon) passing the function attribute as well when we shouldn't. llvm-svn: 233223
* Add Hardware Transactional Memory (HTM) SupportKit Barton2015-03-251-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds Hardware Transaction Memory (HTM) support supported by ISA 2.07 (POWER8). The intrinsic support is based on GCC one [1], with both 'PowerPC HTM Low Level Built-in Functions' and 'PowerPC HTM High Level Inline Functions' implemented. Along with builtins a new driver switch is added to enable/disable HTM instruction support (-mhtm) and a header with common definitions (mostly to parse the TFHAR register value). The HTM switch also sets a preprocessor builtin HTM. The HTM usage requires a recently newer kernel with PPC HTM enabled. Tested on powerpc64 and powerpc64le. This is send along a llvm patch to enabled the builtins and option switch. [1] https://gcc.gnu.org/onlinedocs/gcc/PowerPC-Hardware-Transactional-Memory-Built-in-Functions.html Phabricator Review: http://reviews.llvm.org/D8248 llvm-svn: 233205
* Create android x86_32 and x86_64 target infoTamas Berghammer2015-03-251-4/+40
| | | | | | | | | | | On android x86_32 the long double is only 64 bits (compared to 80 bits on linux x86_32) and on android x86_64 the long double is IEEEquad (compared to x87DoubleExtended on linux x86_64). This CL creates new TargetInfo classes for this targets to represent these differences. Differential revision: http://reviews.llvm.org/D8357 llvm-svn: 233177
* Move private classes into anonymous namespacesBenjamin Kramer2015-03-231-86/+1
| | | | | | Also merge anonymous namespaces in Targets.cpp a bit. NFC. llvm-svn: 232945
* MS ABI: Define _HAS_CHAR16_T_LANGUAGE_SUPPORT when appropriateDavid Majnemer2015-03-181-0/+3
| | | | | | | If we are in MSVC 2015 compatibility mode and C++11 language conformance is enabled, define _HAS_CHAR16_T_LANGUAGE_SUPPORT to 1. llvm-svn: 232615
* Basic: Update clang to reflect changes made to LLVM datalayoutDavid Majnemer2015-03-171-7/+9
| | | | | | | We now give x86-64 COFF targets a different mangling code, update clang to use it. llvm-svn: 232571
* [ARM] Add support for ARMV6K subtarget (Clang)Renato Golin2015-03-171-2/+3
| | | | | | | | | | | | | | | | | | | | | ARMv6K is another layer between ARMV6 and ARMV6T2. This is the Clang side of the changes. ARMV6 family LLVM implementation. +-------------------------------------+ | ARMV6 | +----------------+--------------------+ | ARMV6M (thumb) | ARMV6K (arm,thumb) | <- From ARMV6K and ARMV6M processors +----------------+--------------------+ have support for hint instructions | ARMV6T2 (arm,thumb,thumb2) | (SEV/WFE/WFI/NOP/YIELD). They can +-------------------------------------+ be either real or default to NOP. | ARMV7 (arm,thumb,thumb2) | The two processors also use +-------------------------------------+ different encoding for them. Patch by Vinicius Tinti. llvm-svn: 232469
* Under duress, move check for target support of __builtin_setjmp/Joerg Sonnenberger2015-03-111-0/+8
| | | | | | __builtin_longjmp to Sema as requested by John McCall. llvm-svn: 231986
* [PowerPC] ABI support for the QPX vector instruction setHal Finkel2015-03-111-3/+10
| | | | | | | | | | | | | | Support for the QPX vector instruction set, used on the IBM BG/Q supercomputer, has recently been added to the LLVM PowerPC backend. This vector instruction set requires some ABI modifications because the ABI on the BG/Q expects <4 x double> vectors to be provided with 32-byte stack alignment, and to be handled as native vector types (similar to how Altivec vectors are handled on mainline PPC systems). I've named this ABI variant elfv1-qpx, have made this the default ABI when QPX is supported, and have updated the ABI handling code to provide QPX vectors with the correct stack alignment and associated register-assignment logic. llvm-svn: 231960
* Add target information for CloudABI on x86-64.Ed Schouten2015-03-111-0/+24
| | | | | | | | | | | CloudABI can be identified by the __CloudABI__ preprocessor definition. The system uses ELF executables. CloudABI uses Unicode 7.0.0 for the encoding of wchar_t. As Unicode 7.0.0 is synchronized with ISO/IEC 10646:2012 (released on 2012-06-01), __STDC_ISO_10646__ is defined as 201206L. llvm-svn: 231912
* Add Clang support for PPC cryptography builtinsNemanja Ivanovic2015-03-041-1/+19
| | | | | | Review: http://reviews.llvm.org/D7951 llvm-svn: 231291
* Support __attribute__((availability)) on Android.Dan Albert2015-03-031-1/+6
| | | | | | | | | | | | Reviewers: srhines Reviewed By: srhines Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D7929 llvm-svn: 231092
* Add __ARM_DWARF_EH__ to signify the use of Itanium ABI for unwind instructions.Renato Golin2015-02-271-2/+14
| | | | | | | | Equally to NetBSD, Bitrig will be using .eh_frame unwinding on ARM. Patch by Patrick Wildt. llvm-svn: 230763
* AMDGCN: Define cl_khr_fp64 when compiling OpenCL programsTom Stellard2015-02-271-0/+2
| | | | llvm-svn: 230761
* Win64: Silently ignore __stdcall, __fastcall, and __thiscallReid Kleckner2015-02-261-4/+16
| | | | | | | | | | MSVC doesn't warn on this. Users are expected to apply the WINAPI macro to functions passed by pointer to the Win32 API, and this macro expands to __stdcall. This means we end up with a lot of useless noisy warnings about ignored calling conventions when compiling code with clang for Win64. llvm-svn: 230668
* Add support for generating MIPS legacy NaNPetar Jovanovic2015-02-261-0/+4
| | | | | | | | | | | Currently, the NaN values emitted for MIPS architectures do not cover non-IEEE754-2008 compliant case. This change fixes the issue. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D7882 llvm-svn: 230653
* Remove some unused includes of llvm/IR headers from parts of Clang that reallyRichard Smith2015-02-261-1/+0
| | | | | | shouldn't depend on LLVM IR. llvm-svn: 230586
* [Mips] Support mips32r3, mips32r5, mips64r3, mips64r5 MIPS ISA namesSimon Atanasyan2015-02-201-0/+12
| | | | | | | | | The patch teaches the clang's driver to understand new MIPS ISA names, pass appropriate options to the assembler, defines corresponding macros etc http://reviews.llvm.org/D7737 llvm-svn: 230092
* Change representation of member function pointers for MIPS targetsZoran Jovanovic2015-02-181-1/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D7148 llvm-svn: 229680
* [ARM] Add missing M/R class CPUsBradley Smith2015-02-181-7/+9
| | | | | | | | | | | | Add some of the missing M and R class Cortex CPUs, namely: Cortex-M0+ (called Cortex-M0plus for GCC compatibility) Cortex-M1 SC000 SC300 Cortex-R5 llvm-svn: 229661
* Remove the ABI from the target features. It's obsoleted byEric Christopher2015-02-171-3/+0
| | | | | | the -target-abi use and those features don't exist anymore. llvm-svn: 229526
* Preprocessor: support __BIGGEST_ALIGNMENT__ macroTim Northover2015-02-061-2/+2
| | | | | | | | | | | For compatibility with GCC (and because it's generally helpful information otherwise inaccessible to the preprocessor). This appears to be canonically the alignment of max_align_t (e.g. on i386, __BIGGEST_ALIGNMENT__ is 4 even though vector types will be given greater alignment). Patch mostly by Mats Petersson llvm-svn: 228367
* Teaches the Clang driver to accept Cortex-A72Renato Golin2015-02-041-4/+4
| | | | | | | | | A previous commit added Cortex-A72 to LLVM, this teaches Clang to accept it as well. Patch by Ranjeet Singh. llvm-svn: 228141
* Windows: Fix _CPPUNWIND definition to follow -fcxx-exceptionsReid Kleckner2015-01-301-1/+1
| | | | | | | This is consistent with how we interpret the MSVC /EH flag, which controls -fcxx-exceptions. llvm-svn: 227616
* [mips] Pass ABI name via -target-abi instead of target-featuresDaniel Sanders2015-01-301-8/+0
| | | | | | | | | | | | | | Patch by Vladimir Medic Reviewers: echristo, atanasyan, dsanders Reviewed By: atanasyan, dsanders Subscribers: llvm-commits, echristo, atanasyan Differential Revision: http://reviews.llvm.org/D6091 llvm-svn: 227583
* Remove support for pnaclcall attributeDerek Schuff2015-01-281-5/+0
| | | | | | | | | | | | | | | | | | Summary: It was used for interoperability with PNaCl's calling conventions, but it's no longer needed. Also Remove NaCl*ABIInfo which just existed to delegate to either the portable or native ABIInfo, and remove checkCallingConvention which was now a no-op override. Reviewers: jvoung Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D7206 llvm-svn: 227362
* R600: Use a Southern Islands GPU as the default for the amdgcn targetTom Stellard2015-01-281-2/+9
| | | | llvm-svn: 227315
* Begin to teach clang about the PS4.Alex Rosenberg2015-01-271-0/+29
| | | | llvm-svn: 227194
* [Mips] Fix type of 64-bit integer in case of MIPS N64 ABISimon Atanasyan2015-01-221-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D7127 llvm-svn: 226877
* Re-apply "r226548 - Introduce SPIR calling conventions" reverted in r226558.Alexander Kornienko2015-01-201-0/+9
| | | | | | | | | | | | | | | | | | | | | | | The test was fixed after a discussion with the revision author: the check pattern was made more flexible as the "%call" part is not what we actually want to check strictly there. The original patch description: === Introduce SPIR calling conventions. This implements Section 3.7 from the SPIR 1.2 spec: SPIR kernels should use "spir_kernel" calling convention. Non-kernel functions use "spir_func" calling convention. All other calling conventions are disallowed. The patch works only for OpenCL source. Any other uses will need to ensure that kernels are assigned the spir_kernel calling convention correctly. === llvm-svn: 226561
* Reverting r226548 as one of the tests fails in some configurations.Alexander Kornienko2015-01-201-9/+0
| | | | | | | | | | | | | | | | | | | | | | Here's the fail log from our internal setup: === .../tools/clang/clang -cc1 -internal-isystem .../tools/clang/staging/include -nostdsysteminc .../tools/clang/test/CodeGenOpenCL/spir-calling-conv.cl -triple spir-unknown-unknown -emit-llvm -o - FileCheck .../tools/clang/test/CodeGenOpenCL/spir-calling-conv.cl .../tools/clang/test/CodeGenOpenCL/spir-calling-conv.cl:11:12: error: expected string not found in input // CHECK: %call = tail call spir_func i32 @get_dummy_id(i32 0) ^ <stdin>:6:52: note: scanning from here define spir_kernel void @foo(i32 addrspace(1)* %A) #0 { ^ <stdin>:7:2: note: possible intended match here %1 = tail call spir_func i32 @get_dummy_id(i32 0) #2 ^ === Here's a failure on a public CI server: http://lab.llvm.org:8080/green/job/clang-stage2-configure-Rlto_check/1183/ llvm-svn: 226558
* Introduce SPIR calling conventions.Sameer Sahasrabuddhe2015-01-201-0/+9
| | | | | | | | | | | | | | This implements Section 3.7 from the SPIR 1.2 spec: SPIR kernels should use "spir_kernel" calling convention. Non-kernel functions use "spir_func" calling convention. All other calling conventions are disallowed. The patch works only for OpenCL source. Any other uses will need to ensure that kernels are assigned the spir_kernel calling convention correctly. llvm-svn: 226548
* AArch64: implement AAPCS layout rules for bit-fields.Tim Northover2015-01-161-0/+7
| | | | llvm-svn: 226294
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