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* [Mips] Define macros `__mips_isa_rev` in case of mips32r6/mips64r6 optionsSimon Atanasyan2015-01-151-0/+4
| | | | llvm-svn: 226136
* PR22208: On FreeBSD systems, __STDC_MB_MIGHT_NEQ_WC__ is expected to be definedRichard Smith2015-01-131-0/+6
| | | | | | | | | | | even though every basic source character literal has the same numerical value as a narrow or wide character literal. It appears that the FreeBSD folks are trying to use this macro to mean something other than what the relevant standards say it means, but their usage is conforming, so put up with it. llvm-svn: 225751
* [mips] Explain why we need to always clobber for MIPS inline asm. NFC.Toma Tabacu2015-01-121-0/+21
| | | | llvm-svn: 225632
* R600: Handle amdgcn tripleTom Stellard2015-01-061-0/+1
| | | | | | For now there is no difference between amdgcn and r600. llvm-svn: 225294
* Sema: analyze I,J,K,M,N,O constraintsSaleem Abdulrasool2015-01-061-0/+55
| | | | | | | | | | Add additional constraint checking for target specific behaviour for inline assembly constraints. We would previously silently let all arguments through for these constraints. In cases where the constraints were violated, we could end up failing to select instructions and triggering assertions or worse, silently ignoring instructions. llvm-svn: 225244
* Fix formatting. NFC.Craig Topper2014-12-271-2/+2
| | | | llvm-svn: 224877
* Update for llvm front end change and use the TargetOptions structEric Christopher2014-12-181-5/+0
| | | | | | for ABI. llvm-svn: 224493
* Make sure that arm-linux-gnu is still the apcs-gnu ABI when weEric Christopher2014-12-181-0/+3
| | | | | | | | | | | | use clang -cc1 matching the front end and backend. Fix up a couple of tests that were testing aapcs for arm-linux-gnu. The test that removes the aapcs abi calling convention removes them because the default triple matches what the backend uses for the calling convention there and so it doesn't need to be explicitly stated - see the code in TargetInfo.cpp. llvm-svn: 224491
* [mips] Always clobber $1 for MIPS inline asm.Toma Tabacu2014-12-171-2/+1
| | | | | | | | | | | | | | | | | | | | Summary: Because GCC doesn't use $1 for code generation, inline assembly code can use $1 without having to add it to the clobbers list. LLVM, on the other hand, does not shy away from using $1, and this can cause conflicts with inline assembly which assumes GCC-like code generation. A solution to this problem is to make Clang automatically clobber $1 for all MIPS inline assembly. This is not the optimal solution, but it seems like a necessary compromise, for now. Reviewers: dsanders Reviewed By: dsanders Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D6638 llvm-svn: 224428
* Re-work the Clang system for classifying Intel x86 CPUs to use theirChandler Carruth2014-12-091-38/+71
| | | | | | | | | | | | | | | | | | | | | | | | basic microarchitecture names, and add support (with tests) for parsing all of the masic microarchitecture names for CPUs documented to be accepted by GCC with -march. I didn't go back through the 32-bit-only old microarchitectures, but this at least brings the recent architecture names up to speed. This is essentially the follow-up to the LLVM commit r223769 which did similar cleanups for the LLVM CPUs. One particular benefit is that you can now use -march=westmere in Clang and get the LLVM westmere processor which is a different ISA variant (!) and so quite significant. Much like with r223769, I would appreciate the Intel folks carefully thinking about the macros defined, names used, etc for the atom chips and newest primary x86 chips. The current patterns seem quite strange to me, especially here in Clang. Note that I haven't replicated the per-microarchitecture macro defines provided by GCC. I'm really opposed to source code using these rather than using ISA feature macros. llvm-svn: 223776
* Have the driver and the target code agree on what the default ABIEric Christopher2014-12-051-1/+36
| | | | | | | | | is for each machine. Fix up darwin tests that were testing for aapcs on armv7-ios when the actual ABI is apcs. Should be no user visible change without -cc1. llvm-svn: 223429
* CUDA host device code with two code pathsReid Kleckner2014-12-031-8/+41
| | | | | | | | | | | | | | | | | | | | | | | Summary: Allow CUDA host device functions with two code paths using __CUDA_ARCH__ to differentiate between code path being compiled. For example: __host__ __device__ void host_device_function(void) { #ifdef __CUDA_ARCH__ device_only_function(); #else host_only_function(); #endif } Patch by Jacques Pienaar. Reviewed By: rnk Differential Revision: http://reviews.llvm.org/D6457 llvm-svn: 223271
* Make le64 DescriptionString consistent with other targets.JF Bastien2014-12-021-1/+1
| | | | | | | | | | | | | | | Summary: In particular, remove the defaults and reorder fields so it matches the result of DataLayout::getStringDescription(). Change by David Neto. Reviewers: dschuff, sdt Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D6482 llvm-svn: 223140
* Update R600 address space map to include genericMatt Arsenault2014-12-011-2/+1
| | | | llvm-svn: 223046
* [OpenCL] Generic address space has been added in OpenCL v2.0.Anastasia Stulova2014-11-261-0/+7
| | | | | | | | | | To support it in the frontend, the following has been added: - generic address space type attribute; - documentation for the OpenCL address space attributes; - parsing of __generic(generic) keyword; - test code for the parser and diagnostics. llvm-svn: 222831
* [ARM] Define __ARM_FEATURE_DSP macro for CPUs that have DSP instructionsSergey Dmitrouk2014-11-251-0/+7
| | | | | | | | | | | | | | | | | Summary: This resolves [[ http://llvm.org/bugs/show_bug.cgi?id=17391 | PR17391 ]]. GCC's sources were used as a guide (couldn't find much information in ARM documentation). Reviewers: doug.gregor, asl Reviewed By: asl Subscribers: asl, aemerson, cfe-commits Differential Revision: http://reviews.llvm.org/D6339 llvm-svn: 222741
* Fix 80-column violations, trailing whitespace, comment text.Eric Christopher2014-11-181-63/+74
| | | | llvm-svn: 222269
* Basic: tweak commentSaleem Abdulrasool2014-11-171-0/+1
| | | | | | | Add a missing surrounding brace for doxygen group. This messes with pair jumping in vim and is annoying. NFC. llvm-svn: 222155
* Remove some redundant virtual specifiers on overriden functions.David Blaikie2014-11-141-7/+7
| | | | llvm-svn: 222024
* Remove -fseh-exceptions in favor of checking the tripleReid Kleckner2014-11-141-0/+4
| | | | | | | | | This option was misleading because it looked like it enabled the language feature of SEH (__try / __except), when this option was really controlling which EH personality function to use. Mingw only supports SEH and SjLj EH on x86_64, so we can simply do away with this flag. llvm-svn: 221963
* Hook up FreeBSD AArch64 supportEd Maste2014-11-131-0/+4
| | | | | | Patch from Andrew Turner. llvm-svn: 221900
* Introduce a SanitizerKind enum to LangOptions.Alexey Samsonov2014-11-071-1/+2
| | | | | | | | | | | | | Use the bitmask to store the set of enabled sanitizers instead of a bitfield. On the negative side, it makes syntax for querying the set of enabled sanitizers a bit more clunky. On the positive side, we will be able to use SanitizerKind to eventually implement the new semantics for -fsanitize-recover= flag, that would allow us to make some sanitizers recoverable, and some non-recoverable. No functionality change. llvm-svn: 221558
* Remove references to the cortex-a9-mp CPU.Charlie Turner2014-11-061-3/+2
| | | | | | | | | | This CPU definition is redundant. The Cortex-A9 is defined as supporting multiprocessing extensions. Remove references to this CPU. This CPU was recently removed from LLVM. See http://reviews.llvm.org/D6057 Change-Id: I62ae7cc656fcae54fbaefc4b6976e77e694a8678 llvm-svn: 221458
* [X86] Slightly refactor default features for AMD bdver cpus (NFC). Also add ↵Andrea Di Biagio2014-11-061-12/+7
| | | | | | | | | | | | | | | | | | | missing checks to test for target features. This patch simplifies how default target features are set for AMD bdver2 and bdver1. In particular, method 'getDefaultFeatures' now implements a fallthrough from case 'CK_BDVER2' to case 'CK_BDVER1'. That is because 'bdver2' has the same features available in bdver1 plus BMI, FMA, F16C and TBM. This patch also adds missing checks for predefined macros in test predefined-arch-macros.c. In the case of BTVER2, the test now also checks for F16C, BMI and PCLMUL. In the case of BDVER3 and BDVER4, the test now also checks for the presence of FSGSBASE. Differential Revision: http://reviews.llvm.org/D6134 llvm-svn: 221449
* [X86] Use fallthroughs to reduce the number of calls to setFeatureEnabled ↵Craig Topper2014-11-061-98/+45
| | | | | | for different CPUs. llvm-svn: 221437
* [x86] Add cx16 feature to KNL, SKX, and CoreAVXi CPUs.Craig Topper2014-11-031-2/+5
| | | | llvm-svn: 221132
* [x86] Realphabetize the feature string decoding function since it was mostly ↵Craig Topper2014-11-031-4/+4
| | | | | | in alphabetical order. llvm-svn: 221131
* Add FSGSBASE intrinsics to x86 intrinsic headers.Craig Topper2014-11-031-7/+24
| | | | llvm-svn: 221130
* [PowerPC] Change PPCTargetInfo::hasFeature() to use StringSwitchBill Schmidt2014-11-021-3/+5
| | | | | | Implement post-commit comment on r220989 from Eric Christopher. llvm-svn: 221099
* Implement IRGen for the x86 vectorcall conventionReid Kleckner2014-10-311-0/+2
| | | | | | | | | | | | | | | The most complex aspect of the convention is the handling of homogeneous vector and floating point aggregates. Reuse the homogeneous aggregate classification code that we use on PPC64 and ARM for this. This convention also has a C mangling, and we apparently implement that in both Clang and LLVM. Reviewed By: majnemer Differential Revision: http://reviews.llvm.org/D6063 llvm-svn: 221006
* [PowerPC] Initial VSX intrinsic support, with min/max for vector doubleBill Schmidt2014-10-311-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have initial support for VSX, we can begin adding intrinsics for programmer access to VSX instructions. This patch performs the necessary enablement in the front end, and tests it by implementing intrinsics for minimum and maximum using the vector double data type. The main change in the front end is to no longer disallow "vector" and "double" in the same declaration (lib/Sema/DeclSpec.cpp), but "vector" and "long double" must still be disallowed. The new intrinsics are accessed via vec_max and vec_min with changes in lib/Headers/altivec.h. Note that for v4f32, we already access corresponding VMX builtins, but with VSX enabled we should use the forms that allow all 64 vector registers. The new built-ins are defined in include/clang/Basic/BuiltinsPPC.def. I've added a new test in test/CodeGen/builtins-ppc-vsx.c that is similar to, but much smaller than, builtins-ppc-altivec.c. This allows us to test VSX IR generation without duplicating CHECK lines for the existing bazillion Altivec tests. Since vector double is now legal when VSX is available, I've modified the error message, and changed where we test for it and for vector long double, since the target machine isn't visible in the old place. This serendipitously removed a not-pertinent warning about 'long' being deprecated when used with 'vector', when "vector long double" is encountered and we just want to issue an error. The existing tests test/Parser/altivec.c and test/Parser/cxx-altivec.cpp have been updated accordingly, and I've added test/Parser/vsx.c to verify that "vector double" is now legitimate with VSX enabled. There is a companion patch for LLVM. llvm-svn: 220989
* Add frontend support for __vectorcallReid Kleckner2014-10-241-2/+3
| | | | | | | | | | | | | Wire it through everywhere we have support for fastcall, essentially. This allows us to parse the MSVC "14" CTP headers, but we will miscompile them because LLVM doesn't support __vectorcall yet. Reviewed By: Aaron Ballman Differential Revision: http://reviews.llvm.org/D5808 llvm-svn: 220573
* Switch C compilations to C11 by default.Richard Smith2014-10-201-3/+3
| | | | | | | | This is long-since overdue, and matches GCC 5.0. This should also be backwards-compatible, because we already supported all of C11 as an extension in C99 mode. llvm-svn: 220244
* Use the triple's isiOS() method instead of checking the value directly. NFC.Bob Wilson2014-10-191-1/+1
| | | | llvm-svn: 220158
* As requested by Matt Thomas, use long long for intmax_t and int64_t onJoerg Sonnenberger2014-10-151-0/+4
| | | | | | PPC64/NetBSD. llvm-svn: 219839
* Set ABI and DescriptionString first to reduce OS specific logic.Joerg Sonnenberger2014-10-151-10/+13
| | | | | | Use switch for FreeBSD check to allow easier extension. llvm-svn: 219838
* ARM: remove ARM/Thumb distinction for preferred alignment.Tim Northover2014-10-141-60/+30
| | | | | | | | | | | | Thumb1 has legitimate reasons for preferring 32-bit alignment of types i1/i8/i16, since the 16-bit encoding of "add rD, sp, #imm" requires #imm to be a multiple of 4. However, this is a trade-off betweem code size and RAM usage; the DataLayout string is not the best place to represent it even if desired. So this patch removes the extra Thumb requirements, hopefully making ARM and Thumb completely compatible in this respect. llvm-svn: 219735
* ARM: set preferred aggregate alignment to 32 universally.Tim Northover2014-10-141-7/+7
| | | | | | | | | | | Before, ARM and Thumb mode code had different preferred alignments, which could lead to some rather unexpected results. There's justification for reducing it from the default 64-bits (wasted space), but I don't think there is for going below 32-bits. There's no actual ABI change here, just to reassure people. llvm-svn: 219720
* Adds support for the Cortex-A17 processor to ClangRenato Golin2014-10-131-3/+3
| | | | | | Patch by Matthew Wahab. llvm-svn: 219607
* [PowerPC] Reduce names from Power8Vector to P8VectorBill Schmidt2014-10-101-4/+4
| | | | | | Per Hal Finkel's review, improving typability of some variable names. llvm-svn: 219515
* [PowerPC] Add feature for Power8 vector extensionsBill Schmidt2014-10-101-1/+9
| | | | | | | | | | | | | | | | | | The current VSX feature for PowerPC specifies availability of the VSX instructions added with the 2.06 architecture version. With 2.07, the architecture adds new instructions to both the Category:Vector and Category:VSX instruction sets. Additionally, unaligned vector storage operations have improved performance. This patch adds a feature to provide access to the new instructions and performance capabilities of Power8. For compatibility with GCC, the feature is controlled via a new -mpower8-vector switch, and the feature causes the __POWER8_VECTOR__ builtin define to be generated by the preprocessor. There is a companion patch for llvm being committed at the same time. llvm-svn: 219502
* Adds 'override' to overriding methods. NFC.Fariborz Jahanian2014-10-011-13/+13
| | | | | | These were uncoveredby my yet undelivered patch. llvm-svn: 218774
* [ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DPOliver Stannard2014-10-011-3/+3
| | | | | | | | | The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be modeled using the same target feature, and all double-precision operations are already disabled by the fp-only-sp target features. llvm-svn: 218748
* Make sure aggregates are properly alligned on MSP430.Job Noorman2014-09-301-1/+1
| | | | llvm-svn: 218666
* Silence a signed/unsigned mismatch warning from MSVC; NFC.Aaron Ballman2014-09-191-1/+1
| | | | llvm-svn: 218121
* [x86] Enable broadwell target in clang.Robert Khasanov2014-09-191-5/+37
| | | | | | Added -madx option llvm-svn: 218116
* [X86, inlineasm] Do not allow using constraint 'x' for a variable larger thanAkira Hatanaka2014-09-181-1/+2
| | | | | | | | 128-bit unless the target CPU supports AVX. rdar://problem/11846140 llvm-svn: 218082
* [X86, inline-asm] Allow 256-bit wide operands for the 'x' constraintsHans Wennborg2014-09-181-1/+2
| | | | | | | The 'x' constraint is for "any SSE register", and GCC seems to include the 256-bit ymm registers in that concept. llvm-svn: 218073
* [X86, inlineasm] Check that the output size is correct for the given constraint.Akira Hatanaka2014-09-181-3/+23
| | | | llvm-svn: 218064
* Basic: use hex string for __ARM_FP macroSaleem Abdulrasool2014-09-181-1/+2
| | | | | | | The ARM ACLE describes the values as hex constants rather than numeric constants; follow suit. Address post-commit review comments from Jon Roelofs. llvm-svn: 218009
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