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* Add the _CALL_LINUX preprocessor define for ppc linux platforms.Eric Christopher2017-03-251-0/+6
| | | | | | | | This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but our ppc suppport post-dates this and it should work on all linux platforms. It is guaranteed to work on all elfv2 platforms. llvm-svn: 298765
* __BIGGEST_ALIGNMENT__ has always been 16 on all power platforms ratherEric Christopher2017-03-251-2/+1
| | | | | | than the default of 8 in clang, fix and update tests accordingly. llvm-svn: 298761
* Add preprocessor defines for a bare powerpc64le triple/cpu.Eric Christopher2017-03-251-62/+72
| | | | | | | The le triple didn't exist until power8, so use that as a default (this also matches what gcc does). llvm-svn: 298759
* Move setting of LangOpts based on target flags out of CompilerInstanceEric Christopher2017-03-221-0/+7
| | | | | | | | | and into TargetInfo::adjust so that it gets called in more places throughout the compiler (AST serialization in particular). Should fix PPC modules after removing of faltivec. llvm-svn: 298487
* Remove the -faltivec alias option and replace it with -maltivec everywhere.Eric Christopher2017-03-211-19/+22
| | | | | | | | | | | The alias was only ever used on darwin and had some issues there, and isn't used in practice much. Also fixes a problem with -mno-altivec not turning off -maltivec. Also add a diagnostic for faltivec/fno-altivec that directs users to use maltivec options and include the altivec.h file explicitly. llvm-svn: 298449
* Turn on HTM on power8 and later (including powerpc64le) since it'sEric Christopher2017-03-201-0/+5
| | | | | | available by default on those cpus and configurations. llvm-svn: 298307
* [Hexagon] Recognize hexagonv62 as a valid target CPUKrzysztof Parzyszek2017-03-141-0/+4
| | | | llvm-svn: 297778
* AMDGPU: Make 0 the private nullptr valueMatt Arsenault2017-03-131-1/+1
| | | | | | | | | | | | We can't actually pretend that 0 is valid for address space 0. r295877 added a workaround to stop allocating user objects there, so we can use 0 as the invalid pointer. Some of the tests seemed to be using private as the non-0 null test address space, so add copies using local to make sure this is still stressed. llvm-svn: 297659
* [AMDGPU] Add builtin functions readlane ds_permute mov_dppYaxun Liu2017-03-101-0/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D30551 llvm-svn: 297436
* [DebugInfo] Add address space when creating DIDerivedTypesKonstantin Zhuravlyov2017-03-081-0/+26
| | | | | | Differential Revision: https://reviews.llvm.org/D29671 llvm-svn: 297321
* Set the Int64Type / IntMaxType types correctly for OpenBSD/mips64Brad Smith2017-03-061-1/+5
| | | | llvm-svn: 297098
* Migrate all of aarch64-linux-gnu to \01_mcount instead of just when passing ↵Eric Christopher2017-02-281-2/+3
| | | | | | | | along gnueabi as this matches both gcc and what the kernel expects. More of PR27311 llvm-svn: 296490
* Set ABIs correctly for OpenBSD/arm; soft float and aapcs-linux.Brad Smith2017-02-281-0/+2
| | | | llvm-svn: 296430
* AMDGPU: Add fmed3 half builtinMatt Arsenault2017-02-221-0/+3
| | | | llvm-svn: 295874
* Hook up OpenBSD AArch64 supportBrad Smith2017-02-211-1/+4
| | | | llvm-svn: 295786
* [mips] Define macros related to -mabicalls in the preprocessorSimon Dardis2017-02-211-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Historically, NetBSD, FreeBSD and OpenBSD have defined the macro ABICALLS in the preprocessor when -mabicalls is in effect. Mainline GCC later defined __mips_abicalls when -mabicalls is in effect. This patch teaches the preprocessor to define these macros when appropriate. NetBSD does not require the ABICALLS macro. This resolves PR/31694. Thanks to Sean Bruno for highlighting this issue! Reviewers: slthakur, seanbruno Reviewed By: seanbruno Subscribers: joerg, brad, emaste, seanbruno, cfe-commits Differential Revision: https://reviews.llvm.org/D29032 llvm-svn: 295728
* Enable support for __float128 in Clang on OpenBSD/X86Brad Smith2017-02-201-3/+5
| | | | | | | /usr/local/include/c++/4.9.4/type_traits:279:39: error: __float128 is not supported on this target llvm-svn: 295635
* AMDGPU: Add gfx900 and gfx901 processorsMatt Arsenault2017-02-181-1/+4
| | | | llvm-svn: 295556
* Add a definition for __STRUCT_PARM_ALIGN__ for elfv2 and 64-bit darwin ↵Eric Christopher2017-02-151-0/+5
| | | | | | platforms to match what other compilers produce. llvm-svn: 295156
* [AVR] Fix __AVR_xxx macro definitions; authored by Peter WuDylan McKay2017-02-111-238/+238
| | | | | | | | | | | | | | | | | | Summary: The -mmcu option for GCC sets macros like __AVR_ATmega328P__ (with the trailing underscores), be sure to include these underscores for Clangs -mcpu option. See "AVR Built-in Macros" in https://gcc.gnu.org/onlinedocs/gcc/AVR-Options.html Reviewers: jroelofs, dylanmckay Reviewed By: jroelofs, dylanmckay Subscribers: efriedma, cfe-commits Differential Revision: https://reviews.llvm.org/D29817 llvm-svn: 294869
* Temporarily revert "For X86-64 linux and PPC64 linux align int128 to 16 bytes."Eric Christopher2017-02-101-40/+10
| | | | | | | | | until we can get better TargetMachine::isCompatibleDataLayout to compare - otherwise we can't code generate existing bitcode without a string equality data layout. This reverts commit r294703. llvm-svn: 294708
* For X86-64 linux and PPC64 linux align int128 to 16 bytes.Eric Christopher2017-02-101-10/+40
| | | | | | | | | | For other platforms we should find out what they need and likely make the same change, however, a smaller additional change is easier for platforms we know have it specified in the ABI. clang support for r294702 llvm-svn: 294703
* Add support for armv7ve flag in clang (PR31358).George Burgess IV2017-02-091-0/+2
| | | | | | | | | | | This is a followup change to add v7ve support to clang for gcc compatibility. Please see r294661. Patch by Manoj Gupta. Differential Revision: https://reviews.llvm.org/D29773 llvm-svn: 294662
* [X86] Clzero flag addition and inclusion under znver1Craig Topper2017-02-091-0/+7
| | | | | | | | | | | | | 1. Adds the command line flag for clzero. 2. Includes the clzero flag under znver1. 3. Defines the macro for clzero. 4. Adds a new file which has the intrinsic definition for clzero instruction. Patch by Ganesh Gopalasubramanian with some additional tests from me. Differential revision: https://reviews.llvm.org/D29386 llvm-svn: 294559
* [X86] Add -mprefetchwt1/-mno-prefetchwt1 command line options and ↵Craig Topper2017-02-081-0/+2
| | | | | | __PREFETCHWT1__ define to match gcc. llvm-svn: 294424
* [X86] Add -msgx/-mno-sgx command line options and __SGX__ define to match gcc.Craig Topper2017-02-081-0/+2
| | | | llvm-svn: 294423
* [X86] Add -mmpx/-mno-mpx command line options and __MPX__ define to match gcc.Craig Topper2017-02-081-0/+2
| | | | llvm-svn: 294419
* [X86] Add -mclwb/-mno-clwb command line arguments and __CLWB__ define to ↵Craig Topper2017-02-081-0/+2
| | | | | | | | match gcc. In the future, we should also add a clwb intrinsic to the backend, a frontend builtin, and an instrinsic header file. llvm-svn: 294416
* [X86] Remove 'umip' feature flag.Craig Topper2017-02-081-5/+0
| | | | | | This feature flag indicates that the processor has support for removing certain instructions from user mode software. But the feature flag by itself doesn't indicate if the support is enabled in the OS. The affected instructions aren't even instructions the compiler would emit. So I don't think think this feature flag should be in the compiler. llvm-svn: 294414
* [X86] Add -mclflushopt/-mno-clflushopt command line support and ↵Craig Topper2017-02-081-0/+2
| | | | | | __CLFLUSHOPT__ define to match gcc. llvm-svn: 294411
* Use LLVM_FALLTHROUGH instead of FALLTHROUGH comments.Craig Topper2017-02-081-13/+13
| | | | llvm-svn: 294404
* [X86] Remove PCOMMIT feature support since Intel has deprecated this ↵Craig Topper2017-02-081-5/+0
| | | | | | | | instruction with no plans to release products with it. Intel's documentation for the deprecation https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction llvm-svn: 294403
* Revert "Basic: match GCC behaviour for SuS macro"Saleem Abdulrasool2017-02-071-15/+15
| | | | | | | This reverts commit SVN r294148. Seems that it was mistaken, and GCC does still define `__unix` and `unix` when in GNU mode. llvm-svn: 294332
* Revert "Revert "[AVR] Allow specifying the CPU on the command line""Dylan McKay2017-02-071-0/+293
| | | | | | This reverts commit 7ac30e0f839fdab6d723ce2ef6a5b7a4cf03d150. llvm-svn: 294282
* [SystemZ] Provide predefined __ARCH__ and __VX__ macrosUlrich Weigand2017-02-061-0/+11
| | | | | | | | | | | | GCC 7 will predefine two new macros on s390x: - __ARCH__ indicates the ISA architecture level - __VX__ indicates that the vector facility is available This adds those macros to clang as well to ensure continued compatibility with GCC. llvm-svn: 294197
* Revert "[AVR] Allow specifying the CPU on the command line"Diana Picus2017-02-061-293/+0
| | | | | | This reverts commit r294177. It seems to have broken some buildbots. llvm-svn: 294180
* [AVR] Allow specifying the CPU on the command lineDylan McKay2017-02-061-0/+293
| | | | | | | | | | | | | | | | | | Summary: This tells clang about all of the different AVR microcontrollers. It also adds code to define the correct preprocessor macros for each device. Reviewers: jroelofs, asl Reviewed By: asl Subscribers: asl, cfe-commits Differential Revision: https://reviews.llvm.org/D28346 llvm-svn: 294177
* [AVR] Add support for the full set of inline asm constraintsDylan McKay2017-02-061-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Previously the method would simply return false, causing every single inline assembly constraint to trigger a compile error. This adds inline assembly constraint support for the AVR target. This patch is derived from the code in AVRISelLowering::getConstraintType. More details can be found on the AVR-GCC reference wiki http://www.nongnu.org/avr-libc/user-manual/inline_asm.html Reviewers: jroelofs, asl Reviewed By: asl Subscribers: asl, ahatanak, saaadhu, cfe-commits Differential Revision: https://reviews.llvm.org/D28344 llvm-svn: 294176
* Basic: match GCC behaviour for SuS macroSaleem Abdulrasool2017-02-051-15/+15
| | | | | | | | GCC does not generate `__unix` nor `unix` macros. The latter already intrudes into the user's namespace and should be avoided. Use the canonical spelling of `__unix__` across all the targets. llvm-svn: 294148
* AMDGPU: Update for changed subtarget feature nameMatt Arsenault2017-01-231-3/+3
| | | | llvm-svn: 292838
* [Basic] Remove the 32-bit x86 and ARM targets for FuchsiaPetr Hosek2017-01-201-6/+0
| | | | | | | | The 32-bit architectures are no longer supported by Fuchsia. Differential Revision: https://reviews.llvm.org/D28974 llvm-svn: 292671
* [WebAssembly] Add minimal support for the new wasm object format triple.Dan Gohman2017-01-171-2/+10
| | | | llvm-svn: 292269
* Ensure that clang -pthread creates the right macro. -D_POSIX_THREADSJoerg Sonnenberger2017-01-161-1/+1
| | | | | | seems to have been a C&P error from old GCC specs for OpenBSD. llvm-svn: 292119
* AMD family 17h (znver1) enablementCraig Topper2017-01-101-0/+38
| | | | | | | | | | | | | | | | | | | | | | | Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This is linked to llvm review item https://reviews.llvm.org/D28017 Patch by Ganesh Gopalasubramanian. Additional test cases added by Craig Topper. Reviewers: RKSimon, craig.topper Subscribers: cfe-commits, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28018 llvm-svn: 291544
* [CUDA] Let NVPTX inherit the host's calling conventions.Justin Lebar2017-01-051-0/+10
| | | | | | | | | | | | | | | | | | | | Summary: When compiling device code, we may still see host code with explicit calling conventions. NVPTX needs to claim that it supports these CCs, so that (a) we don't raise noisy warnings, and (b) we don't break existing code which relies on the existence of these CCs when specializing templates. (If a CC doesn't exist, clang ignores it, so two template specializations which are different only insofar as one specifies a CC are considered identical and therefore are an error if that CC is not supported.) Reviewers: tra Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D28323 llvm-svn: 291136
* [CUDA] More correctly inherit primitive types from the host during device ↵Justin Lebar2017-01-051-33/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | compilation. Summary: CUDA lets users share structs between the host and device, so for that and other reasons, primitive types such as ptrdiff_t should be the same on both sides of the compilation. Our code to do this wasn't entirely successful. In particular, we did a bunch of work during the NVPTXTargetInfo constructor, only to override it in the NVPTX{32,64}TargetInfo constructors. It worked well enough on Linux and Mac, but Windows is LLP64, which is different enough to break it. This patch removes the NVPTX{32,64}TargetInfo classes entirely and fixes the bug described above. Reviewers: tra Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D28322 llvm-svn: 291135
* [AVR] Revert the functional part of r291083Dylan McKay2017-01-051-2/+1
| | | | | | | As Senthil points out, this is unnecessary as we already have these registers in AddlRegNames. llvm-svn: 291090
* [AVR] Support r26 through r31 in inline assemblyDylan McKay2017-01-051-1/+12
| | | | | | These are synonyms for the X,Y, and Z registers. llvm-svn: 291083
* Add AVR target and toolchain to ClangDylan McKay2017-01-051-0/+93
| | | | | | | | | | | | | | | | | Summary: Authored by Senthil Kumar Selvaraj This patch adds barebones support in Clang for the (experimental) AVR target. It uses the integrated assembler for assembly, and the GNU linker for linking, as lld doesn't know about the target yet. The DataLayout string is the same as the one in AVRTargetMachine.cpp. The alignment specs look wrong to me, as it's an 8 bit target and all types only need 8 bit alignment. Clang failed with a datalayout mismatch error when I tried to change it, so I left it that way for now. Reviewers: rsmith, dylanmckay, cfe-commits, rengolin Subscribers: rengolin, jroelofs, wdng Differential Revision: https://reviews.llvm.org/D27123 llvm-svn: 291082
* [inline-asm]No error for conflict between inputs\outputs and clobber listMarina Yatsina2016-12-261-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | According to extended asm syntax, a case where the clobber list includes a variable from the inputs or outputs should be an error - conflict. for example: const long double a = 0.0; int main() { char b; double t1 = a; __asm__ ("fucompp": "=a" (b) : "u" (t1), "t" (t1) : "cc", "st", "st(1)"); return 0; } This should conflict with the output - t1 which is st, and st which is st aswell. The patch fixes it. Commit on behald of Ziv Izhar. Differential Revision: https://reviews.llvm.org/D15075 llvm-svn: 290539
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