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* [Fixed Point Arithmetic] Fixed Point Precision Bits and Fixed Point LiteralsLeonard Chan2018-06-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This diff includes the logic for setting the precision bits for each primary fixed point type in the target info and logic for initializing a fixed point literal. Fixed point literals are declared using the suffixes ``` hr: short _Fract uhr: unsigned short _Fract r: _Fract ur: unsigned _Fract lr: long _Fract ulr: unsigned long _Fract hk: short _Accum uhk: unsigned short _Accum k: _Accum uk: unsigned _Accum ``` Errors are also thrown for illegal literal values ``` unsigned short _Accum u_short_accum = 256.0uhk; // expected-error{{the integral part of this literal is too large for this unsigned _Accum type}} ``` Differential Revision: https://reviews.llvm.org/D46915 llvm-svn: 335148
* [TargetInfo] Sort target features before passing them to the backendEli Friedman2018-04-251-0/+3
| | | | | | | | | | | | | | | Passing the features in random order will lead to unpredictable results when some of the features are related (like the architecture-version features on ARM). It might be possible to fix this particular case in the ARM target code, to avoid adding overlapping target features. But we should probably be sorting in any case: the behavior shouldn't depend on StringMap's hashing algorithm. Differential Revision: https://reviews.llvm.org/D46030 llvm-svn: 330861
* [CUDA] Revert defining __CUDA_ARCH__ for amdgcn targetsYaxun Liu2018-04-091-55/+0
| | | | | | | | | | amdgcn targets only support HIP, which does not define __CUDA_ARCH__. this is a partial unroll of r329232 / D45277. Differential Revision: https://reviews.llvm.org/D45387 llvm-svn: 329584
* [HIP] define __CUDA_ARCH_=1 for amdgcn targetsYaxun Liu2018-04-061-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D45277 llvm-svn: 329420
* [CUDA] Add amdgpu sub archsYaxun Liu2018-04-041-0/+55
| | | | | | | | | Patch by Greg Rodgers. Revised and lit tests added by Yaxun Liu. Differential Revision: https://reviews.llvm.org/D45277 llvm-svn: 329232
* Make march/target-cpu print a note with the list of valid values for ARMErich Keane2018-02-081-0/+5
| | | | | | | | | | | | When rejecting a march= or target-cpu command line parameter, the message is quite lacking. This patch adds a note that prints all possible values for the current target, if the target supports it. This adds support for the ARM/AArch64 targets (more to come!). Differential Revision: https://reviews.llvm.org/D42978 llvm-svn: 324673
* [RISCV] Create a LinuxTargetInfo when targeting LinuxAlex Bradbury2018-02-031-0/+6
| | | | | | | | | | | | | | Previously, RISCV32TargetInfo or RISCV64TargetInfo were created unconditionally. Use LinuxTargetInfo<RISCV??TargetInfo> to ensure that the proper OS-specific defines are present. This patch only adds logic to instantiate LinuxTargetInfo and leaves a TODO, as I'm reluctant to add logic for other targets (e.g. FreeBSD, RTEMS) until I've produced and tested at least one binary for that OS+target combo. Thanks to @mgrang to reporting the issue. llvm-svn: 324170
* [RISCV] Add the RISCV target and compiler driverAlex Bradbury2018-01-111-0/+6
| | | | | | | | | As RV64 codegen has not yet been upstreamed into LLVM, we focus on RV32 driver support (RV64 to follow). Differential Revision: https://reviews.llvm.org/D39963 llvm-svn: 322276
* [MINGW] normalize WIN32 macrosMartell Malone2017-11-211-1/+8
| | | | | | | | | | | | | | move _WIN64 and _WIN32 defines to lib/Basic/Targets/OSTargets.h move WIN32, WIN64 and __MINGW64__ to addMinGWDefines fixes __MINGW64__ not being defined for aarch64 adds WIN32 definition for x64 Reviewers: mstorsjo Differential Revision: https://reviews.llvm.org/D40285 llvm-svn: 318755
* [Atomic][X8664] set max atomic inline width according to the targetWei Mi2017-09-221-0/+1
| | | | | | | | | | | This is to fix PR31620. MaxAtomicInlineWidth is set to 128 for x86_64. However for target without cx16 support, 128 atomic operation will generate __sync_* libcalls. The patch set MaxAtomicInlineWidth to 64 if the target doesn't support cx16. Differential Revision: https://reviews.llvm.org/D38046 llvm-svn: 313992
* [AArch64] Add support for a MinGW AArch64 targetMartin Storsjo2017-08-131-1/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D36364 llvm-svn: 310798
* [Targets] Move addCygMingDefines into the arch-independent Targets.cpp (NFC)Martin Storsjo2017-07-311-0/+24
| | | | | | | | | | | | This fixes a dependency inconsistency, where addMinGWDefines in Targets.cpp (used from other architectures than X86) called the addCygMingDefines function in X86.h. This was inconsistently split in SVN r308791 (D35701). Differential Revision: https://reviews.llvm.org/D36072 llvm-svn: 309598
* Remove Bitrig: Clang ChangesErich Keane2017-07-211-8/+0
| | | | | | | | Bitrig code has been merged back to OpenBSD, thus the OS has been abandoned. Differential Revision: https://reviews.llvm.org/D35708 llvm-svn: 308797
* Break up Targets.cpp into a header/impl pair per target type[NFCI]Erich Keane2017-07-211-9599/+36
| | | | | | | | | | | | | | | | Targets.cpp is getting unwieldy, and even minor changes cause the entire thing to cause recompilation for everyone. This patch bites the bullet and breaks it up into a number of files. I tended to keep function definitions in the class declaration unless it caused additional includes to be necessary. In those cases, I pulled it over into the .cpp file. Content is copy/paste for the most part, besides includes/format/etc. Differential Revision: https://reviews.llvm.org/D35701 llvm-svn: 308791
* [Hexagon] Add inline-asm constraint 'a' for modifier register classKrzysztof Parzyszek2017-07-211-0/+3
| | | | | | | For example asm ("memw(%0++%1) = %2" : : "r"(addr),"a"(mod),"r"(val) : "memory") llvm-svn: 308763
* [NVPTX] Add lowering of i128 params.Artem Belevich2017-07-201-2/+2
| | | | | | | | | | | | | | | | | The patch adds support of i128 params lowering. The changes are quite trivial to support i128 as a "special case" of integer type. With this patch, we lower i128 params the same way as aggregates of size 16 bytes: .param .b8 _ [16]. Currently, NVPTX can't deal with the 128 bit integers: * in some cases because of failed assertions like ValVTs.size() == OutVals.size() && "Bad return value decomposition" * in other cases emitting PTX with .i128 or .u128 types (which are not valid [1]) [1] http://docs.nvidia.com/cuda/parallel-thread-execution/index.html#fundamental-types Differential Revision: https://reviews.llvm.org/D34555 Patch by: Denys Zariaiev (denys.zariaiev@gmail.com) llvm-svn: 308675
* [X86] Put avx512vpopcntdq in the right spot in the validateCpuSupports ↵Craig Topper2017-07-191-1/+1
| | | | | | | | string switch. The validateCpuSupports switch is in the order of the enum defined in CGBuiltin.cpp and libgcc/compiler-rt. llvm-svn: 308546
* Add isValidCPUName and isValidFeature to TargetInfoErich Keane2017-07-191-95/+223
| | | | | | | These two functions are really useful for implementations of attributes (including attribute-target), so add the functionality. llvm-svn: 308530
* [COFF, ARM64] Set the data type widths and the data layout stringMandeep Singh Grang2017-07-171-1/+14
| | | | | | | | | | | | | | Summary: COFF ARM64 is LLP64 platform. So int is 4 bytes, long is 4 bytes and long long is 8 bytes. Reviewers: compnerd, ruiu, rnk, efriedma Reviewed By: compnerd, efriedma Subscribers: efriedma, javed.absar, cfe-commits, aemerson, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D34859 llvm-svn: 308222
* [AArch64] Add support for __builtin_ms_va_list on aarch64Martin Storsjo2017-07-171-1/+5
| | | | | | | | | | | Move builtins from the x86 specific scope into the global scope. Their use is still limited to x86_64 and aarch64 though. This allows wine on aarch64 to properly handle variadic functions. Differential Revision: https://reviews.llvm.org/D34475 llvm-svn: 308218
* [SystemZ] Add support for IBM z14 processor (2/3)Ulrich Weigand2017-07-171-1/+1
| | | | | | | | | | This patch extends the -fzvector language feature to enable the new "vector float" data type when compiling at -march=z14. This matches the updated extension definition implemented by other compilers for the platform, which is indicated to applications by pre-defining __VEC__ to 10302 (instead of 10301). llvm-svn: 308198
* [SystemZ] Add support for IBM z14 processor (1/3)Ulrich Weigand2017-07-171-0/+4
| | | | | | | | | | | This patch series adds support for the IBM z14 processor. This part includes: - Basic support for the new processor and its features. - Support for low-level builtins mapped to new LLVM intrinsics. Support for the -fzvector extension to vector float and the new high-level vector intrinsics is provided by separate patches. llvm-svn: 308197
* Enable TLS support on OpenBSD, but default to the emulatated TLS model.Brad Smith2017-07-171-2/+0
| | | | llvm-svn: 308155
* [X86] Add 'movbe' to btver2 CPU.Craig Topper2017-07-141-0/+1
| | | | | | This probably doesn't change anything because the frotend doesn't do anything with this feature and the backend will infer from the cpu string. So this is just for consistency with other cpus that support movbe. llvm-svn: 308002
* [AArch64] Add support for handling the +sve target feature.Amara Emerson2017-07-131-4/+11
| | | | | | | | This also adds the appropriate predefine for SVE if enabled. Differential Revision: https://reviews.llvm.org/D35118 llvm-svn: 307919
* [mips] Create the correct profiling symbol on Linux MIPSSimon Atanasyan2017-07-111-0/+4
| | | | llvm-svn: 307627
* CodeGen: Fix address space of global variableYaxun Liu2017-07-081-0/+4
| | | | | | | | | | | | | Certain targets (e.g. amdgcn) require global variable to stay in global or constant address space. In C or C++ global variables are emitted in the default (generic) address space. This patch introduces virtual functions TargetCodeGenInfo::getGlobalVarAddressSpace and TargetInfo::getConstantAddressSpace to handle this in a general approach. It only affects IR generated for amdgcn target. Differential Revision: https://reviews.llvm.org/D33842 llvm-svn: 307470
* [X86] Replace 'fallthrough' comments with LLVM_FALLTHROUGH.Craig Topper2017-07-071-6/+6
| | | | llvm-svn: 307420
* This reverts r305820 (ARMv.2-A FP16 vector intrinsics) because it showsSjoerd Meijer2017-07-061-3/+0
| | | | | | | | problems in testing, see comments in D34161 for some more details. A fix is in progres in D35011, but a revert seems better now as the fix will probably take some more time to land. llvm-svn: 307277
* [SystemZ] Simplify handling of ISA revisionsUlrich Weigand2017-07-051-26/+22
| | | | | | | | | | This moves determination of the ISA revision from the CPU name to one single place, removing a bunch of duplicated code. It also makes the supported ISA revisions available as feature strings. No functional change. llvm-svn: 307156
* [AMDGPU] Fix size and alignment of size_t and pointer typesYaxun Liu2017-07-051-6/+14
| | | | | | Differential Revision: https://reviews.llvm.org/D34995 llvm-svn: 307121
* [AMDGPU] Fix regressions on mesa/clover with libclc due to address spaceYaxun Liu2017-07-041-10/+18
| | | | | | | | | | Currently AMDGPUTargetInfo does not initialize AddrSpaceMap in constructor, which causes regressions in mesa/clover with libclc. This patch fixes that. Differential Revision: https://reviews.llvm.org/D34987 llvm-svn: 307105
* fix trivial typos; NFCHiroshi Inoue2017-07-011-1/+1
| | | | llvm-svn: 306954
* Changed Opts.EABIVersion type string to llvm::EABI enum classYuka Takahashi2017-07-011-2/+2
| | | | | | | | | | Summary: Changed EABIVersion type from string to llvm::EABI. It seems it was just a typo and this is intended implementation. Differential Revision: https://reviews.llvm.org/D34595 llvm-svn: 306953
* [X86] Add RDRND feature to Goldmont. Add MOVBE to all Atom CPUs.Craig Topper2017-06-301-0/+2
| | | | | | Diffential Revision: https://reviews.llvm.org/D34842 llvm-svn: 306851
* [X86] Add a break to the last case of a few switches to prevent accidents in ↵Craig Topper2017-06-301-0/+4
| | | | | | the future. NFC llvm-svn: 306850
* [X86] Move all atom CPUs to the same section of the switch and use ↵Craig Topper2017-06-301-3/+6
| | | | | | | | fallthroughs like we do for other CPU generations. NFC This is prep work to add MOVBE to all Atom CPUs. This instruction didn't come in to the Nehalem/Westmere/SandyBridge/etc. line until later so there's no natural place to overlap the Atom CPUs into that part of the switch. llvm-svn: 306849
* ARMV8-A archkind and target defines helper functionsSjoerd Meijer2017-06-301-12/+47
| | | | | | | | | | | | This introduces helper functions that set target defines for different ARMV8-A architecture kinds. It fixes an issue that the v8.1 define ARM_FEATURE_QRDMX was not set for v8.2. These helper functions make things more “scalable” if we want to add ARMv8.3 at some point, and a cleanup has been done to hold the architecture kind in one variable (instead of one for each). Differential Revision: https://reviews.llvm.org/D34686 llvm-svn: 306805
* [Clang][X86][Goldmont]Adding new target-cpu: Goldmont Michael Zuckerman2017-06-291-0/+21
| | | | | | | | | | | | | | | [Clang-side] Connecting the GoldMont processor to his feature. Reviewers: 1. igorb 2. delena 3. zvi Differential Revision: https://reviews.llvm.org/D34807 llvm-svn: 306673
* [COFF, ARM64] Add support for Windows ARM64 COFF formatMandeep Singh Grang2017-06-271-0/+39
| | | | | | | | | | | | | | Summary: This is the clang part of the initial implementation to support Windows ARM64 COFF format. Reviewers: ruiu, t.p.northover, rnk, compnerd Reviewed By: ruiu, compnerd Subscribers: aemerson, kristof.beyls, cfe-commits, llvm-commits Differential Revision: https://reviews.llvm.org/D34706 llvm-svn: 306489
* Reapply "Frontend support for Nios2 target"Nikolai Bozhenov2017-06-271-0/+145
| | | | | | | | | | | | | | Summary: - Implements TargetInfo class for Nios2 target. - Enables handling of -march and -mcpu options for Nios2 target. - Definition of Nios2 builtin functions. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D33356 Author: belickim <mateusz.belicki@intel.com> llvm-svn: 306383
* Add support for Ananas platformEd Schouten2017-06-251-0/+19
| | | | | | | | | | | | | | | | | Ananas is a home-brew operating system, mainly for amd64 machines. After using GCC for quite some time, it has switched to clang and never looked back - yet, having to manually patch things is annoying, so it'd be much nicer if this was in the official tree. More information: https://github.com/zhmu/ananas/ https://rink.nu/projects/ananas.html Submitted by: Rink Springer Differential Revision: https://reviews.llvm.org/D32936 llvm-svn: 306239
* [MSP430] Fix data layout string.Vadzim Dambrouski2017-06-231-1/+1
| | | | | | | | | | | | | | | | | Summary: Change data layout string so it would be compatible with MSP430 EABI. Depends on D34561 Reviewers: asl, awygle Reviewed By: asl Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D34562 llvm-svn: 306161
* [AArch64] ADD ARMv.2-A FP16 vector intrinsicsAbderrazek Zaafrani2017-06-201-0/+10
| | | | | | Differential Revision: https://reviews.llvm.org/D34161 llvm-svn: 305820
* Revert "Define _GNU_SOURCE for rtems c++"Daniel Jasper2017-06-151-3/+0
| | | | | | | | | | | | | | | | | This reverts commit r305399. This breaks a build in libcxx: libcxx/src/system_error.cpp:90:16: error: assigning to 'int' from incompatible type 'char *' if ((ret = ::strerror_r(ev, buffer, strerror_buff_size)) != 0) { ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1 error generated. Which makes sense according to: https://linux.die.net/man/3/strerror_r Not entirely sure how this needs to be fixed. llvm-svn: 305456
* Define _GNU_SOURCE for rtems c++James Y Knight2017-06-141-0/+3
| | | | | | | | | | This is required by the libc++ locale support. Patch by Walter Lee. Differential Revision: https://reviews.llvm.org/D34105 llvm-svn: 305399
* Revert of r305066 "Reapply Frontend support for Nios2 target"Nikolai Bozhenov2017-06-091-145/+0
| | | | llvm-svn: 305068
* Reapply "Frontend support for Nios2 target"Nikolai Bozhenov2017-06-091-0/+145
| | | | | | | | | | | | | | Summary: - Implements TargetInfo class for Nios2 target. - Enables handling of -march and -mcpu options for Nios2 target. - Definition of Nios2 builtin functions. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D33356 Author: belickim <mateusz.belicki@intel.com> llvm-svn: 305066
* Revert "Frontend support for Nios2 target"Nikolai Bozhenov2017-06-081-145/+0
| | | | | | As it breaks many buildbots. llvm-svn: 305002
* Frontend support for Nios2 target.Nikolai Bozhenov2017-06-081-0/+145
| | | | | | | | | | | | | | Summary: - Implements TargetInfo class for Nios2 target. - Enables handling of -march and -mcpu options for Nios2 target. - Definition of Nios2 builtin functions. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D33356 Author: belickim <mateusz.belicki@intel.com> llvm-svn: 304994
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