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* Remove some redundant virtual specifiers on overriden functions.David Blaikie2014-11-141-7/+7
| | | | llvm-svn: 222024
* Remove -fseh-exceptions in favor of checking the tripleReid Kleckner2014-11-141-0/+4
| | | | | | | | | This option was misleading because it looked like it enabled the language feature of SEH (__try / __except), when this option was really controlling which EH personality function to use. Mingw only supports SEH and SjLj EH on x86_64, so we can simply do away with this flag. llvm-svn: 221963
* Hook up FreeBSD AArch64 supportEd Maste2014-11-131-0/+4
| | | | | | Patch from Andrew Turner. llvm-svn: 221900
* Introduce a SanitizerKind enum to LangOptions.Alexey Samsonov2014-11-071-1/+2
| | | | | | | | | | | | | Use the bitmask to store the set of enabled sanitizers instead of a bitfield. On the negative side, it makes syntax for querying the set of enabled sanitizers a bit more clunky. On the positive side, we will be able to use SanitizerKind to eventually implement the new semantics for -fsanitize-recover= flag, that would allow us to make some sanitizers recoverable, and some non-recoverable. No functionality change. llvm-svn: 221558
* Remove references to the cortex-a9-mp CPU.Charlie Turner2014-11-061-3/+2
| | | | | | | | | | This CPU definition is redundant. The Cortex-A9 is defined as supporting multiprocessing extensions. Remove references to this CPU. This CPU was recently removed from LLVM. See http://reviews.llvm.org/D6057 Change-Id: I62ae7cc656fcae54fbaefc4b6976e77e694a8678 llvm-svn: 221458
* [X86] Slightly refactor default features for AMD bdver cpus (NFC). Also add ↵Andrea Di Biagio2014-11-061-12/+7
| | | | | | | | | | | | | | | | | | | missing checks to test for target features. This patch simplifies how default target features are set for AMD bdver2 and bdver1. In particular, method 'getDefaultFeatures' now implements a fallthrough from case 'CK_BDVER2' to case 'CK_BDVER1'. That is because 'bdver2' has the same features available in bdver1 plus BMI, FMA, F16C and TBM. This patch also adds missing checks for predefined macros in test predefined-arch-macros.c. In the case of BTVER2, the test now also checks for F16C, BMI and PCLMUL. In the case of BDVER3 and BDVER4, the test now also checks for the presence of FSGSBASE. Differential Revision: http://reviews.llvm.org/D6134 llvm-svn: 221449
* [X86] Use fallthroughs to reduce the number of calls to setFeatureEnabled ↵Craig Topper2014-11-061-98/+45
| | | | | | for different CPUs. llvm-svn: 221437
* [x86] Add cx16 feature to KNL, SKX, and CoreAVXi CPUs.Craig Topper2014-11-031-2/+5
| | | | llvm-svn: 221132
* [x86] Realphabetize the feature string decoding function since it was mostly ↵Craig Topper2014-11-031-4/+4
| | | | | | in alphabetical order. llvm-svn: 221131
* Add FSGSBASE intrinsics to x86 intrinsic headers.Craig Topper2014-11-031-7/+24
| | | | llvm-svn: 221130
* [PowerPC] Change PPCTargetInfo::hasFeature() to use StringSwitchBill Schmidt2014-11-021-3/+5
| | | | | | Implement post-commit comment on r220989 from Eric Christopher. llvm-svn: 221099
* Implement IRGen for the x86 vectorcall conventionReid Kleckner2014-10-311-0/+2
| | | | | | | | | | | | | | | The most complex aspect of the convention is the handling of homogeneous vector and floating point aggregates. Reuse the homogeneous aggregate classification code that we use on PPC64 and ARM for this. This convention also has a C mangling, and we apparently implement that in both Clang and LLVM. Reviewed By: majnemer Differential Revision: http://reviews.llvm.org/D6063 llvm-svn: 221006
* [PowerPC] Initial VSX intrinsic support, with min/max for vector doubleBill Schmidt2014-10-311-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have initial support for VSX, we can begin adding intrinsics for programmer access to VSX instructions. This patch performs the necessary enablement in the front end, and tests it by implementing intrinsics for minimum and maximum using the vector double data type. The main change in the front end is to no longer disallow "vector" and "double" in the same declaration (lib/Sema/DeclSpec.cpp), but "vector" and "long double" must still be disallowed. The new intrinsics are accessed via vec_max and vec_min with changes in lib/Headers/altivec.h. Note that for v4f32, we already access corresponding VMX builtins, but with VSX enabled we should use the forms that allow all 64 vector registers. The new built-ins are defined in include/clang/Basic/BuiltinsPPC.def. I've added a new test in test/CodeGen/builtins-ppc-vsx.c that is similar to, but much smaller than, builtins-ppc-altivec.c. This allows us to test VSX IR generation without duplicating CHECK lines for the existing bazillion Altivec tests. Since vector double is now legal when VSX is available, I've modified the error message, and changed where we test for it and for vector long double, since the target machine isn't visible in the old place. This serendipitously removed a not-pertinent warning about 'long' being deprecated when used with 'vector', when "vector long double" is encountered and we just want to issue an error. The existing tests test/Parser/altivec.c and test/Parser/cxx-altivec.cpp have been updated accordingly, and I've added test/Parser/vsx.c to verify that "vector double" is now legitimate with VSX enabled. There is a companion patch for LLVM. llvm-svn: 220989
* Add frontend support for __vectorcallReid Kleckner2014-10-241-2/+3
| | | | | | | | | | | | | Wire it through everywhere we have support for fastcall, essentially. This allows us to parse the MSVC "14" CTP headers, but we will miscompile them because LLVM doesn't support __vectorcall yet. Reviewed By: Aaron Ballman Differential Revision: http://reviews.llvm.org/D5808 llvm-svn: 220573
* Switch C compilations to C11 by default.Richard Smith2014-10-201-3/+3
| | | | | | | | This is long-since overdue, and matches GCC 5.0. This should also be backwards-compatible, because we already supported all of C11 as an extension in C99 mode. llvm-svn: 220244
* Use the triple's isiOS() method instead of checking the value directly. NFC.Bob Wilson2014-10-191-1/+1
| | | | llvm-svn: 220158
* As requested by Matt Thomas, use long long for intmax_t and int64_t onJoerg Sonnenberger2014-10-151-0/+4
| | | | | | PPC64/NetBSD. llvm-svn: 219839
* Set ABI and DescriptionString first to reduce OS specific logic.Joerg Sonnenberger2014-10-151-10/+13
| | | | | | Use switch for FreeBSD check to allow easier extension. llvm-svn: 219838
* ARM: remove ARM/Thumb distinction for preferred alignment.Tim Northover2014-10-141-60/+30
| | | | | | | | | | | | Thumb1 has legitimate reasons for preferring 32-bit alignment of types i1/i8/i16, since the 16-bit encoding of "add rD, sp, #imm" requires #imm to be a multiple of 4. However, this is a trade-off betweem code size and RAM usage; the DataLayout string is not the best place to represent it even if desired. So this patch removes the extra Thumb requirements, hopefully making ARM and Thumb completely compatible in this respect. llvm-svn: 219735
* ARM: set preferred aggregate alignment to 32 universally.Tim Northover2014-10-141-7/+7
| | | | | | | | | | | Before, ARM and Thumb mode code had different preferred alignments, which could lead to some rather unexpected results. There's justification for reducing it from the default 64-bits (wasted space), but I don't think there is for going below 32-bits. There's no actual ABI change here, just to reassure people. llvm-svn: 219720
* Adds support for the Cortex-A17 processor to ClangRenato Golin2014-10-131-3/+3
| | | | | | Patch by Matthew Wahab. llvm-svn: 219607
* [PowerPC] Reduce names from Power8Vector to P8VectorBill Schmidt2014-10-101-4/+4
| | | | | | Per Hal Finkel's review, improving typability of some variable names. llvm-svn: 219515
* [PowerPC] Add feature for Power8 vector extensionsBill Schmidt2014-10-101-1/+9
| | | | | | | | | | | | | | | | | | The current VSX feature for PowerPC specifies availability of the VSX instructions added with the 2.06 architecture version. With 2.07, the architecture adds new instructions to both the Category:Vector and Category:VSX instruction sets. Additionally, unaligned vector storage operations have improved performance. This patch adds a feature to provide access to the new instructions and performance capabilities of Power8. For compatibility with GCC, the feature is controlled via a new -mpower8-vector switch, and the feature causes the __POWER8_VECTOR__ builtin define to be generated by the preprocessor. There is a companion patch for llvm being committed at the same time. llvm-svn: 219502
* Adds 'override' to overriding methods. NFC.Fariborz Jahanian2014-10-011-13/+13
| | | | | | These were uncoveredby my yet undelivered patch. llvm-svn: 218774
* [ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DPOliver Stannard2014-10-011-3/+3
| | | | | | | | | The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be modeled using the same target feature, and all double-precision operations are already disabled by the fp-only-sp target features. llvm-svn: 218748
* Make sure aggregates are properly alligned on MSP430.Job Noorman2014-09-301-1/+1
| | | | llvm-svn: 218666
* Silence a signed/unsigned mismatch warning from MSVC; NFC.Aaron Ballman2014-09-191-1/+1
| | | | llvm-svn: 218121
* [x86] Enable broadwell target in clang.Robert Khasanov2014-09-191-5/+37
| | | | | | Added -madx option llvm-svn: 218116
* [X86, inlineasm] Do not allow using constraint 'x' for a variable larger thanAkira Hatanaka2014-09-181-1/+2
| | | | | | | | 128-bit unless the target CPU supports AVX. rdar://problem/11846140 llvm-svn: 218082
* [X86, inline-asm] Allow 256-bit wide operands for the 'x' constraintsHans Wennborg2014-09-181-1/+2
| | | | | | | The 'x' constraint is for "any SSE register", and GCC seems to include the 256-bit ymm registers in that concept. llvm-svn: 218073
* [X86, inlineasm] Check that the output size is correct for the given constraint.Akira Hatanaka2014-09-181-3/+23
| | | | llvm-svn: 218064
* Basic: use hex string for __ARM_FP macroSaleem Abdulrasool2014-09-181-1/+2
| | | | | | | The ARM ACLE describes the values as hex constants rather than numeric constants; follow suit. Address post-commit review comments from Jon Roelofs. llvm-svn: 218009
* [X86, inline-asm] Check that the input size is correct for constraints R, q, Q,Akira Hatanaka2014-09-171-1/+26
| | | | | | | | | | | S, D, A, y, x, f, t, and u. This is a follow-up patch for r167717. rdar://problem/11846140 rdar://problem/17476970 llvm-svn: 217994
* Basic: add support for ARM ACLE 6.5.1Saleem Abdulrasool2014-09-171-12/+32
| | | | | | | | Extend ARM ACLE support (Section 6.5.1) for AArch32. Define __ARM_FP if hardware floating point support is available as per the value defined by the ACLE. llvm-svn: 217957
* Basic: use range-based for loops for ARM targetSaleem Abdulrasool2014-09-171-19/+20
| | | | | | | Tweak handleTargetFeature for the ARM(32) target to use range based for loops. NFC. llvm-svn: 217956
* Basic: whitespace fixup for ARM target infoSaleem Abdulrasool2014-09-171-2/+1
| | | | | | Fix whitespace. NFC. llvm-svn: 217955
* [ARM] Add ACLE predefines: maxmin, rounding and h/w integer divisionJames Molloy2014-09-151-0/+8
| | | | | | Patch by Assad Hashmi! llvm-svn: 217760
* No need to use PNaCl's calling convention since PNaCl now uses a separate ↵JF Bastien2014-09-121-3/+0
| | | | | | approach for calling conventions. llvm-svn: 217696
* Add support for le64.JF Bastien2014-09-121-0/+60
| | | | | | | | | | | | | | | | | Summary: le64 is a generic little-endian 64-bit processor, mimicking le32. Also see the associated LLVM change. Test Plan: make check-all Reviewers: dschuff Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5318 llvm-svn: 217694
* Fixing MSVC warning: "warning C4373: 'blah': virtual function overrides ↵Aaron Ballman2014-08-221-4/+2
| | | | | | | | 'blah', previous versions of the compiler did not override when parameters only differed by const/volatile qualifiers." This warning is basically useless because the "previous versions" being referred to is MSVC 2005 and earlier, and we obviously do not care about them. However, this warning isn't particularly chatty (I don't recall ever seeing it previously), and it has the opportunity to point out cases where the cv-qualifiers differ unintentionally (like this case), so I am leaving it enabled for now. llvm-svn: 216267
* [AArch64, inline-asm] Improve diagnostic that is printed when the size of aAkira Hatanaka2014-08-221-6/+13
| | | | | | | | | | | | | | | | | variable that has regiser constraint "r" is not 64-bit. General register operands are output using 64-bit "x" register names, regardless of the size of the variable, unless the asm operand is prefixed with the "%w" modifier. This surprises and confuses many users who aren't familiar with aarch64 inline assembly rules. With this commit, a note and fixit hint are printed which tell the users that they need modifier "%w" in order to output a "w" register instead of an "x" register. <rdar://problem/12764785> llvm-svn: 216260
* R600: Implement getPointerWidthV()Tom Stellard2014-08-211-0/+17
| | | | | | | This fixes a crash in the OCL_ImgProc/Canny OpenCV test. NOTE: This is a candidate for the 3.5 branch. llvm-svn: 216181
* R600: Add processor type for hainanTom Stellard2014-08-211-0/+1
| | | | llvm-svn: 216180
* Delete support for AuroraUX.Rafael Espindola2014-08-141-41/+2
| | | | | | auroraux.org is not resolving. llvm-svn: 215644
* Add predefined macros to identify x86_64h architectures.Bob Wilson2014-08-081-0/+4
| | | | | | Patch by Jim Grosbach. llvm-svn: 215260
* Change __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ for versions > 10.9.Bob Wilson2014-08-081-6/+17
| | | | | | | | The previous encoding only allowed a single digit for the minor version number. This changes it to use 2 digits for both the minor version and the revision number. llvm-svn: 215245
* MachO: set sizeof result type to what embedded headers expect.Tim Northover2014-08-051-2/+2
| | | | | | | | | Embedded systems seem to have inherited Darwin's choise of "unsigned long" for size_t (via a bunch of headers), so we should respect that. rdar://problem/17872787 llvm-svn: 214854
* [x32] Add __int128 supportPavel Chupin2014-08-041-0/+2
| | | | | | | | | | | | | | | | Summary: Adding __int128 support explicitly for x86_64 because currently it's on only when pointer size >= 64 which is not the case for x32. Test Plan: One of the tests using __int128 is updated Reviewers: atanasyan, chandlerc Subscribers: cfe-commits, rob.khasanov, zinovy.nis, dschuff Differential Revision: http://reviews.llvm.org/D4755 llvm-svn: 214710
* Let's assume PowerPC has no SSE.Joerg Sonnenberger2014-08-011-1/+0
| | | | llvm-svn: 214562
* [SKX] Enabling SKX target (Skylake server chip) Robert Khasanov2014-07-301-5/+56
| | | | | | | | | a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
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