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* Add Hardware Transactional Memory (HTM) SupportKit Barton2015-03-251-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds Hardware Transaction Memory (HTM) support supported by ISA 2.07 (POWER8). The intrinsic support is based on GCC one [1], with both 'PowerPC HTM Low Level Built-in Functions' and 'PowerPC HTM High Level Inline Functions' implemented. Along with builtins a new driver switch is added to enable/disable HTM instruction support (-mhtm) and a header with common definitions (mostly to parse the TFHAR register value). The HTM switch also sets a preprocessor builtin HTM. The HTM usage requires a recently newer kernel with PPC HTM enabled. Tested on powerpc64 and powerpc64le. This is send along a llvm patch to enabled the builtins and option switch. [1] https://gcc.gnu.org/onlinedocs/gcc/PowerPC-Hardware-Transactional-Memory-Built-in-Functions.html Phabricator Review: http://reviews.llvm.org/D8248 llvm-svn: 233205
* Create android x86_32 and x86_64 target infoTamas Berghammer2015-03-251-4/+40
| | | | | | | | | | | On android x86_32 the long double is only 64 bits (compared to 80 bits on linux x86_32) and on android x86_64 the long double is IEEEquad (compared to x87DoubleExtended on linux x86_64). This CL creates new TargetInfo classes for this targets to represent these differences. Differential revision: http://reviews.llvm.org/D8357 llvm-svn: 233177
* Move private classes into anonymous namespacesBenjamin Kramer2015-03-231-86/+1
| | | | | | Also merge anonymous namespaces in Targets.cpp a bit. NFC. llvm-svn: 232945
* MS ABI: Define _HAS_CHAR16_T_LANGUAGE_SUPPORT when appropriateDavid Majnemer2015-03-181-0/+3
| | | | | | | If we are in MSVC 2015 compatibility mode and C++11 language conformance is enabled, define _HAS_CHAR16_T_LANGUAGE_SUPPORT to 1. llvm-svn: 232615
* Basic: Update clang to reflect changes made to LLVM datalayoutDavid Majnemer2015-03-171-7/+9
| | | | | | | We now give x86-64 COFF targets a different mangling code, update clang to use it. llvm-svn: 232571
* [ARM] Add support for ARMV6K subtarget (Clang)Renato Golin2015-03-171-2/+3
| | | | | | | | | | | | | | | | | | | | | ARMv6K is another layer between ARMV6 and ARMV6T2. This is the Clang side of the changes. ARMV6 family LLVM implementation. +-------------------------------------+ | ARMV6 | +----------------+--------------------+ | ARMV6M (thumb) | ARMV6K (arm,thumb) | <- From ARMV6K and ARMV6M processors +----------------+--------------------+ have support for hint instructions | ARMV6T2 (arm,thumb,thumb2) | (SEV/WFE/WFI/NOP/YIELD). They can +-------------------------------------+ be either real or default to NOP. | ARMV7 (arm,thumb,thumb2) | The two processors also use +-------------------------------------+ different encoding for them. Patch by Vinicius Tinti. llvm-svn: 232469
* Under duress, move check for target support of __builtin_setjmp/Joerg Sonnenberger2015-03-111-0/+8
| | | | | | __builtin_longjmp to Sema as requested by John McCall. llvm-svn: 231986
* [PowerPC] ABI support for the QPX vector instruction setHal Finkel2015-03-111-3/+10
| | | | | | | | | | | | | | Support for the QPX vector instruction set, used on the IBM BG/Q supercomputer, has recently been added to the LLVM PowerPC backend. This vector instruction set requires some ABI modifications because the ABI on the BG/Q expects <4 x double> vectors to be provided with 32-byte stack alignment, and to be handled as native vector types (similar to how Altivec vectors are handled on mainline PPC systems). I've named this ABI variant elfv1-qpx, have made this the default ABI when QPX is supported, and have updated the ABI handling code to provide QPX vectors with the correct stack alignment and associated register-assignment logic. llvm-svn: 231960
* Add target information for CloudABI on x86-64.Ed Schouten2015-03-111-0/+24
| | | | | | | | | | | CloudABI can be identified by the __CloudABI__ preprocessor definition. The system uses ELF executables. CloudABI uses Unicode 7.0.0 for the encoding of wchar_t. As Unicode 7.0.0 is synchronized with ISO/IEC 10646:2012 (released on 2012-06-01), __STDC_ISO_10646__ is defined as 201206L. llvm-svn: 231912
* Add Clang support for PPC cryptography builtinsNemanja Ivanovic2015-03-041-1/+19
| | | | | | Review: http://reviews.llvm.org/D7951 llvm-svn: 231291
* Support __attribute__((availability)) on Android.Dan Albert2015-03-031-1/+6
| | | | | | | | | | | | Reviewers: srhines Reviewed By: srhines Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D7929 llvm-svn: 231092
* Add __ARM_DWARF_EH__ to signify the use of Itanium ABI for unwind instructions.Renato Golin2015-02-271-2/+14
| | | | | | | | Equally to NetBSD, Bitrig will be using .eh_frame unwinding on ARM. Patch by Patrick Wildt. llvm-svn: 230763
* AMDGCN: Define cl_khr_fp64 when compiling OpenCL programsTom Stellard2015-02-271-0/+2
| | | | llvm-svn: 230761
* Win64: Silently ignore __stdcall, __fastcall, and __thiscallReid Kleckner2015-02-261-4/+16
| | | | | | | | | | MSVC doesn't warn on this. Users are expected to apply the WINAPI macro to functions passed by pointer to the Win32 API, and this macro expands to __stdcall. This means we end up with a lot of useless noisy warnings about ignored calling conventions when compiling code with clang for Win64. llvm-svn: 230668
* Add support for generating MIPS legacy NaNPetar Jovanovic2015-02-261-0/+4
| | | | | | | | | | | Currently, the NaN values emitted for MIPS architectures do not cover non-IEEE754-2008 compliant case. This change fixes the issue. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D7882 llvm-svn: 230653
* Remove some unused includes of llvm/IR headers from parts of Clang that reallyRichard Smith2015-02-261-1/+0
| | | | | | shouldn't depend on LLVM IR. llvm-svn: 230586
* [Mips] Support mips32r3, mips32r5, mips64r3, mips64r5 MIPS ISA namesSimon Atanasyan2015-02-201-0/+12
| | | | | | | | | The patch teaches the clang's driver to understand new MIPS ISA names, pass appropriate options to the assembler, defines corresponding macros etc http://reviews.llvm.org/D7737 llvm-svn: 230092
* Change representation of member function pointers for MIPS targetsZoran Jovanovic2015-02-181-1/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D7148 llvm-svn: 229680
* [ARM] Add missing M/R class CPUsBradley Smith2015-02-181-7/+9
| | | | | | | | | | | | Add some of the missing M and R class Cortex CPUs, namely: Cortex-M0+ (called Cortex-M0plus for GCC compatibility) Cortex-M1 SC000 SC300 Cortex-R5 llvm-svn: 229661
* Remove the ABI from the target features. It's obsoleted byEric Christopher2015-02-171-3/+0
| | | | | | the -target-abi use and those features don't exist anymore. llvm-svn: 229526
* Preprocessor: support __BIGGEST_ALIGNMENT__ macroTim Northover2015-02-061-2/+2
| | | | | | | | | | | For compatibility with GCC (and because it's generally helpful information otherwise inaccessible to the preprocessor). This appears to be canonically the alignment of max_align_t (e.g. on i386, __BIGGEST_ALIGNMENT__ is 4 even though vector types will be given greater alignment). Patch mostly by Mats Petersson llvm-svn: 228367
* Teaches the Clang driver to accept Cortex-A72Renato Golin2015-02-041-4/+4
| | | | | | | | | A previous commit added Cortex-A72 to LLVM, this teaches Clang to accept it as well. Patch by Ranjeet Singh. llvm-svn: 228141
* Windows: Fix _CPPUNWIND definition to follow -fcxx-exceptionsReid Kleckner2015-01-301-1/+1
| | | | | | | This is consistent with how we interpret the MSVC /EH flag, which controls -fcxx-exceptions. llvm-svn: 227616
* [mips] Pass ABI name via -target-abi instead of target-featuresDaniel Sanders2015-01-301-8/+0
| | | | | | | | | | | | | | Patch by Vladimir Medic Reviewers: echristo, atanasyan, dsanders Reviewed By: atanasyan, dsanders Subscribers: llvm-commits, echristo, atanasyan Differential Revision: http://reviews.llvm.org/D6091 llvm-svn: 227583
* Remove support for pnaclcall attributeDerek Schuff2015-01-281-5/+0
| | | | | | | | | | | | | | | | | | Summary: It was used for interoperability with PNaCl's calling conventions, but it's no longer needed. Also Remove NaCl*ABIInfo which just existed to delegate to either the portable or native ABIInfo, and remove checkCallingConvention which was now a no-op override. Reviewers: jvoung Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D7206 llvm-svn: 227362
* R600: Use a Southern Islands GPU as the default for the amdgcn targetTom Stellard2015-01-281-2/+9
| | | | llvm-svn: 227315
* Begin to teach clang about the PS4.Alex Rosenberg2015-01-271-0/+29
| | | | llvm-svn: 227194
* [Mips] Fix type of 64-bit integer in case of MIPS N64 ABISimon Atanasyan2015-01-221-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D7127 llvm-svn: 226877
* Re-apply "r226548 - Introduce SPIR calling conventions" reverted in r226558.Alexander Kornienko2015-01-201-0/+9
| | | | | | | | | | | | | | | | | | | | | | | The test was fixed after a discussion with the revision author: the check pattern was made more flexible as the "%call" part is not what we actually want to check strictly there. The original patch description: === Introduce SPIR calling conventions. This implements Section 3.7 from the SPIR 1.2 spec: SPIR kernels should use "spir_kernel" calling convention. Non-kernel functions use "spir_func" calling convention. All other calling conventions are disallowed. The patch works only for OpenCL source. Any other uses will need to ensure that kernels are assigned the spir_kernel calling convention correctly. === llvm-svn: 226561
* Reverting r226548 as one of the tests fails in some configurations.Alexander Kornienko2015-01-201-9/+0
| | | | | | | | | | | | | | | | | | | | | | Here's the fail log from our internal setup: === .../tools/clang/clang -cc1 -internal-isystem .../tools/clang/staging/include -nostdsysteminc .../tools/clang/test/CodeGenOpenCL/spir-calling-conv.cl -triple spir-unknown-unknown -emit-llvm -o - FileCheck .../tools/clang/test/CodeGenOpenCL/spir-calling-conv.cl .../tools/clang/test/CodeGenOpenCL/spir-calling-conv.cl:11:12: error: expected string not found in input // CHECK: %call = tail call spir_func i32 @get_dummy_id(i32 0) ^ <stdin>:6:52: note: scanning from here define spir_kernel void @foo(i32 addrspace(1)* %A) #0 { ^ <stdin>:7:2: note: possible intended match here %1 = tail call spir_func i32 @get_dummy_id(i32 0) #2 ^ === Here's a failure on a public CI server: http://lab.llvm.org:8080/green/job/clang-stage2-configure-Rlto_check/1183/ llvm-svn: 226558
* Introduce SPIR calling conventions.Sameer Sahasrabuddhe2015-01-201-0/+9
| | | | | | | | | | | | | | This implements Section 3.7 from the SPIR 1.2 spec: SPIR kernels should use "spir_kernel" calling convention. Non-kernel functions use "spir_func" calling convention. All other calling conventions are disallowed. The patch works only for OpenCL source. Any other uses will need to ensure that kernels are assigned the spir_kernel calling convention correctly. llvm-svn: 226548
* AArch64: implement AAPCS layout rules for bit-fields.Tim Northover2015-01-161-0/+7
| | | | llvm-svn: 226294
* [Mips] Define macros `__mips_isa_rev` in case of mips32r6/mips64r6 optionsSimon Atanasyan2015-01-151-0/+4
| | | | llvm-svn: 226136
* PR22208: On FreeBSD systems, __STDC_MB_MIGHT_NEQ_WC__ is expected to be definedRichard Smith2015-01-131-0/+6
| | | | | | | | | | | even though every basic source character literal has the same numerical value as a narrow or wide character literal. It appears that the FreeBSD folks are trying to use this macro to mean something other than what the relevant standards say it means, but their usage is conforming, so put up with it. llvm-svn: 225751
* [mips] Explain why we need to always clobber for MIPS inline asm. NFC.Toma Tabacu2015-01-121-0/+21
| | | | llvm-svn: 225632
* R600: Handle amdgcn tripleTom Stellard2015-01-061-0/+1
| | | | | | For now there is no difference between amdgcn and r600. llvm-svn: 225294
* Sema: analyze I,J,K,M,N,O constraintsSaleem Abdulrasool2015-01-061-0/+55
| | | | | | | | | | Add additional constraint checking for target specific behaviour for inline assembly constraints. We would previously silently let all arguments through for these constraints. In cases where the constraints were violated, we could end up failing to select instructions and triggering assertions or worse, silently ignoring instructions. llvm-svn: 225244
* Fix formatting. NFC.Craig Topper2014-12-271-2/+2
| | | | llvm-svn: 224877
* Update for llvm front end change and use the TargetOptions structEric Christopher2014-12-181-5/+0
| | | | | | for ABI. llvm-svn: 224493
* Make sure that arm-linux-gnu is still the apcs-gnu ABI when weEric Christopher2014-12-181-0/+3
| | | | | | | | | | | | use clang -cc1 matching the front end and backend. Fix up a couple of tests that were testing aapcs for arm-linux-gnu. The test that removes the aapcs abi calling convention removes them because the default triple matches what the backend uses for the calling convention there and so it doesn't need to be explicitly stated - see the code in TargetInfo.cpp. llvm-svn: 224491
* [mips] Always clobber $1 for MIPS inline asm.Toma Tabacu2014-12-171-2/+1
| | | | | | | | | | | | | | | | | | | | Summary: Because GCC doesn't use $1 for code generation, inline assembly code can use $1 without having to add it to the clobbers list. LLVM, on the other hand, does not shy away from using $1, and this can cause conflicts with inline assembly which assumes GCC-like code generation. A solution to this problem is to make Clang automatically clobber $1 for all MIPS inline assembly. This is not the optimal solution, but it seems like a necessary compromise, for now. Reviewers: dsanders Reviewed By: dsanders Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D6638 llvm-svn: 224428
* Re-work the Clang system for classifying Intel x86 CPUs to use theirChandler Carruth2014-12-091-38/+71
| | | | | | | | | | | | | | | | | | | | | | | | basic microarchitecture names, and add support (with tests) for parsing all of the masic microarchitecture names for CPUs documented to be accepted by GCC with -march. I didn't go back through the 32-bit-only old microarchitectures, but this at least brings the recent architecture names up to speed. This is essentially the follow-up to the LLVM commit r223769 which did similar cleanups for the LLVM CPUs. One particular benefit is that you can now use -march=westmere in Clang and get the LLVM westmere processor which is a different ISA variant (!) and so quite significant. Much like with r223769, I would appreciate the Intel folks carefully thinking about the macros defined, names used, etc for the atom chips and newest primary x86 chips. The current patterns seem quite strange to me, especially here in Clang. Note that I haven't replicated the per-microarchitecture macro defines provided by GCC. I'm really opposed to source code using these rather than using ISA feature macros. llvm-svn: 223776
* Have the driver and the target code agree on what the default ABIEric Christopher2014-12-051-1/+36
| | | | | | | | | is for each machine. Fix up darwin tests that were testing for aapcs on armv7-ios when the actual ABI is apcs. Should be no user visible change without -cc1. llvm-svn: 223429
* CUDA host device code with two code pathsReid Kleckner2014-12-031-8/+41
| | | | | | | | | | | | | | | | | | | | | | | Summary: Allow CUDA host device functions with two code paths using __CUDA_ARCH__ to differentiate between code path being compiled. For example: __host__ __device__ void host_device_function(void) { #ifdef __CUDA_ARCH__ device_only_function(); #else host_only_function(); #endif } Patch by Jacques Pienaar. Reviewed By: rnk Differential Revision: http://reviews.llvm.org/D6457 llvm-svn: 223271
* Make le64 DescriptionString consistent with other targets.JF Bastien2014-12-021-1/+1
| | | | | | | | | | | | | | | Summary: In particular, remove the defaults and reorder fields so it matches the result of DataLayout::getStringDescription(). Change by David Neto. Reviewers: dschuff, sdt Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D6482 llvm-svn: 223140
* Update R600 address space map to include genericMatt Arsenault2014-12-011-2/+1
| | | | llvm-svn: 223046
* [OpenCL] Generic address space has been added in OpenCL v2.0.Anastasia Stulova2014-11-261-0/+7
| | | | | | | | | | To support it in the frontend, the following has been added: - generic address space type attribute; - documentation for the OpenCL address space attributes; - parsing of __generic(generic) keyword; - test code for the parser and diagnostics. llvm-svn: 222831
* [ARM] Define __ARM_FEATURE_DSP macro for CPUs that have DSP instructionsSergey Dmitrouk2014-11-251-0/+7
| | | | | | | | | | | | | | | | | Summary: This resolves [[ http://llvm.org/bugs/show_bug.cgi?id=17391 | PR17391 ]]. GCC's sources were used as a guide (couldn't find much information in ARM documentation). Reviewers: doug.gregor, asl Reviewed By: asl Subscribers: asl, aemerson, cfe-commits Differential Revision: http://reviews.llvm.org/D6339 llvm-svn: 222741
* Fix 80-column violations, trailing whitespace, comment text.Eric Christopher2014-11-181-63/+74
| | | | llvm-svn: 222269
* Basic: tweak commentSaleem Abdulrasool2014-11-171-0/+1
| | | | | | | Add a missing surrounding brace for doxygen group. This messes with pair jumping in vim and is annoying. NFC. llvm-svn: 222155
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