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* Reapply r304929 [mips] Add runtime options to enable/disable madd/sub.fmtPetar Jovanovic2017-06-071-1/+7
| | | | | | | | | | | | | | | | | The test in r304929 broke multiple buildbots as it expected mips target to be registered and available (which is not necessarily true). Updating the test with this condition. Original commit: [mips] Add runtime options to enable/disable madd.fmt and msub.fmt Add options to clang: -mmadd4 and -mno-madd4, use it to enable or disable generation of madd.fmt and similar instructions respectively, as per GCC. Patch by Stefan Maksimovic. llvm-svn: 304953
* Revert r304929 [mips] Add runtime options to enable/disable madd/sub.fmtPetar Jovanovic2017-06-071-7/+1
| | | | | | | | | | | | | | | Revert r304929 since the test broke buildbots. Original commit: [mips] Add runtime options to enable/disable madd.fmt and msub.fmt Add options to clang: -mmadd4 and -mno-madd4, use it to enable or disable generation of madd.fmt and similar instructions respectively, as per GCC. Patch by Stefan Maksimovic. llvm-svn: 304935
* [mips] Add runtime options to enable/disable madd.fmt and msub.fmtPetar Jovanovic2017-06-071-1/+7
| | | | | | | | | | | Add options to clang: -mmadd4 and -mno-madd4, use it to enable or disable generation of madd.fmt and similar instructions respectively, as per GCC. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D33401 llvm-svn: 304929
* [CodeGen] Add thumb-mode to target-features for arm/thumb triples.Florian Hahn2017-06-071-0/+7
| | | | | | | | | | | | | | | | | | | | | Summary: The thumb-mode target feature is used to force Thumb or ARM code generation on a per-function basis. Explicitly adding +thumb-mode to functions for thumbxx triples enables mixed ARM/Thumb code generation in places where compilation units with thumbxx and armxx triples are merged together (e.g. the IR linker or LTO). For armxx triples, -thumb-mode is added in a similar fashion. Reviewers: echristo, t.p.northover, kristof.beyls, rengolin Reviewed By: echristo Subscribers: rinon, aemerson, mehdi_amini, javed.absar, cfe-commits Differential Revision: https://reviews.llvm.org/D33448 llvm-svn: 304897
* [ARM] Fix Neon vector type alignment to 64-bitJaved Absar2017-06-071-0/+4
| | | | | | | | | | This is restricted version of patch - https://reviews.llvm.org/D33205 that I reverted as it was leading to ABI breaks on darwin etc. This patch restricts the fix to AAPCS (Android remains 128-bit). Reviewed by: Renato Golin, Stephen Hines Differential Revision: https://reviews.llvm.org/D33786 llvm-svn: 304889
* [WebAssembly] Set MaxAtomicInlineWidth to 64.Dan Gohman2017-06-071-1/+1
| | | | | | | | The WebAssembly threads proposal has changed such that C++ implementations can now declare that atomics up to 64 bits are "lock free" in C++'s terms. llvm-svn: 304859
* [ARM] Add support for target("arm") and target("thumb").Florian Hahn2017-06-061-1/+11
| | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds support for the target("arm") and target("thumb") attributes, which can be used to force the compiler to generated ARM or Thumb code for a function. In LLVM, ARM or Thumb code generation can be controlled by the thumb-mode target feature. But GCC already uses target("arm") and target("thumb"), so we have to substitute "arm" with -thumb-mode and "thumb" with +thumb-mode. Reviewers: echristo, pcc, kristof.beyls Reviewed By: echristo Subscribers: ahatanak, aemerson, javed.absar, kristof.beyls, cfe-commits Differential Revision: https://reviews.llvm.org/D33721 llvm-svn: 304781
* Revert "[AArch64] Add ARMv8.2-A FP16 vefctor intrinsics"Vedant Kumar2017-06-021-10/+0
| | | | | | | | | | | | This reverts commit r304493. It breaks all the Darwin bots: http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental_check/37168 Failure: Failing Tests (2): Clang :: CodeGen/aarch64-v8.2a-neon-intrinsics.c Clang :: CodeGen/arm_neon_intrinsics.c llvm-svn: 304509
* [AArch64] Add ARMv8.2-A FP16 vefctor intrinsicsAbderrazek Zaafrani2017-06-011-0/+10
| | | | llvm-svn: 304493
* [OpenCL] Makes kernels use the SPIR_KERNEL CC by default.Pekka Jaaskelainen2017-06-011-0/+16
| | | | | | | | | | | | | | | | Rationale: OpenCL kernels are called via an explicit runtime API with arguments set with clSetKernelArg(), not as normal sub-functions. Return SPIR_KERNEL by default as the kernel calling convention to ensure the fingerprint is fixed such way that each OpenCL argument gets one matching argument in the produced kernel function argument list to enable feasible implementation of clSetKernelArg() with aggregates etc. In case we would use the default C calling conv here, clSetKernelArg() might break depending on the target-specific conventions; different targets might split structs passed as values to multiple function arguments etc. https://reviews.llvm.org/D33639 llvm-svn: 304389
* Reverting Neon vector type 64-alignment fixJaved Absar2017-05-301-5/+0
| | | | | | | The patch caused ABI breaks on darwin/others. Reverting to come back with a more restrictive patch. llvm-svn: 304220
* [ARM] Fix Neon vector type alignment to 64-bitJaved Absar2017-05-301-0/+5
| | | | | | | | | | | The maximum alignment for ARM NEON data types should be 64-bits as specified in ARM procedure call standard document Sec. A.2 Notes. This patch fixes it from its current larger natural default values, except for Android (so as not to break existing ABI). Reviewed by: Stephen Hines, Renato Golin. Differential Revision: https://reviews.llvm.org/D33205 llvm-svn: 304201
* Only define __SIZEOF_FLOAT128__ on x86 as intended in r304012Reid Kleckner2017-05-261-0/+3
| | | | | | GCC only defines it on x86. llvm-svn: 304013
* Enable __float128 for mingw for GCC compatibility and define ↵Reid Kleckner2017-05-261-1/+4
| | | | | | | | | | | | __SIZEOF_FLOAT128__ on x86 GCC defines __FLOAT128__ on Power and __SIZEOF_FLOAT128__ on x86. We're just following the inconsistency for now so users have some way to test. Effectively merges this patch as requested by Martell Malone: https://github.com/Alexpux/MINGW-packages/blob/master/mingw-w64-clang/0107-enable-__float128-for-X86-MinGW.patch llvm-svn: 304012
* [X86] Adding avx512_vpopcntdq feature set and its intrinsicsOren Ben Simhon2017-05-251-4/+12
| | | | | | | | | | AVX512_VPOPCNTDQ is a new feature set that was published by Intel. The patch represents the Clang side of the addition of six intrinsics for two new machine instructions (vpopcntd and vpopcntq). It also includes the addition of the new feature set. Differential Revision: https://reviews.llvm.org/D33170 llvm-svn: 303857
* Basic: fix whitespace in file header (NFC)Saleem Abdulrasool2017-05-241-1/+1
| | | | llvm-svn: 303804
* Removed fallthrough annotation which does not directly precede switch label.Galina Kistanova2017-05-231-2/+0
| | | | llvm-svn: 303653
* Added LLVM_FALLTHROUGH to address gcc warning: this statement may fall through.Galina Kistanova2017-05-231-1/+45
| | | | llvm-svn: 303649
* [AMDGPU] Do not require opencl triple environment for OpenCLYaxun Liu2017-05-231-6/+11
| | | | | | | | | | | | A recent change requires opencl triple environment for compiling OpenCL program, which causes regressions in libclc. This patch fixes that. Instead of deducing language based on triple environment, it checks LangOptions. Differential Revision: https://reviews.llvm.org/D33445 llvm-svn: 303644
* CodeGen: Cast alloca to expected address spaceYaxun Liu2017-05-181-20/+44
| | | | | | | | | | | Alloca always returns a pointer in alloca address space, which may be different from the type defined by the language. For example, in C++ the auto variables are in the default address space. Therefore cast alloca to the expected address space when necessary. Differential Revision: https://reviews.llvm.org/D32248 llvm-svn: 303370
* [SPARC] Support 'f' and 'e' inline asm constraints.James Y Knight2017-05-121-0/+5
| | | | | | | | Patch by Patrick Boettcher. Differential Revision: https://reviews.llvm.org/D29117 llvm-svn: 302913
* [X86][LWP] Add clang support for LWP instructions.Simon Pilgrim2017-05-081-0/+8
| | | | | | | | This patch adds support for the the LightWeight Profiling (LWP) instructions which are available on all AMD Bulldozer class CPUs (bdver1 to bdver4). Differential Revision: https://reviews.llvm.org/D32770 llvm-svn: 302418
* [ARM] Limit the diagnose when an ISR calls a regular functionWeiming Zhao2017-05-051-0/+1
| | | | | | | | | | | | | | | | Summary: When the function is compiled with soft-float or on CPU with no FPU, we don't need to diagnose for a call from an ISR to a regular function. Reviewers: jroelofs, eli.friedman Reviewed By: jroelofs Subscribers: aemerson, rengolin, javed.absar, cfe-commits Differential Revision: https://reviews.llvm.org/D32918 llvm-svn: 302274
* Darwin: Define __STDC_NO_THREADS__ on Darwin targetsDuncan P. N. Exon Smith2017-04-271-0/+1
| | | | | | | | | Darwin doesn't support C11 threads.h. Define `__STDC_NO_THREADS__` so that users can check for it. rdar://problem/18461003 llvm-svn: 301508
* [ARM,AArch64] Define __ELF__ for arm-none-eabihf and AArch64Oliver Stannard2017-04-181-1/+8
| | | | | | | This macro is defined for arm-none-eabi as of r266625, but it should also be defined for eabihf and aarch64. llvm-svn: 300549
* When we turn on vsx it should also turn on altivec explicitly, sameEric Christopher2017-04-151-19/+21
| | | | | | | | | with disabling it as well as disabling all vsx specific features when turning off altivec. Fixes PR32663. llvm-svn: 300395
* [AMDGPU][GFX9] Set +fp32-denormals for >=gfx900 unless -cl-denorms-are-zero ↵Konstantin Zhuravlyov2017-04-141-3/+6
| | | | | | | | is set Differential Revision: https://reviews.llvm.org/D31482 llvm-svn: 300306
* [OpenCL] Map default address space to alloca address spaceYaxun Liu2017-04-111-1/+7
| | | | | | | | | | | | | | For OpenCL, the private address space qualifier is 0 in AST. Before this change, 0 address space qualifier is always mapped to target address space 0. As now target private address space is specified by alloca address space in data layout, address space qualifier 0 needs to be mapped to alloca addr space specified by the data layout. This change has no impact on targets whose alloca addr space is 0. With contributions from Matt Arsenault, Tony Tye and Wen-Heng (Jack) Chung Differential Revision: https://reviews.llvm.org/D31404 llvm-svn: 299965
* [AMDGPU] Temporarily change constant address space from 4 to 2 for the new ↵Yaxun Liu2017-04-061-4/+4
| | | | | | | | | | address space mapping Change constant address space from 4 to 2 for the new address space mapping in Clang. Differential Revision: https://reviews.llvm.org/D31771 llvm-svn: 299691
* Default enable the rtm feature only on skylake and later for now because ↵Eric Christopher2017-03-281-1/+1
| | | | | | | | | | Intel disabled the feature on some haswell and broadwell processors: http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/core-m-processor-family-spec-update.pdf the -mrtm option will still work normally. llvm-svn: 298956
* _CALL_LINUX is only defined on 64-bit ppc linux platforms, not 32-bit.Eric Christopher2017-03-251-3/+3
| | | | | | Adjust and add a test for the 32-bit side. llvm-svn: 298778
* [AMDGPU] Make AMDGPUTargetInfo::AS privateYaxun Liu2017-03-251-2/+1
| | | | llvm-svn: 298773
* Update the comment on not yet generated preprocessor defines to remove ↵Eric Christopher2017-03-251-1/+0
| | | | | | __LONGDOUBLE128. llvm-svn: 298771
* Add the __LONGDOUBLE128 define for ppc targets that have 128 bit long doubles.Eric Christopher2017-03-251-1/+3
| | | | llvm-svn: 298770
* Define __HAVE_BSWAP__ on ppc to match gcc since we support both builtins as ↵Eric Christopher2017-03-251-1/+3
| | | | | | well. llvm-svn: 298769
* [AMDGPU] Switch address space mapping by triple environment amdgizYaxun Liu2017-03-251-26/+66
| | | | | | | | For target environment amdgiz and amdgizcl (giz means Generic Is Zero), AMDGPU will use new address space mapping where generic address space is 0 and private address space is 5. The data layout is also changed correspondingly. Differential Revision: https://reviews.llvm.org/D31210 llvm-svn: 298767
* Add the _CALL_LINUX preprocessor define for ppc linux platforms.Eric Christopher2017-03-251-0/+6
| | | | | | | | This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but our ppc suppport post-dates this and it should work on all linux platforms. It is guaranteed to work on all elfv2 platforms. llvm-svn: 298765
* __BIGGEST_ALIGNMENT__ has always been 16 on all power platforms ratherEric Christopher2017-03-251-2/+1
| | | | | | than the default of 8 in clang, fix and update tests accordingly. llvm-svn: 298761
* Add preprocessor defines for a bare powerpc64le triple/cpu.Eric Christopher2017-03-251-62/+72
| | | | | | | The le triple didn't exist until power8, so use that as a default (this also matches what gcc does). llvm-svn: 298759
* Move setting of LangOpts based on target flags out of CompilerInstanceEric Christopher2017-03-221-0/+7
| | | | | | | | | and into TargetInfo::adjust so that it gets called in more places throughout the compiler (AST serialization in particular). Should fix PPC modules after removing of faltivec. llvm-svn: 298487
* Remove the -faltivec alias option and replace it with -maltivec everywhere.Eric Christopher2017-03-211-19/+22
| | | | | | | | | | | The alias was only ever used on darwin and had some issues there, and isn't used in practice much. Also fixes a problem with -mno-altivec not turning off -maltivec. Also add a diagnostic for faltivec/fno-altivec that directs users to use maltivec options and include the altivec.h file explicitly. llvm-svn: 298449
* Turn on HTM on power8 and later (including powerpc64le) since it'sEric Christopher2017-03-201-0/+5
| | | | | | available by default on those cpus and configurations. llvm-svn: 298307
* [Hexagon] Recognize hexagonv62 as a valid target CPUKrzysztof Parzyszek2017-03-141-0/+4
| | | | llvm-svn: 297778
* AMDGPU: Make 0 the private nullptr valueMatt Arsenault2017-03-131-1/+1
| | | | | | | | | | | | We can't actually pretend that 0 is valid for address space 0. r295877 added a workaround to stop allocating user objects there, so we can use 0 as the invalid pointer. Some of the tests seemed to be using private as the non-0 null test address space, so add copies using local to make sure this is still stressed. llvm-svn: 297659
* [AMDGPU] Add builtin functions readlane ds_permute mov_dppYaxun Liu2017-03-101-0/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D30551 llvm-svn: 297436
* [DebugInfo] Add address space when creating DIDerivedTypesKonstantin Zhuravlyov2017-03-081-0/+26
| | | | | | Differential Revision: https://reviews.llvm.org/D29671 llvm-svn: 297321
* Set the Int64Type / IntMaxType types correctly for OpenBSD/mips64Brad Smith2017-03-061-1/+5
| | | | llvm-svn: 297098
* Migrate all of aarch64-linux-gnu to \01_mcount instead of just when passing ↵Eric Christopher2017-02-281-2/+3
| | | | | | | | along gnueabi as this matches both gcc and what the kernel expects. More of PR27311 llvm-svn: 296490
* Set ABIs correctly for OpenBSD/arm; soft float and aapcs-linux.Brad Smith2017-02-281-0/+2
| | | | llvm-svn: 296430
* AMDGPU: Add fmed3 half builtinMatt Arsenault2017-02-221-0/+3
| | | | llvm-svn: 295874
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