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* [AArch64] Define the macro __ARM_FP16_ARGSKeith Walker2015-08-241-0/+1
| | | | | | | | | | | | | The ACLE (ARM C Language Extensions) 2.0 defines that the predefined macro __ARM_FP16_ARGS should be defined if __fp16 can be used as an argument and result. The support for __fp16 to be used as an argument and result is already implemented for AArch64 so this change is just adding the missing macro. Differential Revision: http://reviews.llvm.org/D12240 llvm-svn: 245833
* Revert the 64bit part of r245084; long double values were not changed byYaron Keren2015-08-201-4/+1
| | | | | | it as they are already set correctly by X86_64TargetInfo and X86TargetInfo. llvm-svn: 245620
* Revert the 32bit part of r245084; mingw values were correct before it.Yaron Keren2015-08-201-5/+1
| | | | llvm-svn: 245618
* According to i686 ABI, long double size on x86 is 12 bytes not 16 bytes.Yaron Keren2015-08-191-1/+2
| | | | | | | See https://gcc.gnu.org/onlinedocs/gcc-3.2/gcc/i386-and-x86-64-Options.html llvm-svn: 245459
* [ARM] Proper generic cpus handlingVladimir Sukharev2015-08-191-12/+10
| | | | | | | | | | | | | | "generic" cpu was wrongly handled as exact real CPU name of ARMv8.1A architecture. This has been fixed, now it is abstract name, suitable for any arch. Reviewers: rengolin Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D11640 llvm-svn: 245445
* Rename getDefaultFeatures -> initDefaultFeatures and update commentEric Christopher2015-08-191-10/+10
| | | | | | with the current behavior as the name seems to match what's going on. llvm-svn: 245405
* Remove dead code, there's no need for an override that just duplicatesEric Christopher2015-08-171-2/+0
| | | | | | the default behavior. llvm-svn: 245251
* WindowsX86: long double is x87DoubleExtended on mingwMartell Malone2015-08-141-2/+8
| | | | | | | | | | | | | | | | Summary: long double on x86 mingw is 80bits and is aligned to 16bytes Fixes: https://llvm.org/bugs/show_bug.cgi?id=24398 Reviewers: rnk Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D12037 llvm-svn: 245084
* Windows ARM: ignore calling conventions as described on MSDNMartell Malone2015-08-141-0/+13
| | | | | | | | | | | | | | | | | | Summary: MSDN says that fastcall, stdcall, thiscall, and vectorcall are all accepted but ignored on ARM and X64. https://msdn.microsoft.com/en-us/library/984x0h58.aspx MSDN also says cdecl is also accepted and typically ignored This patch brings ARM in line with how we ignore them for X64 Reviewers: rnk Subscribers: compnerd, cfe-commits Differential Revision: http://reviews.llvm.org/D12034 llvm-svn: 245076
* Removed one too many braces.Brad Smith2015-08-131-0/+1
| | | | llvm-svn: 244962
* [SPARC] Fix types of size_t, intptr_t, and ptrdiff_t on OpenBSD.Brad Smith2015-08-131-7/+10
| | | | llvm-svn: 244961
* Rangify some for loops; NFC.Aaron Ballman2015-08-121-6/+5
| | | | llvm-svn: 244749
* [MIPS] Use arch values for lock-free atomic operationsPetar Jovanovic2015-08-111-2/+1
| | | | | | | | | Let NaClMips32ELTargetInfo inherit arch values for maximum width lock-free atomic operations. Differential Revision: http://reviews.llvm.org/D11949 llvm-svn: 244675
* Update a comment to be more descriptive.Eric Christopher2015-08-071-1/+1
| | | | llvm-svn: 244346
* Make sure the Features field of the Builtin Info struct is always ↵Craig Topper2015-08-071-30/+39
| | | | | | | | initialized. Silences -Wmissing-field-initializers. While there convert 0 in the BUILTIN macros to nullptr. llvm-svn: 244307
* Make 'arm' cover both 32 and 64 bit architecutresBen Langmuir2015-08-071-0/+2
| | | | | | | | | | | | | | | | ... and add aarch32 to specifically refer to the 32-bit ones. Previously, 'arm' meant only 32-bit architectures and there was no way for a module to build with both 32 and 64 bit ARM architectures. Now a module that is intended to work on both architectures can specify requires arm whereas a module only for 32-bit platforms can say requires aarch32 and just like before, 64-bit only can say requires aarch64 llvm-svn: 244306
* Continue the work from r243908 by adding a Features field to Builtin::InfoEric Christopher2015-08-061-2/+4
| | | | | | | | so that we can populate it on a per-target basis with required features. Future commits will start using this information for warnings. llvm-svn: 244286
* Rename DescriptionString -> DataLayoutString as it matches the actualEric Christopher2015-08-051-85/+83
| | | | | | use of the string. llvm-svn: 244178
* Add support for System z vector language extensionsUlrich Weigand2015-07-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The z13 vector facility has an associated language extension, closely modeled on AltiVec/VSX. The main differences are: - vector long, vector float and vector pixel are not supported - vector long long and vector double are supported (like VSX) - comparison operators return a vector rather than a scalar integer - shift operators behave like the OpenCL shift operators - vector bool is only supported as argument to certain operators; some operators allow mixing a bool with a non-bool vector This patch adds clang support for the extension. It is closely modelled on the AltiVec support. Similarly to the -faltivec option, there's a new -fzvector option to enable the extensions (as well as an -mzvector alias for compatibility with GCC). There's also a separate LangOpt. The extension as implemented here is intended to be compatible with the -mzvector extension recently implemented by GCC. Based on a patch by Richard Sandiford. Differential Revision: http://reviews.llvm.org/D11001 llvm-svn: 243642
* RegParmMax must be 0 for AArch64, as the regparm function attribute is not ↵Kristof Beyls2015-07-281-1/+0
| | | | | | supported on AArch64. llvm-svn: 243417
* [Targets] Define _M_AMD64 and _M_X64 to a more appropriate valueDavid Majnemer2015-07-261-2/+2
| | | | | | We used to define them to 1, we should have defined them to 100. llvm-svn: 243255
* Correct x86_64 Android fp128 mangled nameChih-Hung Hsieh2015-07-241-0/+4
| | | | | | | | | | These changes are for Android x86_64 targets to be compatible with current Android g++. https://llvm.org/bugs/show_bug.cgi?id=23897 Use 'g' and 'Cg' for "long double" and "long double _Complex" mangled type names. Differential Revision: http://reviews.llvm.org/D11466 llvm-svn: 243133
* Test commit.Chih-Hung Hsieh2015-07-241-3/+3
| | | | llvm-svn: 243125
* [MSVC Compatibility] Use a better predicate for __BOOL_DEFINEDDavid Majnemer2015-07-221-1/+2
| | | | | | | Instead of using CPlusPlus, use Bool. No functionality change is intended, it just makes things a tad bit more clear. llvm-svn: 242957
* Add cygwin x86_64 target.Yaron Keren2015-07-221-0/+27
| | | | | | | | Patch by Martell Malone! http://reviews.llvm.org/D11349 llvm-svn: 242914
* ARM: actually define __ARM_ARCH_7S__ for the armv7s sliceTim Northover2015-07-211-1/+2
| | | | | | | We ended up with the wrong predefine after the recent TargetParser shuffle, and I accidentally solidified it with a test. This should fix it. llvm-svn: 242841
* [X86, inlineasm] Improve analysis of x,Y0,Yi,Ym,Yt,L,e,Z,s asm constraints ↵Alexey Bataev2015-07-201-21/+51
| | | | | | | | | (patch by Alexey Frolov) Improve Sema checking of 9 existing inline asm constraints (‘x’, ‘Y*’, ‘L’, ‘e’, ‘Z’, ‘s’). Differential Revision: http://reviews.llvm.org/D10536 llvm-svn: 242665
* basic: default to MSVC on WindowsSaleem Abdulrasool2015-07-171-6/+3
| | | | | | | | | | | The "armv7-windows", "i686-windows", and "x86_64-windows" targets should be equivalent to the MSVC environment. This was previously discussed when the triples for Windows werw canonicalised. Im not sure how this was overlooked. This fixes the emission of non-COFF formats on Windows. Thanks to ki9a for reporting this issue over IRC! llvm-svn: 242574
* R600: Add macro defs for all supported OpenCL extensionsTom Stellard2015-07-171-1/+9
| | | | llvm-svn: 242523
* Fix android build after r242514Tamas Berghammer2015-07-171-1/+1
| | | | | | | On android std::to_string isn't supported. Replace it with llvm::utostr. llvm-svn: 242516
* -Refactored ARMTargetInfo in order to use the API of TargetParserAlexandros Lamprineas2015-07-171-156/+150
| | | | | | | | | | | for extracting target specific information. -Patches commit r241343: case 'armv7l' was unhandled in ARMTargetInfo::getCPUAttr(), and thus it was returning invalid characters for macro definition. Change-Id: I1a0972e5ff5529cd17376c6562047bab8b4da32c Phabricator: http://reviews.llvm.org/D10839 llvm-svn: 242514
* Allow __builtin_setjmp/__builtin_longjmp on ARMMatthias Braun2015-07-171-0/+4
| | | | | | | | The problems in the llvm target got fixed in r242481 and r242482. Related to rdar://20544153, rdar://20660786 llvm-svn: 242489
* [Targets] Define __BOOL_DEFINED for Windows targets in C++ modeDavid Majnemer2015-07-151-0/+2
| | | | | | | | | | MSVC 4.2 didn't have bool as a builtin type but MSVC 5.0 does. When they added it, they added a macro (__BOOL_DEFINED) which allows build scripts and the like to know if they should provide their own bool. Clang always supports bool as a builtin type in C++ mode. llvm-svn: 242307
* Add support for armv7-windows-gnu targets to the clang front end.Yaron Keren2015-07-151-0/+43
| | | | | | | | | http://reviews.llvm.org/D11071 Patch by Martell Malone Reviewed by Reid Kleckner llvm-svn: 242292
* Add a "maximum TLS alignment" characteristic to the target info, so itPaul Robinson2015-07-141-0/+2
| | | | | | | | | | can be different from the normal variable maximum. Add an error diagnostic for when TLS variables exceed maximum TLS alignment. Currenty only PS4 sets an explicit maximum TLS alignment. Patch by Charles Li! llvm-svn: 242198
* Fix a couple of typos: specifc->specific.Eric Christopher2015-07-101-1/+1
| | | | llvm-svn: 241924
* Add missing builtins to altivec.h for ABI compliance (vol. 3)Nemanja Ivanovic2015-07-101-2/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D10972 Fix for the handling of dependent features that are enabled by default on some CPU's (such as -mvsx, -mpower8-vector). Also provides a number of new interfaces or fixes existing ones in altivec.h. Changed signatures to conform to ABI: vector short vec_perm(vector signed short, vector signed short, vector unsigned char) vector int vec_perm(vector signed int, vector signed int, vector unsigned char) vector long long vec_perm(vector signed long long, vector signed long long, vector unsigned char) vector signed char vec_sld(vector signed char, vector signed char, const int) vector unsigned char vec_sld(vector unsigned char, vector unsigned char, const int) vector bool char vec_sld(vector bool char, vector bool char, const int) vector unsigned short vec_sld(vector unsigned short, vector unsigned short, const int) vector signed short vec_sld(vector signed short, vector signed short, const int) vector signed int vec_sld(vector signed int, vector signed int, const int) vector unsigned int vec_sld(vector unsigned int, vector unsigned int, const int) vector float vec_sld(vector float, vector float, const int) vector signed char vec_splat(vector signed char, const int) vector unsigned char vec_splat(vector unsigned char, const int) vector bool char vec_splat(vector bool char, const int) vector signed short vec_splat(vector signed short, const int) vector unsigned short vec_splat(vector unsigned short, const int) vector bool short vec_splat(vector bool short, const int) vector pixel vec_splat(vector pixel, const int) vector signed int vec_splat(vector signed int, const int) vector unsigned int vec_splat(vector unsigned int, const int) vector bool int vec_splat(vector bool int, const int) vector float vec_splat(vector float, const int) Added a VSX path to: vector float vec_round(vector float) Added interfaces: vector signed char vec_eqv(vector signed char, vector signed char) vector signed char vec_eqv(vector bool char, vector signed char) vector signed char vec_eqv(vector signed char, vector bool char) vector unsigned char vec_eqv(vector unsigned char, vector unsigned char) vector unsigned char vec_eqv(vector bool char, vector unsigned char) vector unsigned char vec_eqv(vector unsigned char, vector bool char) vector signed short vec_eqv(vector signed short, vector signed short) vector signed short vec_eqv(vector bool short, vector signed short) vector signed short vec_eqv(vector signed short, vector bool short) vector unsigned short vec_eqv(vector unsigned short, vector unsigned short) vector unsigned short vec_eqv(vector bool short, vector unsigned short) vector unsigned short vec_eqv(vector unsigned short, vector bool short) vector signed int vec_eqv(vector signed int, vector signed int) vector signed int vec_eqv(vector bool int, vector signed int) vector signed int vec_eqv(vector signed int, vector bool int) vector unsigned int vec_eqv(vector unsigned int, vector unsigned int) vector unsigned int vec_eqv(vector bool int, vector unsigned int) vector unsigned int vec_eqv(vector unsigned int, vector bool int) vector signed long long vec_eqv(vector signed long long, vector signed long long) vector signed long long vec_eqv(vector bool long long, vector signed long long) vector signed long long vec_eqv(vector signed long long, vector bool long long) vector unsigned long long vec_eqv(vector unsigned long long, vector unsigned long long) vector unsigned long long vec_eqv(vector bool long long, vector unsigned long long) vector unsigned long long vec_eqv(vector unsigned long long, vector bool long long) vector float vec_eqv(vector float, vector float) vector float vec_eqv(vector bool int, vector float) vector float vec_eqv(vector float, vector bool int) vector double vec_eqv(vector double, vector double) vector double vec_eqv(vector bool long long, vector double) vector double vec_eqv(vector double, vector bool long long) vector bool long long vec_perm(vector bool long long, vector bool long long, vector unsigned char) vector double vec_round(vector double) vector double vec_splat(vector double, const int) vector bool long long vec_splat(vector bool long long, const int) vector signed long long vec_splat(vector signed long long, const int) vector unsigned long long vec_splat(vector unsigned long long, vector bool int vec_sld(vector bool int, vector bool int, const int) vector bool short vec_sld(vector bool short, vector bool short, const int) llvm-svn: 241904
* [MIPS] Add support for direct-to-nacl in ClangPetar Jovanovic2015-07-081-1/+14
| | | | | | | | | | | For Mips direct-to-nacl, the goal is to be close to le32 front-end and use Mips32EL backend. This patch defines new NaClMips32ELTargetInfo and modifies it slightly to be close to le32. It also adds necessary parts, inline with ARM and X86. Differential Revision: http://reviews.llvm.org/D10739 llvm-svn: 241678
* Revert "Refactored ARMTargetInfo in order to use the API of ↵Renato Golin2015-07-031-78/+118
| | | | | | | | llvm/lib/Support/TargetParser.cpp This reverts commit r241343, as it was, again, breaking all ARM buildbots. llvm-svn: 241362
* - Refactored ARMTargetInfo in order to use the API of ↵Alexandros Lamprineas2015-07-031-118/+78
| | | | | | | | | | | llvm/lib/Support/TargetParser.cpp for extracting target specific information. - Patch for commit 241267: ShouldUseInlineAtomic was set incorrectly when subArch was not specified, causing regressions. Change-Id: Iabb35d59722f4972f1a3ab4365880add5bbcfdcc llvm-svn: 241343
* Revert "Refactored ARMTargetInfo in order to use the API of ↵Rafael Espindola2015-07-021-72/+117
| | | | | | | | llvm/lib/Support/TargetParser.cpp for extracting target specific information." This reverts commit r241267. Tests were failing on the bots. llvm-svn: 241275
* Refactored ARMTargetInfo in order to use the API of ↵Alexandros Lamprineas2015-07-021-117/+72
| | | | | | | | | llvm/lib/Support/TargetParser.cpp for extracting target specific information. Change-Id: Ia0b83ecdb8d9223f9c4ef38dd9206969f78e53f3 llvm-svn: 241267
* test commitAlexandros Lamprineas2015-07-021-0/+2
| | | | | Change-Id: Ibaa2e1115544ddfa491335b81226819fd9cc04b4 llvm-svn: 241260
* [OPENMP] Introduced type trait "__builtin_omp_required_simd_align" for ↵Alexey Bataev2015-07-021-0/+4
| | | | | | | | | default simd alignment. Adds type trait "__builtin_omp_required_simd_align" after discussions here http://reviews.llvm.org/D9894 Differential Revision: http://reviews.llvm.org/D10597 llvm-svn: 241237
* Fix sse4 for target attribute feature additions.Eric Christopher2015-07-011-1/+14
| | | | | | | | | | This reinstates part of the hack removed in r233223, by special casing sse4 as part of the feature additions. The notable change here is that we consider it only as part of setting the SSE level and not as part of the actual target features set which handles setting the rest of the masks. llvm-svn: 241130
* Add support for the x86 builtin __builtin_cpu_supports.Eric Christopher2015-06-291-0/+28
| | | | | | | | | | | | | | | | | | | | This matches the implementation of the gcc support for the same feature, including checking the values set up by libgcc at runtime. The structure looks like this: unsigned int __cpu_vendor; unsigned int __cpu_type; unsigned int __cpu_subtype; unsigned int __cpu_features[1]; with a set of enums to match various fields that are field out after parsing the output of the cpuid instruction. This also adds a set of errors checking for valid input (and cpu). compiler-rt support for this and the other builtins in this family (__builtin_cpu_init and __builtin_cpu_is) are forthcoming. llvm-svn: 240994
* [ARM] The bits set in the variable HW_FP could get unsetRanjeet Singh2015-06-241-6/+10
| | | | | | | | | | | | when iterating through the Features vector if we don't keep track of what's already been set. This could lead to the macro __ARM_FP getting the wrong value. This patch fixes this issue by keeping track of the bits that have already been set in the loop. Differential Revision: http://reviews.llvm.org/D10395 llvm-svn: 240607
* [CodeGen] Teach X86_64ABIInfo about AVX512.Ahmed Bougacha2015-06-221-1/+3
| | | | | | | | | | | | | | | | As specified in the SysV AVX512 ABI drafts. It follows the same scheme as AVX2: Arguments of type __m512 are split into eight eightbyte chunks. The least significant one belongs to class SSE and all the others to class SSEUP. This also means we change the OpenMP SIMD default alignment on AVX512. Based on r240337. Differential Revision: http://reviews.llvm.org/D9894 llvm-svn: 240338
* AMDGPU: Fix places missed in renameMatt Arsenault2015-06-191-13/+13
| | | | llvm-svn: 240148
* AMDGPU: Add missing GK_VOLCANIC_ISLANDS to switch statementTom Stellard2015-06-181-0/+1
| | | | | | This fixes buildbot failures introduced by r240038. llvm-svn: 240059
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