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* Basic/Targets.cpp: Reformat aarch64 CPU list.Matthias Braun2016-07-271-8/+11
| | | | | | | Having 1 entry per line and an alphabetical order is clearer and reduces the risk of invalid merges. llvm-svn: 276931
* Adjust coercion of aggregates on RenderScriptPirama Arumuga Nainar2016-07-271-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: In RenderScript, the size of the argument or return value emitted in the IR is expected to be the same as the size of corresponding qualified type. For ARM and AArch64, the coercion performed by Clang can change the parameter or return value to a type whose size is different (usually larger) than the original aggregate type. Specifically, this can happen in the following cases: - Aggregate parameters of size <= 64 bytes and return values smaller than 4 bytes on ARM - Aggregate parameters and return values smaller than bytes on AArch64 This patch coerces the cases above to an integer array that is the same size and alignment as the original aggregate. A new field is added to TargetInfo to detect a RenderScript target and limit this coercion just to that case. Tests added to test/CodeGen/renderscript.c Reviewers: rsmith Subscribers: aemerson, srhines, llvm-commits Differential Revision: https://reviews.llvm.org/D22822 llvm-svn: 276904
* [Myriad]: better compatibility with vendor sourceDouglas Katzman2016-07-251-13/+29
| | | | | | | | - Accept ma{2100,2150,2150} for -mcpu - Define more preprocessor macros - Don't append "le/" to little-endian lib dirs llvm-svn: 276646
* [mips] Correct label prefixes for N32 and N64.Daniel Sanders2016-07-191-2/+2
| | | | | | | | | | | | | | | | | Summary: N32 and N64 follow the standard ELF conventions (.L) whereas O32 uses its own ($). This fixes the majority of object differences between -fintegrated-as and -fno-integrated-as. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: https://reviews.llvm.org/D22412 llvm-svn: 275967
* Allow iOS and tvOS version numbers with 2-digit major version numbers.Bob Wilson2016-07-181-8/+19
| | | | | | rdar://problem/26921601 llvm-svn: 275905
* Update switch statement to match coding standards.Simon Pilgrim2016-07-071-1/+2
| | | | llvm-svn: 274799
* [AArch64] Change the preferred alignment for char and short.Chad Rosier2016-07-071-2/+2
| | | | | | | | This reinstates commits r273280 and r273289. Original Review: http://reviews.llvm.org/D21414. llvm-svn: 274791
* Revert "[AArch64] Change the preferred alignment for char and short to word ↵Chad Rosier2016-07-071-2/+2
| | | | | | | | alignment" This reverts commit r273280 as the change was not properly approved. llvm-svn: 274766
* Fix "not all control paths return a value" warning on MSVCSimon Pilgrim2016-07-071-3/+1
| | | | | | This time without causing a 'all enums handled' warning on other compilers. llvm-svn: 274748
* Fix "not all control paths return a value" warning on MSVCSimon Pilgrim2016-07-071-0/+2
| | | | llvm-svn: 274746
* [CUDA] Add utility functions for dealing with CUDA versions / architectures.Justin Lebar2016-07-061-49/+19
| | | | | | | | | | | | | | | | | | Summary: Currently our handling of CUDA architectures is scattered all around clang. This patch centralizes it. A key advantage of this centralization is that you can now write a C++ switch on e.g. CudaArch and get a compile error if you don't handle one of the enum values. Reviewers: tra Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D21867 llvm-svn: 274681
* [CUDA] Add support for CUDA 8 and sm_60-62.Justin Lebar2016-07-061-29/+39
| | | | | | | | | | | | Summary: Also add sm_32, which was missing. Reviewers: tra Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D21778 llvm-svn: 274680
* [Sparc] Allow LEON cpu models to be selected with -mcpuJacob Baungard Hansen2016-07-041-1/+25
| | | | | | | | | | | | Summary: This change exposes the recently added LEON CPUs (D19359) in the LLVM Sparc backend to Clang, allowing the cpu's to be selected using the -mcpu flag. Reviewers: jyknight, lero_chris Subscribers: jyknight, cfe-commits Differential Revision: http://reviews.llvm.org/D21683 llvm-svn: 274487
* Add TargetInfo for 32-bit and 64-bit RenderScriptPirama Arumuga Nainar2016-07-021-0/+41
| | | | | | | | | | | | | | | | | | | Summary: The TargetInfo for 'renderscript32' and 'renderscript64' ArchTypes are subclasses of ARMleTargetInfo and AArch64leTargetInfo respectively. RenderScript32TargetInfo modifies the ARM ABI to set LongWidth and LongAlign to be 64-bits. Other than this modification, the underlying TargetInfo base classes is initialized as if they have "armv7" and "aarch64" architecture type respectively. Reviewers: rsmith, echristo Subscribers: aemerson, tberghammer, cfe-commits, danalbert, mehdi_amini, srhines Differential Revision: http://reviews.llvm.org/D21334 llvm-svn: 274409
* AMDGPU: Set amdgpu_kernel calling convention for OpenCL kernels.Nikolay Haustov2016-06-301-2/+12
| | | | | | | | | | | | | | | | | | Summary: Summary: Change Clang calling convention SpirKernel to OpenCLKernel. Set calling convention OpenCLKernel for amdgcn as well. Add virtual method .getOpenCLKernelCallingConv() to TargetCodeGenInfo and use it to set target calling convention for AMDGPU and SPIR. Update tests. Reviewers: rsmith, tstellarAMD, Anastasia, yaxunl Subscribers: kzhuravl, cfe-commits Differential Revision: http://reviews.llvm.org/D21367 llvm-svn: 274220
* [Driver][AArch64] Add support for Broadcom Vulcan core.Pankaj Gode2016-06-291-0/+1
| | | | | | | | Adding support for new Broadcom Vulcan core (ARMv8.1A). Differential Revision: http://reviews.llvm.org/D21501 llvm-svn: 274114
* AvailabilityAttr: we accept "macos" as the platform name.Manman Ren2016-06-281-1/+1
| | | | | | | | | | | | | | We continue accepting "macosx" but canonicalize it to "macos", When emitting diagnostics, we use "macOS" instead of "OS X". The PlatformName in TargetInfo is changed from "macosx" to "macos" so we can directly compare the Platform in AvailabilityAttr with the PlatformName in TargetInfo. rdar://26795172 rdar://26800775 llvm-svn: 274064
* [SPARC] Allows inlining of atomics for Sparc32 with appropriate store barrier.Chris Dewhurst2016-06-281-0/+1
| | | | | | The final change is required to extend the back-end's AtomicExpandPass that was implemented for Sparc (64 bit) and later extended for Sparc (32 bit). llvm-svn: 274012
* Revert r273950, (empty). Please recommit it with readable commit message.NAKAMURA Takumi2016-06-281-2/+0
| | | | llvm-svn: 273994
* [clang-cl] Define _MSVC_LANGDavid Majnemer2016-06-281-0/+7
| | | | | | | | | | | Recently, Microsoft added support for a flag, /std, which controls which version of the language rules MSVC should use. MSVC hasn't updated __cplusplus though. Instead, they added a new macro, _MSVC_LANG, which is defined in a similar fashion to __cplusplus. This is used to indicate which mode the compiler is in. llvm-svn: 273987
* (no commit message)Chris Dewhurst2016-06-271-0/+2
| | | | llvm-svn: 273950
* Add support for musl-libc on ARM Linux.Rafael Espindola2016-06-241-0/+2
| | | | | | Patch by Lei Zhang! llvm-svn: 273735
* [AArch64] Change the preferred alignment for char and short to word alignmentEvandro Menezes2016-06-211-2/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D21414 llvm-svn: 273280
* NVPTX: Add supported CL featuresJan Vesely2016-06-171-0/+13
| | | | | | | | | | Fixes libclc compilation broken by r269670 Reviewers: jholewinsky Differential Revision: http://reviews.llvm.org/D20389 llvm-svn: 273031
* AMDGPU: Fix supported CL featuresJan Vesely2016-06-171-23/+22
| | | | | | | | Reviewers: arsenm Differential Revision: http://reviews.llvm.org/D20388 llvm-svn: 272986
* [Sparc] setjmp and longjmp intrinsic support update to add unit tests and ↵Chris Dewhurst2016-06-151-1/+0
| | | | | | | | remove accidentally checked-in code. Related to revision r272782 llvm-svn: 272798
* [Sparc] Change to let clang know that setjmp and longjmp intrinsics are ↵Chris Dewhurst2016-06-151-0/+5
| | | | | | | | implemented in the back-end. Differential Revision: http://reviews.llvm.org/D19798 llvm-svn: 272782
* [mips] Defer validity check for CPU/ABI pairs and improve error message for ↵Daniel Sanders2016-06-141-34/+79
| | | | | | | | | | | | | | | | | | | | | invalid cases. Summary: The validity of ABI/CPU pairs is no longer checked on the fly but is instead checked after initialization. As a result, invalid CPU/ABI pairs can be reported as being known but invalid instead of being unknown. For example, we now emit: error: ABI 'n32' is not supported on CPU 'mips32r2' instead of: error: unknown target ABI 'n64' Reviewers: atanasyan Subscribers: sdardis, cfe-commits Differential Revision: http://reviews.llvm.org/D21023 llvm-svn: 272645
* AMDGPU: Verify subtarget specific builtinsMatt Arsenault2016-06-081-49/+87
| | | | | | Cleanup setup of subtarget features. llvm-svn: 272091
* [mips] The P5600 does not support N32/N64 since it's a 32-bit CPU.Daniel Sanders2016-06-061-1/+1
| | | | | | | | | | | | Summary: Reviewers: atanasyan Subscribers: cfe-commits, sdardis Differential Revision: http://reviews.llvm.org/D20963 llvm-svn: 271877
* [mips] Replace almost all Arch checks in MipsTargetInfo with ABI checks. NFC.Daniel Sanders2016-06-061-51/+65
| | | | | | | | | | | | | | Summary: setABI() is still tied to the Arch component of the Triple to preserve existing behaviour. Reviewers: atanasyan Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D20961 llvm-svn: 271875
* [mips] Slightly simplify MipsTargetInfo::setDataLayout(). NFC.Daniel Sanders2016-06-031-19/+15
| | | | | | | | | | | | Summary: Reviewers: atanasyan Subscribers: atanasyan, cfe-commits Differential Revision: http://reviews.llvm.org/D20680 llvm-svn: 271647
* This adds target support and tests for Cortex-A73Sjoerd Meijer2016-06-021-0/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D20864 llvm-svn: 271507
* AMDGPU: Update datalayout stringMatt Arsenault2016-05-311-1/+1
| | | | llvm-svn: 271297
* [mips] Kill 'support' for untested EABI.Daniel Sanders2016-05-271-6/+4
| | | | | | | | | | | | | | | | | Summary: There are no llvm backend tests* for EABI and no EABI buildbots. There were only three clang tests, all of which checked that -mabi=eabi was passed to the assembler. *There is a single backend test that specifies EABI but it actually tests MIPS16. Reviewers: atanasyan Subscribers: emaste, sdardis, atanasyan, cfe-commits Differential Revision: http://reviews.llvm.org/D20679 llvm-svn: 270998
* [mips] Fold MipsTargetInfoBase subclasses into MipsTargetInfoBase and rename ↵Daniel Sanders2016-05-271-317/+209
| | | | | | | | | | | | | | | | | to MipsTargetInfo. NFC Summary: This unifies mips/mipsel and mips64/mips64el into a single class so that we can later support O32 on mips64/mips64el and N32/N64 on mips/mipsel (when an appropriate CPU selected). Reviewers: atanasyan Subscribers: atanasyan, jfb, cfe-commits, dschuff Differential Revision: http://reviews.llvm.org/D20678 llvm-svn: 270984
* Revert "[AArch64] Using new TargetParser in Clang"Renato Golin2016-05-251-4/+8
| | | | | | | | This reverts commit r270688 and r270689. The issue is not a random order, but a different order for some targets and others (prob. Linux vs Darwin). Reverting until we have a better fix. llvm-svn: 270691
* [AArch64] Using new TargetParser in ClangRenato Golin2016-05-251-8/+4
| | | | | | | | | | Using AArch64TargetParser in clang to avoid repetitive string parsing. Use TargetParser to do ARCH/CPU/ArchExt parsing instead of local implementation. Patch by Jojo Ma. llvm-svn: 270688
* [Sparc] Add software float option -msoft-floatJacob Baungard Hansen2016-05-241-3/+1
| | | | | | | | | | | | | | | Summary: Following patch D19265 which enable software floating point support in the Sparc backend, this patch enables the option to be enabled in the front-end using the -msoft-float option. The user should ensure a library (such as the builtins from Compiler-RT) that includes the software floating point routines is provided. Reviewers: jyknight, lero_chris Subscribers: jyknight, cfe-commits Differential Revision: http://reviews.llvm.org/D20419 llvm-svn: 270538
* Make __FreeBSD_cc_version predefined macro configurable at build timeDimitry Andric2016-05-201-2/+9
| | | | | | | | | | | | | | | | | | The `FreeBSDTargetInfo` class has always set the `__FreeBSD_cc_version` predefined macro to a rather static value, calculated from the major OS version. In the FreeBSD base system, we will start incrementing the value of this macro whenever we make any signifant change to clang, so we need a way to configure the macro's value at build time. Use `FREEBSD_CC_VERSION` for this, which we can define in the FreeBSD build system using either the `-D` command line option, or an include file. Stock builds will keep the earlier value. Differential Revision: http://reviews.llvm.org/D20037 llvm-svn: 270240
* Add all the avx512 flavors to __builtin_cpu_supports's list.Benjamin Kramer2016-05-201-0/+11
| | | | | | | | This is matching what trunk gcc is accepting. Also adds a missing ssse3 case. PR27779. The amount of duplication here is annoying, maybe it should be factored into a separate .def file? llvm-svn: 270224
* [Hexagon] Recognize "s" constraint in inline-asmKrzysztof Parzyszek2016-05-201-0/+3
| | | | llvm-svn: 270216
* [CUDA] Allow sm_50,52,53 GPUsArtem Belevich2016-05-191-0/+15
| | | | | | | | LLVM accepts them since r233575. Differential Revision: http://reviews.llvm.org/D20405 llvm-svn: 270084
* [Hexagon] Recognize "q" and "v" in inline-asm as register constraintsKrzysztof Parzyszek2016-05-181-1/+10
| | | | | | Clang follow-up to r269933. llvm-svn: 269934
* Add new intrinsic support for MONITORX and MWAITX instructionsAshutosh Nema2016-05-181-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: MONITORX/MWAITX instructions provide similar capability to the MONITOR/MWAIT pair while adding a timer function, such that another termination of the MWAITX instruction occurs when the timer expires. The presence of the MONITORX and MWAITX instructions is indicated by CPUID 8000_0001, ECX, bit 29. The MONITORX and MWAITX instructions are intercepted by the same bits that intercept MONITOR and MWAIT. MONITORX instruction establishes a range to be monitored. MWAITX instruction causes the processor to stop instruction execution and enter an implementation-dependent optimized state until occurrence of a class of events. Opcode of MONITORX instruction is "0F 01 FA". Opcode of MWAITX instruction is "0F 01 FB". These opcode information is used in adding tests for the disassembler. These instructions are enabled for AMD's bdver4 architecture. Patch by Ganesh Gopalasubramanian! Reviewers: echristo, craig.topper Subscribers: RKSimon, joker.eph, llvm-commits, cfe-commits Differential Revision: http://reviews.llvm.org/D19796 llvm-svn: 269907
* [PS4] Change the names of some "environmental" things to what ourPaul Robinson2016-05-161-1/+1
| | | | | | | | licensees actually see in the toolchain we deliver to them. This will reduce the set of local patches we have to maintain. The triple is not changing. (The term ORBIS is an internal code name for PS4.) llvm-svn: 269671
* [OpenCL] Add supported OpenCL extensions to target info.Yaxun Liu2016-05-161-11/+37
| | | | | | | | | | Add supported OpenCL extensions to target info. It serves as default values to save the users of the burden setting each supported extensions and optional core features in command line. Re-commit after fixing build error due to missing override attribute. Differential Revision: http://reviews.llvm.org/D19484 llvm-svn: 269670
* ARM-MachO: stop claiming to be EABITim Northover2016-05-131-1/+1
| | | | | | | | | | Embedded ARM MachO targets are AAPCS but not full EABI (we don't use __aeabi_whatever and the functions are allowed to be hard-float). Turns out there was already a test for this, but its original purpose had become corrupted over the years. llvm-svn: 269487
* Revert "[OpenCL] Add supported OpenCL extensions to target info."Yaxun Liu2016-05-131-37/+11
| | | | | | | | | Revert r269431 due to build failure caused by warning msg: llvm/tools/clang/lib/Basic/Targets.cpp:2090:9: error: 'setSupportedOpenCLOpts' overrides a member function but is not marked 'override' [-Werror,-Winconsistent-missing-override] void setSupportedOpenCLOpts() { llvm-svn: 269435
* [OpenCL] Add supported OpenCL extensions to target info.Yaxun Liu2016-05-131-11/+37
| | | | | | | | Add supported OpenCL extensions to target info. It serves as default values to save the users of the burden setting each supported extensions and optional core features in command line. Differential Revision: http://reviews.llvm.org/D19484 llvm-svn: 269431
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