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* Hook up OpenBSD AArch64 supportBrad Smith2017-02-211-1/+4
| | | | llvm-svn: 295786
* [mips] Define macros related to -mabicalls in the preprocessorSimon Dardis2017-02-211-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Historically, NetBSD, FreeBSD and OpenBSD have defined the macro ABICALLS in the preprocessor when -mabicalls is in effect. Mainline GCC later defined __mips_abicalls when -mabicalls is in effect. This patch teaches the preprocessor to define these macros when appropriate. NetBSD does not require the ABICALLS macro. This resolves PR/31694. Thanks to Sean Bruno for highlighting this issue! Reviewers: slthakur, seanbruno Reviewed By: seanbruno Subscribers: joerg, brad, emaste, seanbruno, cfe-commits Differential Revision: https://reviews.llvm.org/D29032 llvm-svn: 295728
* Enable support for __float128 in Clang on OpenBSD/X86Brad Smith2017-02-201-3/+5
| | | | | | | /usr/local/include/c++/4.9.4/type_traits:279:39: error: __float128 is not supported on this target llvm-svn: 295635
* AMDGPU: Add gfx900 and gfx901 processorsMatt Arsenault2017-02-181-1/+4
| | | | llvm-svn: 295556
* Add a definition for __STRUCT_PARM_ALIGN__ for elfv2 and 64-bit darwin ↵Eric Christopher2017-02-151-0/+5
| | | | | | platforms to match what other compilers produce. llvm-svn: 295156
* [AVR] Fix __AVR_xxx macro definitions; authored by Peter WuDylan McKay2017-02-111-238/+238
| | | | | | | | | | | | | | | | | | Summary: The -mmcu option for GCC sets macros like __AVR_ATmega328P__ (with the trailing underscores), be sure to include these underscores for Clangs -mcpu option. See "AVR Built-in Macros" in https://gcc.gnu.org/onlinedocs/gcc/AVR-Options.html Reviewers: jroelofs, dylanmckay Reviewed By: jroelofs, dylanmckay Subscribers: efriedma, cfe-commits Differential Revision: https://reviews.llvm.org/D29817 llvm-svn: 294869
* Temporarily revert "For X86-64 linux and PPC64 linux align int128 to 16 bytes."Eric Christopher2017-02-101-40/+10
| | | | | | | | | until we can get better TargetMachine::isCompatibleDataLayout to compare - otherwise we can't code generate existing bitcode without a string equality data layout. This reverts commit r294703. llvm-svn: 294708
* For X86-64 linux and PPC64 linux align int128 to 16 bytes.Eric Christopher2017-02-101-10/+40
| | | | | | | | | | For other platforms we should find out what they need and likely make the same change, however, a smaller additional change is easier for platforms we know have it specified in the ABI. clang support for r294702 llvm-svn: 294703
* Add support for armv7ve flag in clang (PR31358).George Burgess IV2017-02-091-0/+2
| | | | | | | | | | | This is a followup change to add v7ve support to clang for gcc compatibility. Please see r294661. Patch by Manoj Gupta. Differential Revision: https://reviews.llvm.org/D29773 llvm-svn: 294662
* [X86] Clzero flag addition and inclusion under znver1Craig Topper2017-02-091-0/+7
| | | | | | | | | | | | | 1. Adds the command line flag for clzero. 2. Includes the clzero flag under znver1. 3. Defines the macro for clzero. 4. Adds a new file which has the intrinsic definition for clzero instruction. Patch by Ganesh Gopalasubramanian with some additional tests from me. Differential revision: https://reviews.llvm.org/D29386 llvm-svn: 294559
* [X86] Add -mprefetchwt1/-mno-prefetchwt1 command line options and ↵Craig Topper2017-02-081-0/+2
| | | | | | __PREFETCHWT1__ define to match gcc. llvm-svn: 294424
* [X86] Add -msgx/-mno-sgx command line options and __SGX__ define to match gcc.Craig Topper2017-02-081-0/+2
| | | | llvm-svn: 294423
* [X86] Add -mmpx/-mno-mpx command line options and __MPX__ define to match gcc.Craig Topper2017-02-081-0/+2
| | | | llvm-svn: 294419
* [X86] Add -mclwb/-mno-clwb command line arguments and __CLWB__ define to ↵Craig Topper2017-02-081-0/+2
| | | | | | | | match gcc. In the future, we should also add a clwb intrinsic to the backend, a frontend builtin, and an instrinsic header file. llvm-svn: 294416
* [X86] Remove 'umip' feature flag.Craig Topper2017-02-081-5/+0
| | | | | | This feature flag indicates that the processor has support for removing certain instructions from user mode software. But the feature flag by itself doesn't indicate if the support is enabled in the OS. The affected instructions aren't even instructions the compiler would emit. So I don't think think this feature flag should be in the compiler. llvm-svn: 294414
* [X86] Add -mclflushopt/-mno-clflushopt command line support and ↵Craig Topper2017-02-081-0/+2
| | | | | | __CLFLUSHOPT__ define to match gcc. llvm-svn: 294411
* Use LLVM_FALLTHROUGH instead of FALLTHROUGH comments.Craig Topper2017-02-081-13/+13
| | | | llvm-svn: 294404
* [X86] Remove PCOMMIT feature support since Intel has deprecated this ↵Craig Topper2017-02-081-5/+0
| | | | | | | | instruction with no plans to release products with it. Intel's documentation for the deprecation https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction llvm-svn: 294403
* Revert "Basic: match GCC behaviour for SuS macro"Saleem Abdulrasool2017-02-071-15/+15
| | | | | | | This reverts commit SVN r294148. Seems that it was mistaken, and GCC does still define `__unix` and `unix` when in GNU mode. llvm-svn: 294332
* Revert "Revert "[AVR] Allow specifying the CPU on the command line""Dylan McKay2017-02-071-0/+293
| | | | | | This reverts commit 7ac30e0f839fdab6d723ce2ef6a5b7a4cf03d150. llvm-svn: 294282
* [SystemZ] Provide predefined __ARCH__ and __VX__ macrosUlrich Weigand2017-02-061-0/+11
| | | | | | | | | | | | GCC 7 will predefine two new macros on s390x: - __ARCH__ indicates the ISA architecture level - __VX__ indicates that the vector facility is available This adds those macros to clang as well to ensure continued compatibility with GCC. llvm-svn: 294197
* Revert "[AVR] Allow specifying the CPU on the command line"Diana Picus2017-02-061-293/+0
| | | | | | This reverts commit r294177. It seems to have broken some buildbots. llvm-svn: 294180
* [AVR] Allow specifying the CPU on the command lineDylan McKay2017-02-061-0/+293
| | | | | | | | | | | | | | | | | | Summary: This tells clang about all of the different AVR microcontrollers. It also adds code to define the correct preprocessor macros for each device. Reviewers: jroelofs, asl Reviewed By: asl Subscribers: asl, cfe-commits Differential Revision: https://reviews.llvm.org/D28346 llvm-svn: 294177
* [AVR] Add support for the full set of inline asm constraintsDylan McKay2017-02-061-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Previously the method would simply return false, causing every single inline assembly constraint to trigger a compile error. This adds inline assembly constraint support for the AVR target. This patch is derived from the code in AVRISelLowering::getConstraintType. More details can be found on the AVR-GCC reference wiki http://www.nongnu.org/avr-libc/user-manual/inline_asm.html Reviewers: jroelofs, asl Reviewed By: asl Subscribers: asl, ahatanak, saaadhu, cfe-commits Differential Revision: https://reviews.llvm.org/D28344 llvm-svn: 294176
* Basic: match GCC behaviour for SuS macroSaleem Abdulrasool2017-02-051-15/+15
| | | | | | | | GCC does not generate `__unix` nor `unix` macros. The latter already intrudes into the user's namespace and should be avoided. Use the canonical spelling of `__unix__` across all the targets. llvm-svn: 294148
* AMDGPU: Update for changed subtarget feature nameMatt Arsenault2017-01-231-3/+3
| | | | llvm-svn: 292838
* [Basic] Remove the 32-bit x86 and ARM targets for FuchsiaPetr Hosek2017-01-201-6/+0
| | | | | | | | The 32-bit architectures are no longer supported by Fuchsia. Differential Revision: https://reviews.llvm.org/D28974 llvm-svn: 292671
* [WebAssembly] Add minimal support for the new wasm object format triple.Dan Gohman2017-01-171-2/+10
| | | | llvm-svn: 292269
* Ensure that clang -pthread creates the right macro. -D_POSIX_THREADSJoerg Sonnenberger2017-01-161-1/+1
| | | | | | seems to have been a C&P error from old GCC specs for OpenBSD. llvm-svn: 292119
* AMD family 17h (znver1) enablementCraig Topper2017-01-101-0/+38
| | | | | | | | | | | | | | | | | | | | | | | Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This is linked to llvm review item https://reviews.llvm.org/D28017 Patch by Ganesh Gopalasubramanian. Additional test cases added by Craig Topper. Reviewers: RKSimon, craig.topper Subscribers: cfe-commits, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28018 llvm-svn: 291544
* [CUDA] Let NVPTX inherit the host's calling conventions.Justin Lebar2017-01-051-0/+10
| | | | | | | | | | | | | | | | | | | | Summary: When compiling device code, we may still see host code with explicit calling conventions. NVPTX needs to claim that it supports these CCs, so that (a) we don't raise noisy warnings, and (b) we don't break existing code which relies on the existence of these CCs when specializing templates. (If a CC doesn't exist, clang ignores it, so two template specializations which are different only insofar as one specifies a CC are considered identical and therefore are an error if that CC is not supported.) Reviewers: tra Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D28323 llvm-svn: 291136
* [CUDA] More correctly inherit primitive types from the host during device ↵Justin Lebar2017-01-051-33/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | compilation. Summary: CUDA lets users share structs between the host and device, so for that and other reasons, primitive types such as ptrdiff_t should be the same on both sides of the compilation. Our code to do this wasn't entirely successful. In particular, we did a bunch of work during the NVPTXTargetInfo constructor, only to override it in the NVPTX{32,64}TargetInfo constructors. It worked well enough on Linux and Mac, but Windows is LLP64, which is different enough to break it. This patch removes the NVPTX{32,64}TargetInfo classes entirely and fixes the bug described above. Reviewers: tra Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D28322 llvm-svn: 291135
* [AVR] Revert the functional part of r291083Dylan McKay2017-01-051-2/+1
| | | | | | | As Senthil points out, this is unnecessary as we already have these registers in AddlRegNames. llvm-svn: 291090
* [AVR] Support r26 through r31 in inline assemblyDylan McKay2017-01-051-1/+12
| | | | | | These are synonyms for the X,Y, and Z registers. llvm-svn: 291083
* Add AVR target and toolchain to ClangDylan McKay2017-01-051-0/+93
| | | | | | | | | | | | | | | | | Summary: Authored by Senthil Kumar Selvaraj This patch adds barebones support in Clang for the (experimental) AVR target. It uses the integrated assembler for assembly, and the GNU linker for linking, as lld doesn't know about the target yet. The DataLayout string is the same as the one in AVRTargetMachine.cpp. The alignment specs look wrong to me, as it's an 8 bit target and all types only need 8 bit alignment. Clang failed with a datalayout mismatch error when I tried to change it, so I left it that way for now. Reviewers: rsmith, dylanmckay, cfe-commits, rengolin Subscribers: rengolin, jroelofs, wdng Differential Revision: https://reviews.llvm.org/D27123 llvm-svn: 291082
* [inline-asm]No error for conflict between inputs\outputs and clobber listMarina Yatsina2016-12-261-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | According to extended asm syntax, a case where the clobber list includes a variable from the inputs or outputs should be an error - conflict. for example: const long double a = 0.0; int main() { char b; double t1 = a; __asm__ ("fucompp": "=a" (b) : "u" (t1), "t" (t1) : "cc", "st", "st(1)"); return 0; } This should conflict with the output - t1 which is st, and st which is st aswell. The patch fixes it. Commit on behald of Ziv Izhar. Differential Revision: https://reviews.llvm.org/D15075 llvm-svn: 290539
* ARM: define a macro for the FPv5 FPU in ARM mode.Tim Northover2016-12-211-0/+2
| | | | | | | FPv5 is in Cortex-M7 and the 64-bit CPUs when running in 32-bit mode. The name is from the Cortex-M7 TRM. llvm-svn: 290268
* Recommit r289979 [OpenCL] Allow disabling types and declarations associated ↵Yaxun Liu2016-12-181-27/+27
| | | | | | | | with extensions Fixed undefined behavior due to cast integer to bool in initializer list. llvm-svn: 290056
* Revert r289979 due to regressionsYaxun Liu2016-12-161-27/+27
| | | | llvm-svn: 289991
* [OpenCL] Allow disabling types and declarations associated with extensionsYaxun Liu2016-12-161-27/+27
| | | | | | | | | | | | | | | | | | Added a map to associate types and declarations with extensions. Refactored existing diagnostic for disabled types associated with extensions and extended it to declarations for generic situation. Fixed some bugs for types associated with extensions. Allow users to use pragma to declare types and functions for supported extensions, e.g. #pragma OPENCL EXTENSION the_new_extension_name : begin // declare types and functions associated with the extension here #pragma OPENCL EXTENSION the_new_extension_name : end Differential Revision: https://reviews.llvm.org/D21698 llvm-svn: 289979
* Re-commit r289252 and r289285, and fix PR31374Yaxun Liu2016-12-151-0/+7
| | | | llvm-svn: 289787
* Revert 289252 (and follow-up 289285), it caused PR31374Nico Weber2016-12-141-7/+0
| | | | llvm-svn: 289713
* Replace APFloatBase static fltSemantics data members with getter functionsStephan Bergmann2016-12-141-23/+23
| | | | | | | | | | | | | At least the plugin used by the LibreOffice build (<https://wiki.documentfoundation.org/Development/Clang_plugins>) indirectly uses those members (through inline functions in LLVM/Clang include files in turn using them), but they are not exported by utils/extract_symbols.py on Windows, and accessing data across DLL/EXE boundaries on Windows is generally problematic. Differential Revision: https://reviews.llvm.org/D26671 llvm-svn: 289647
* Add support for non-zero null pointer for C and OpenCLYaxun Liu2016-12-091-0/+7
| | | | | | | | | | | | | | | | | | In amdgcn target, null pointers in global, constant, and generic address space take value 0 but null pointers in private and local address space take value -1. Currently LLVM assumes all null pointers take value 0, which results in incorrectly translated IR. To workaround this issue, instead of emit null pointers in local and private address space, a null pointer in generic address space is emitted and casted to local and private address space. Tentative definition of global variables with non-zero initializer will have weak linkage instead of common linkage since common linkage requires zero initializer and does not have explicit section to hold the non-zero value. Virtual member functions getNullPointer and performAddrSpaceCast are added to TargetCodeGenInfo which by default returns ConstantPointerNull and emitting addrspacecast instruction. A virtual member function getNullPointerValue is added to TargetInfo which by default returns 0. Each target can override these virtual functions to get target specific null pointer and the null pointer value for specific address space, and perform specific translations for addrspacecast. Wrapper functions getNullPointer is added to CodegenModule and getTargetNullPointerValue is added to ASTContext to facilitate getting the target specific null pointers and their values. This change has no effect on other targets except amdgcn target. Other targets can provide support of non-zero null pointer in a similar way. This change only provides support for non-zero null pointer for C and OpenCL. Supporting for other languages will be added later incrementally. Differential Revision: https://reviews.llvm.org/D26196 llvm-svn: 289252
* [WebAssembly] Revert r288447.Dan Gohman2016-12-031-4/+0
| | | | | | | Revert r288447 which introduced -mdirect. It turns out we don't need a custom flag for this, as the information we need is in the target triple. llvm-svn: 288604
* [WebAssembly] Add an -mdirect flag for the direct wasm object feature.Dan Gohman2016-12-021-0/+4
| | | | | | | Add a target flag for enabling the new direct wasm object emission feature. llvm-svn: 288447
* Add a little endian variant of TCE.Pekka Jaaskelainen2016-11-161-2/+33
| | | | llvm-svn: 287112
* Define __ANDROID_API__ when specified as part of an Android target.Stephen Hines2016-11-111-0/+2
| | | | | | | | | | | | | | | | | Summary: This macro should be defined only when the user directly specifies an API level as part of an Android target. For any regular Android target, we leave this macro undefined. Bug: https://llvm.org/bugs/show_bug.cgi?id=30940 Reviewers: eugenis, pirama Subscribers: tberghammer, cfe-commits, pirama, eugenis, danalbert Differential Revision: https://reviews.llvm.org/D26491 llvm-svn: 286543
* [Sparc] LLONG is not lock-free atomic on v8Douglas Katzman2016-11-091-1/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D26286 llvm-svn: 286376
* [AVX-512] Make VBMI instruction set enabling imply that the BWI instruction ↵Craig Topper2016-11-091-0/+6
| | | | | | | | | | | | | | set is also enabled. Summary: This is needed to make the v64i8 and v32i16 types legal for the 512-bit VBMI instructions. Fixes PR30912. Reviewers: delena, zvi Subscribers: RKSimon, cfe-commits Differential Revision: https://reviews.llvm.org/D26306 llvm-svn: 286340
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