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* Add AVR target and toolchain to ClangDylan McKay2017-01-051-0/+93
| | | | | | | | | | | | | | | | | Summary: Authored by Senthil Kumar Selvaraj This patch adds barebones support in Clang for the (experimental) AVR target. It uses the integrated assembler for assembly, and the GNU linker for linking, as lld doesn't know about the target yet. The DataLayout string is the same as the one in AVRTargetMachine.cpp. The alignment specs look wrong to me, as it's an 8 bit target and all types only need 8 bit alignment. Clang failed with a datalayout mismatch error when I tried to change it, so I left it that way for now. Reviewers: rsmith, dylanmckay, cfe-commits, rengolin Subscribers: rengolin, jroelofs, wdng Differential Revision: https://reviews.llvm.org/D27123 llvm-svn: 291082
* [inline-asm]No error for conflict between inputs\outputs and clobber listMarina Yatsina2016-12-261-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | According to extended asm syntax, a case where the clobber list includes a variable from the inputs or outputs should be an error - conflict. for example: const long double a = 0.0; int main() { char b; double t1 = a; __asm__ ("fucompp": "=a" (b) : "u" (t1), "t" (t1) : "cc", "st", "st(1)"); return 0; } This should conflict with the output - t1 which is st, and st which is st aswell. The patch fixes it. Commit on behald of Ziv Izhar. Differential Revision: https://reviews.llvm.org/D15075 llvm-svn: 290539
* ARM: define a macro for the FPv5 FPU in ARM mode.Tim Northover2016-12-211-0/+2
| | | | | | | FPv5 is in Cortex-M7 and the 64-bit CPUs when running in 32-bit mode. The name is from the Cortex-M7 TRM. llvm-svn: 290268
* Recommit r289979 [OpenCL] Allow disabling types and declarations associated ↵Yaxun Liu2016-12-181-27/+27
| | | | | | | | with extensions Fixed undefined behavior due to cast integer to bool in initializer list. llvm-svn: 290056
* Revert r289979 due to regressionsYaxun Liu2016-12-161-27/+27
| | | | llvm-svn: 289991
* [OpenCL] Allow disabling types and declarations associated with extensionsYaxun Liu2016-12-161-27/+27
| | | | | | | | | | | | | | | | | | Added a map to associate types and declarations with extensions. Refactored existing diagnostic for disabled types associated with extensions and extended it to declarations for generic situation. Fixed some bugs for types associated with extensions. Allow users to use pragma to declare types and functions for supported extensions, e.g. #pragma OPENCL EXTENSION the_new_extension_name : begin // declare types and functions associated with the extension here #pragma OPENCL EXTENSION the_new_extension_name : end Differential Revision: https://reviews.llvm.org/D21698 llvm-svn: 289979
* Re-commit r289252 and r289285, and fix PR31374Yaxun Liu2016-12-151-0/+7
| | | | llvm-svn: 289787
* Revert 289252 (and follow-up 289285), it caused PR31374Nico Weber2016-12-141-7/+0
| | | | llvm-svn: 289713
* Replace APFloatBase static fltSemantics data members with getter functionsStephan Bergmann2016-12-141-23/+23
| | | | | | | | | | | | | At least the plugin used by the LibreOffice build (<https://wiki.documentfoundation.org/Development/Clang_plugins>) indirectly uses those members (through inline functions in LLVM/Clang include files in turn using them), but they are not exported by utils/extract_symbols.py on Windows, and accessing data across DLL/EXE boundaries on Windows is generally problematic. Differential Revision: https://reviews.llvm.org/D26671 llvm-svn: 289647
* Add support for non-zero null pointer for C and OpenCLYaxun Liu2016-12-091-0/+7
| | | | | | | | | | | | | | | | | | In amdgcn target, null pointers in global, constant, and generic address space take value 0 but null pointers in private and local address space take value -1. Currently LLVM assumes all null pointers take value 0, which results in incorrectly translated IR. To workaround this issue, instead of emit null pointers in local and private address space, a null pointer in generic address space is emitted and casted to local and private address space. Tentative definition of global variables with non-zero initializer will have weak linkage instead of common linkage since common linkage requires zero initializer and does not have explicit section to hold the non-zero value. Virtual member functions getNullPointer and performAddrSpaceCast are added to TargetCodeGenInfo which by default returns ConstantPointerNull and emitting addrspacecast instruction. A virtual member function getNullPointerValue is added to TargetInfo which by default returns 0. Each target can override these virtual functions to get target specific null pointer and the null pointer value for specific address space, and perform specific translations for addrspacecast. Wrapper functions getNullPointer is added to CodegenModule and getTargetNullPointerValue is added to ASTContext to facilitate getting the target specific null pointers and their values. This change has no effect on other targets except amdgcn target. Other targets can provide support of non-zero null pointer in a similar way. This change only provides support for non-zero null pointer for C and OpenCL. Supporting for other languages will be added later incrementally. Differential Revision: https://reviews.llvm.org/D26196 llvm-svn: 289252
* [WebAssembly] Revert r288447.Dan Gohman2016-12-031-4/+0
| | | | | | | Revert r288447 which introduced -mdirect. It turns out we don't need a custom flag for this, as the information we need is in the target triple. llvm-svn: 288604
* [WebAssembly] Add an -mdirect flag for the direct wasm object feature.Dan Gohman2016-12-021-0/+4
| | | | | | | Add a target flag for enabling the new direct wasm object emission feature. llvm-svn: 288447
* Add a little endian variant of TCE.Pekka Jaaskelainen2016-11-161-2/+33
| | | | llvm-svn: 287112
* Define __ANDROID_API__ when specified as part of an Android target.Stephen Hines2016-11-111-0/+2
| | | | | | | | | | | | | | | | | Summary: This macro should be defined only when the user directly specifies an API level as part of an Android target. For any regular Android target, we leave this macro undefined. Bug: https://llvm.org/bugs/show_bug.cgi?id=30940 Reviewers: eugenis, pirama Subscribers: tberghammer, cfe-commits, pirama, eugenis, danalbert Differential Revision: https://reviews.llvm.org/D26491 llvm-svn: 286543
* [Sparc] LLONG is not lock-free atomic on v8Douglas Katzman2016-11-091-1/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D26286 llvm-svn: 286376
* [AVX-512] Make VBMI instruction set enabling imply that the BWI instruction ↵Craig Topper2016-11-091-0/+6
| | | | | | | | | | | | | | set is also enabled. Summary: This is needed to make the v64i8 and v32i16 types legal for the 512-bit VBMI instructions. Fixes PR30912. Reviewers: delena, zvi Subscribers: RKSimon, cfe-commits Differential Revision: https://reviews.llvm.org/D26306 llvm-svn: 286340
* Revert "Define __ANDROID_API__ for all Android builds."Stephen Hines2016-11-081-2/+0
| | | | | | | | | | Summary: This reverts commit a8804ddd9fe71304b28e5b834d134fe93e568ee0. Subscribers: cfe-commits, pirama, eugenis, tberghammer, danalbert Differential Revision: https://reviews.llvm.org/D26422 llvm-svn: 286298
* Define __ANDROID_API__ for all Android builds.Stephen Hines2016-11-081-0/+2
| | | | | | | | | | | | | | | | | | Summary: Bug: https://llvm.org/bugs/show_bug.cgi?id=30940 This macro (along with __ANDROID__) should always be defined for Android targets. We set it to the major (only) version of the Android API being compiled for. The Android version is able to be set as an integer suffix for any valid Android target. Reviewers: danalbert, eugenis Subscribers: cfe-commits, pirama, eugenis, tberghammer, danalbert Differential Revision: https://reviews.llvm.org/D26385 llvm-svn: 286295
* regcall: Implement regcall Calling Conv in clangErich Keane2016-11-021-0/+3
| | | | | | | | | | This patch implements the register call calling convention, which ensures as many values as possible are passed in registers. CodeGen changes were committed in https://reviews.llvm.org/rL284108. Differential Revision: https://reviews.llvm.org/D25204 llvm-svn: 285849
* [OpenCL] Override supported OpenCL extensions with -cl-ext optionAlexey Bader2016-11-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds a command line option '-cl-ext' to control a set of supported OpenCL extensions. Option accepts a comma-separated list of extensions prefixed with '+' or '-'. It can be used together with a target triple to override support for some extensions: // spir target supports all extensions, but we want to disable fp64 clang -cc1 -triple spir-unknown-unknown -cl-ext=-cl_khr_fp64 Special 'all' extension allows to enable or disable all possible extensions: // only fp64 will be supported clang -cc1 -triple spir-unknown-unknown -cl-ext=-all,+cl_khr_fp64 Patch by asavonic (Andrew Savonichev). Reviewers: joey, yaxunl Subscribers: yaxunl, bader, Anastasia, cfe-commits Differential Revision: https://reviews.llvm.org/D23712 llvm-svn: 285700
* [x86][inline-asm][clang] accept 'v' constraintMichael Zuckerman2016-11-011-0/+2
| | | | | | | | | | | | | | Commit on behalf of: Coby Tayree 1.'v' constraint for (x86) non-avx arch imitates the already implemented 'x' constraint, i.e. allows XMM{0-15} & YMM{0-15} depending on the apparent arch & mode (32/64). 2.for the avx512 arch it allows [X,Y,Z]MM{0-31} (mode dependent) This patch applies the needed changes to clang LLVM patch: https://reviews.llvm.org/D25005 Differential Revision: https://reviews.llvm.org/D25005 llvm-svn: 285688
* [x86][inline-asm][AVX512][clang][PART-1] Introducing "k" and "Yk" ↵Michael Zuckerman2016-10-311-0/+20
| | | | | | | | | | | | | | | | constraints for extended inline assembly, enabling use of AVX512 masked vectorized instructions. Commit on behalf of mharoush Extending inline assembly support, compatible with GCC as folowing: "k" constraint hints the compiler to select any of AVX512 k0-k7 registers. "Yk" constraint is a subset of "k" excluding k0 which is not allowd to be used as a mask. Reviewer: 1. rnk Differential Revision: https://reviews.llvm.org/D25063 llvm-svn: 285604
* [SystemZ] Add -march=archX aliasesUlrich Weigand2016-10-311-2/+6
| | | | | | | | | | | | | | | For compatibility with other compilers on the platform, allow specifying levels of the z/Architecture instead of model names with -march. In particular, the following aliases are now supported: -march=arch8 equals -march=z10 -march=arch9 equals -march=z196 -march=arch10 equals -march=zEC12 -march=arch11 equals -march=z13 This parallels the equivalent (and prerequisite) LLVM change in r285577. llvm-svn: 285578
* second attempt at r285565.Michael Zuckerman2016-10-311-0/+1
| | | | llvm-svn: 285573
* revert r285563 fail in test CodeGen/avx512-inline-asm-kregisters-basics.cMichael Zuckerman2016-10-311-1/+0
| | | | llvm-svn: 285565
* [x86][inline-asm] Introducing (AVX512) k0-k7 registers for inline-asm usageMichael Zuckerman2016-10-311-0/+1
| | | | | | | | | | | | | | | Commit on behalf of mharoush After LGTM and check all: This patch enables usage of k registers in inline assembly syntax. Adding triple Reviewer: 1. rnk 2. delena Differential Revision: https://reviews.llvm.org/D25011 llvm-svn: 285563
* Revert reviosion 285555Michael Zuckerman2016-10-311-1/+0
| | | | llvm-svn: 285556
* [x86][inline-asm] Introducing (AVX512) k0-k7 registers for inline-asm usageMichael Zuckerman2016-10-311-0/+1
| | | | | | | | | | | | | | Commit on behalf of mharoush After LGTM and check all: This patch enables usage of k registers in inline assembly syntax. Reviewer: 1. rnk 2. delena Differential Revision: https://reviews.llvm.org/D25011 llvm-svn: 285555
* AMDGPU: Add missing ISA versions gfx7.x.x and 8.x.x.Yaxun Liu2016-10-261-0/+9
| | | | | | | | Patch by Laurent Morichetti. Differential Revision: https://reviews.llvm.org/D25920 llvm-svn: 285211
* [Basic] Support 32-bit x86 and ARM targets for FuchsiaPetr Hosek2016-10-241-4/+12
| | | | | | | | | Fuchsia has experimental support for 32-bit x86 and ARM targets, add them to the list of supported targets. Differential Revision: https://reviews.llvm.org/D25838 llvm-svn: 285038
* Implement MS _BitScan intrinsicsAlbert Gutowski2016-10-121-0/+2
| | | | | | | | | | | | Summary: _BitScan intrinsics (and some others, for example _Interlocked and _bittest) are supposed to work on both ARM and x86. This is an attempt to isolate them, avoiding repeating their code or writing separate function for each builtin. Reviewers: hans, thakis, rnk, majnemer Subscribers: RKSimon, cfe-commits, aemerson Differential Revision: https://reviews.llvm.org/D25264 llvm-svn: 284060
* Declare WinX86_64ABIInfo to satisfy SwiftABI infoArnold Schwaighofer2016-10-121-0/+1
| | | | | | | | | This is minimal support that allows swift's test cases on non windows platforms to pass. rdar://28738985 llvm-svn: 284032
* Move x86-64 builtins from SemaChecking.cpp to BuiltinsX86_64.defAlbert Gutowski2016-10-121-0/+2
| | | | | | | | | | | | Summary: Follow-up to https://reviews.llvm.org/D24598 (separating builtins for x84-64 and i386). Reviewers: hans, thakis, rnk Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D25494 llvm-svn: 284026
* Revert "[x86][inline-asm][clang] accept 'v' constraint"Daniel Jasper2016-10-101-2/+0
| | | | | | | | | This reverts commit r283716. Breaks buildbot: http://lab.llvm.org:8080/green/job/clang-stage2-configure-Rlto_check/9155/testReport/junit/Clang/CodeGen/x86_inline_asm_v_constraint_c/ llvm-svn: 283743
* [x86][inline-asm][clang] accept 'v' constraintMichael Zuckerman2016-10-101-0/+2
| | | | | | | | | | | | | | Commit in the name of: Coby Tayree 1.'v' constraint for (x86) non-avx arch imitates the already implemented 'x' constraint, i.e. allows XMM{0-15} & YMM{0-15} depending on the apparent arch & mode (32/64). 2.for the avx512 arch it allows [X,Y,Z]MM{0-31} (mode dependent) This patch applies the needed changes to clang LLVM patch: https://reviews.llvm.org/D25005 Differential Revision: D25004 llvm-svn: 283716
* [ARM]: Add Cortex-R52 targetJaved Absar2016-10-071-0/+2
| | | | | | | This patch adds Cortex-R52, the new ARM real-time processor. Cortex-R52 implements the ARMv8-R architecture. llvm-svn: 283543
* Use StringReg in TargetParser APIs (NFC)Mehdi Amini2016-10-071-3/+3
| | | | llvm-svn: 283527
* [Driver] Add driver support for FuchsiaPetr Hosek2016-10-061-0/+26
| | | | | | | | | | | Provide toolchain and tool support for Fuchsia operating system. Fuchsia uses compiler-rt as the runtime library and libc++, libc++abi and libunwind as the C++ standard library. lld is used as a default linker. Differential Revision: https://reviews.llvm.org/D25117 llvm-svn: 283420
* Separate builtins for x84-64 and i386; implement __mulh and __umulhAlbert Gutowski2016-10-041-8/+16
| | | | | | | | | | | | Summary: We need x86-64-specific builtins if we want to implement some of the MS intrinsics - winnt.h contains definitions of some functions for i386, but not for x86-64 (for example _InterlockedOr64), which means that we cannot treat them as builtins for both i386 and x86-64, because then we have definitions of builtin functions in winnt.h on i386. Reviewers: thakis, majnemer, hans, rnk Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D24598 llvm-svn: 283264
* P0035R4: add predefined __STDCPP_DEFAULT_NEW_ALIGNMENT__ macro. By default, weRichard Smith2016-09-301-0/+1
| | | | | | | | | assume that ::operator new provides no more alignment than is necessary for any primitive type, except when we're on a GNU OS, where glibc's malloc guarantees to provide 64-bit alignment on 32-bit systems and 128-bit alignment on 64-bit systems. This can be controlled by the command-line -fnew-alignment flag. llvm-svn: 282974
* [CUDA] added __nvvm_atom_{sys|cta}_* builtins.Artem Belevich2016-09-281-1/+14
| | | | | | | | These builtins are available on sm_60+ GPU only. Differential Revision: https://reviews.llvm.org/D24944 llvm-svn: 282609
* [Power9] Builtins for ELF v.2 ABI conformance - front end portionNemanja Ivanovic2016-09-271-9/+29
| | | | | | | | | | This patch corresponds to review: https://reviews.llvm.org/D24397 It adds the __POWER9_VECTOR__ macro and the -mpower9-vector option along with a number of altivec.h functions (refer to the code review for a list). llvm-svn: 282481
* [OpenBSD] Add type sign information for OpenBSDRenato Golin2016-09-221-1/+5
| | | | | | | | | | | | | | Like NetBSD, OpenBSD prefers having a consistent set of typedefs across the architectures it supports over strictly following the ARM ABIs. The diff below makes sure that clang's view of those types matches OpenBSD's system header files. It also adds a test that checks the relevant types on all OpenBSD platforms that clang works on. Hopefully we can add mips64 and powerpc to that list in the future. Patch by Mark Kettenis <mark.kettenis@xs4all.nl> llvm-svn: 282184
* Add some MS aliases for existing intrinsicsAlbert Gutowski2016-09-141-0/+2
| | | | | | | | | | Reviewers: thakis, compnerd, majnemer, rsmith, rnk Subscribers: alexshap, cfe-commits Differential Revision: https://reviews.llvm.org/D24330 llvm-svn: 281540
* Reverse commit 281375 (breaks building Chromium)Albert Gutowski2016-09-131-2/+0
| | | | llvm-svn: 281399
* Add some MS aliases for existing intrinsicsAlbert Gutowski2016-09-131-0/+2
| | | | | | | | | | Reviewers: thakis, compnerd, majnemer, rsmith, rnk Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D24330 llvm-svn: 281375
* AMDGPU: Fix target options fp32/64-denormalsYaxun Liu2016-09-131-10/+6
| | | | | | | | | | | | | | Fix target options for fp32/64-denormals so that +fp64-denormals is set if fp64 is supported -fp32-denormals if fp32 denormals is not supported, or -cl-denorms-are-zero is set +fp32-denormals if fp32 denormals is supported and -cl-denorms-are-zero is not set If target feature fp32/64-denormals is explicitly set, they will override default options and options deduced from -cl-denorms-are-zero. Differential Revision: https://reviews.llvm.org/D24512 llvm-svn: 281357
* [CUDA] Make __GCC_ATOMIC_XXX_LOCK_FREE macros the same on host/device.Justin Lebar2016-09-091-0/+6
| | | | | | | | | | | | | | | | | | | | | Summary: This fixes a bug where we were unable to compile the following CUDA file with libstdc++ (didn't try libc++): #include <future> void foo() { std::shared_future<int> x; } The problem is that <future> only defines std::shared_future if __GCC_ATOMIC_INT_LOCK_FREE > 1. When we compiled this file for device, the macro was set to 1, and then the class didn't exist at all. Reviewers: tra Subscribers: cfe-commits, jhen Differential Revision: https://reviews.llvm.org/D24407 llvm-svn: 281089
* OpenCL: Defining __ENDIAN_LITTLE__ and fix target endiannessMatt Arsenault2016-09-071-21/+3
| | | | | | | | | OpenCL requires __ENDIAN_LITTLE__ be set for little endian targets. The default for targets was also apparently big endian, so AMDGPU was incorrectly reported as big endian. Set this from the triple so targets don't have another place to set the endianness. llvm-svn: 280787
* Add support for targeting armv6-unknown-cloudabi-eabihf.Ed Schouten2016-09-051-0/+2
| | | | | | | I'm in the progress of adding ARMv6 support to CloudABI. On the compiler side, everything seems to work properly with this tiny change applied. llvm-svn: 280672
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