| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 117900
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represents InstAliases as well. Rename
isAssemblerInstruction -> Validate since that is what
it does (modulo the ARM $lane hack).
llvm-svn: 117899
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instructions and InstAliases. Start creating InstructionInfo's
for Aliases.
llvm-svn: 117898
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in their asmstring. Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.
llvm-svn: 117897
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variables to the list of found variables if they
have not yet been added.
llvm-svn: 117896
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member, and make isAssemblerInstruction() a method (pushing some code
around inside it).
llvm-svn: 117895
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todo: the result field.
llvm-svn: 117894
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CodeGenInstruction into its own helper class. No functionality change.
llvm-svn: 117893
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llvm-svn: 117892
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simplify CodeGenInstruction. No functionality change.
llvm-svn: 117891
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llvm-svn: 117890
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instead of strings, simplifying it.
llvm-svn: 117889
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argument passing. Consolidate all SingletonRegister detection
and handling into a new
InstructionInfo::getSingletonRegisterForToken method instead of
having it scattered about. No change in generated .inc files.
llvm-svn: 117888
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isInlined() just gives meaningless results for non-definitions.
Fixes rdar://problem/8614470
llvm-svn: 117887
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CodeGenInstruction::FlattenAsmStringVariants method. Use it
to simplify the code in AsmWriterInst, which now no longer
needs to worry about variants.
llvm-svn: 117886
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this can start rejecting instructions.
llvm-svn: 117885
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various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.
llvm-svn: 117884
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llvm-svn: 117883
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getVBaseClassOffset instead.
llvm-svn: 117882
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getBaseClassOffset which returns the offset in CharUnits. Do the same thing for getVBaseClassOffset.
llvm-svn: 117881
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specializations provided here. This is a little annoying because its size
changes from platform to platform. If possible, I may follow up with a patch
that uses standard constants to simplify much of this, but assuming for now
that was avoided for a reason.
llvm-svn: 117880
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llvm-svn: 117879
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llvm-svn: 117878
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llvm-svn: 117877
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looks like is happening:
Without the peephole optimizer:
(1) sub r6, r6, #32
orr r12, r12, lr, lsl r9
orr r2, r2, r3, lsl r10
(x) cmp r6, #0
ldr r9, LCPI2_10
ldr r10, LCPI2_11
(2) sub r8, r8, #32
(a) movge r12, lr, lsr r6
(y) cmp r8, #0
LPC2_10:
ldr lr, [pc, r10]
(b) movge r2, r3, lsr r8
With the peephole optimizer:
ldr r9, LCPI2_10
ldr r10, LCPI2_11
(1*) subs r6, r6, #32
(2*) subs r8, r8, #32
(a*) movge r12, lr, lsr r6
(b*) movge r2, r3, lsr r8
(1) is used by (x) for the conditional move at (a). (2) is used by (y) for the
conditional move at (b). After the peephole optimizer, these the flags resulting
from (1*) are ignored and only the flags from (2*) are considered for both
conditional moves.
llvm-svn: 117876
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llvm-svn: 117875
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llvm-svn: 117874
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llvm-svn: 117873
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llvm-svn: 117872
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llvm-svn: 117871
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llvm-svn: 117870
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ASTRecordLayout. Start by storing the offsets in CharUnits in the ASTRecordLayout object.
llvm-svn: 117869
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virtual bases are involved. Fixes PR5974.
llvm-svn: 117868
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llvm-svn: 117867
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/usr/local/bin.
llvm-svn: 117866
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llvm-svn: 117865
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llvm-svn: 117864
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let Constraints = "$val = $dst", Defs = [EFLAGS] in, isCodeGenOnly = 1 {
we now get:
X86InstrCompiler.td:653:52: error: Expected class, def, defm, multiclass or let definition
let Constraints = "$val = $dst", Defs = [EFLAGS] in, isCodeGenOnly = 1 {
^
llvm-svn: 117863
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Use this to make the X86 and ARM targets set isCodeGenOnly=1
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.
llvm-svn: 117862
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and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.
llvm-svn: 117861
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got a dulicated line).
llvm-svn: 117860
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llvm-svn: 117859
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Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the
instruction 'isCodeGenOnly'.
Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are
doing this.
llvm-svn: 117858
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how the push/pop mnemonic aliases are wrong.
llvm-svn: 117857
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calling convention out of the fast and normal ISel files, and
into the calling convention TD file.
llvm-svn: 117856
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which has the same logic specified in the CallingConv TD file.
This brings FastISel in line with the standard X86 ISel.
llvm-svn: 117855
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llvm-svn: 117854
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Clang PR 8426, 8427, & 8433. Reviewed by Ted Kremenek and Doug Gregor.
llvm-svn: 117853
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llvm-svn: 117852
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keep the file size a bit smaller.
Exposed SBValue::GetExpressionPath() so SBValue users can get an expression
path for their values.
llvm-svn: 117851
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