| Commit message (Collapse) | Author | Age | Files | Lines |
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module file when we've merely added a definition
llvm-svn: 147414
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longer needed now that we aren't back-patching ObjCProtocolDecls.
llvm-svn: 147413
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forward declarations and definitions of an Objective-C protocol are
represented within a single chain of ObjCProtocolDecls.
llvm-svn: 147412
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llvm-svn: 147411
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for Objective-C protocols, including:
- Using the first declaration as the canonical declaration
- Using the definition as the primary DeclContext
- Making sure that all declarations have a pointer to the definition
data, and that we know which declaration is the definition
- Serialization support for redeclaration chains and for adding
definitions to already-serialized declarations.
However, note that we're not taking advantage of much of this code
yet, because we're still re-using ObjCProtocolDecls.
llvm-svn: 147410
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is enabled. Fix monitor and mwait to require SSE3 or AVX, previously they worked even if SSE3 was disabled. Make prefetch instructions not set the execution domain since they don't use XMM registers.
llvm-svn: 147409
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separately-allocated DefinitionData structure. Introduce various
functions that will help with the separation of declarations from
definitions (isThisDeclarationADefinition(), hasDefinition(),
getDefinition()).
llvm-svn: 147408
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llvm-svn: 147407
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getCanonicalDecl() when putting ObjCProtocolDecls into a set. This is
groundwork for making ObjCProtocolDecl redeclarable.
llvm-svn: 147406
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take precedence over command line options. Fixes PR10113.
llvm-svn: 147405
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llvm-svn: 147404
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it to simplify a few matchers.
llvm-svn: 147403
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llvm-svn: 147402
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llvm-svn: 147401
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llvm-svn: 147400
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The failure seen on win32, when i64 type is illegal.
It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR.
The failure message is:
llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed.
I added a special test that checks vector shuffle on win32.
llvm-svn: 147399
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llvm-svn: 147395
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llvm-svn: 147394
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llvm-svn: 147393
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a load from being selected.
llvm-svn: 147392
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'and' that would zero out the trailing bits, and to produce an exact shift
ourselves.
llvm-svn: 147391
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See PR11652. Trying to add this assert to
setSubclassData() itself actually prevented
the miscompile entirely, so it has to be here.
This makes the source of the bug more obvious
than the other asserts triggering later on did.
llvm-svn: 147390
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llvm-svn: 147388
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features needed for a particular module to be available. This allows
mixed-language modules, where certain headers only work under some
language variants (e.g., in C++, std.tuple might only be available in
C++11 mode).
llvm-svn: 147387
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mark it as XFAIL: mingw32.
Mingw32 target has not supported integrated-as yet.
llvm-svn: 147386
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llvm-svn: 147385
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Also temporarily remove the assumption from IR gen that we can emit IR for every
constant we can fold, since it isn't currently true in C++11, to fix PR11676.
Original comment from r147271:
constexpr: perform zero-initialization prior to / instead of performing a
constructor call when appropriate. Thanks to Eli for spotting this.
llvm-svn: 147384
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llvm-svn: 147383
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Implement encoder methods getJumpTargetOpValue and getBranchTargetOpValue
for jmptarget and brtarget Mips tablegen operand types in the code emitter
for old-style JIT. Rename the pc relative relocation for branches - new
name is Mips::reloc_mips_pc16.
Patch by Sasa Stankovic
llvm-svn: 147382
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llvm-svn: 147379
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python bindinds.
patch by Tom Schuster!
llvm-svn: 147378
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llvm-svn: 147373
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llvm-svn: 147372
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flag was used.
llvm-svn: 147371
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imply sse3. Matches gcc behavior.
llvm-svn: 147370
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removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal.
llvm-svn: 147369
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llvm-svn: 147368
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llvm-svn: 147367
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of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation.
llvm-svn: 147366
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llvm-svn: 147365
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llvm-svn: 147364
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llvm-svn: 147363
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llvm-svn: 147362
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force alignment on these instructions. Add a couple testcases for memory forms.
llvm-svn: 147361
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size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere.
llvm-svn: 147360
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1. The ST*UX instructions that store and update the stack pointer did not set define/kill on R1. This became a problem when I activated post-RA scheduling (and had incorrectly adjusted the Frames-large test).
2. eliminateFrameIndex did not kill its scavenged temporary register, and this could cause the scavenger to exhaust all available registers (and its emergency spill slot) when there were a lot of CR values to spill. The 2010-02-12-saveCR test has been adjusted to check for this.
llvm-svn: 147359
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Watch for empty symbol tables by doing a lot more error checking on
all mach-o symbol table load command values and data that is obtained.
This avoids a crash that was happening when there was no string table.
llvm-svn: 147358
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'is an extension'. The former is inappropriate and confusing when building with
-Werror/-pedantic-errors.
llvm-svn: 147357
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llvm-svn: 147356
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llvm-svn: 147355
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