| Commit message (Collapse) | Author | Age | Files | Lines |
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Right now it just checks that qSupported returns at least
one recognized gdb stub feature.
llvm-svn: 210573
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!if([Something], []) would error with "No type for list".
llvm-svn: 210572
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llvm-svn: 210571
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llvm-svn: 210570
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llvm-svn: 210569
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llvm-svn: 210568
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llvm-svn: 210567
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llvm-svn: 210566
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doing Objective-C subscript access. // rdar://16842487
PR19682.
llvm-svn: 210565
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llvm-svn: 210564
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llvm-svn: 210563
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return void in C++11
llvm-svn: 210562
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of refacoring in algorithm as well. Give them better names while we're at it. All of these are internal rotines; no visible functionality change.
llvm-svn: 210561
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bits out on c++03, since it doesn't support u"" and U "" style strings.
llvm-svn: 210560
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llvm-svn: 210559
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llvm-svn: 210558
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llvm-svn: 210557
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Add more instruction-specific statistics about failing intrinsic calls during
FastISel.
llvm-svn: 210556
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of the DataLayout.
llvm-svn: 210555
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than a TargetMachine.
llvm-svn: 210554
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llvm-svn: 210553
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llvm-svn: 210552
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llvm-svn: 210551
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We would previously end up with an error when instantiating the
following template:
template <typename> struct __declspec(dllimport) S {
void foo() = delete;
};
S<int> s;
error: attribute 'dllimport' cannot be applied to a deleted function
llvm-svn: 210550
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llvm-svn: 210549
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AArch64FrameLowering.
llvm-svn: 210548
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'super' dispatches a class method in category for OBJC_METACLASS.
This is when class is a weak_import class.
// rdar://16529125
llvm-svn: 210547
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Summary:
Implement materialize of floating point literals in Mips Fast-Isel
Reopened version of D3659
Test Plan: simplestorefp1.ll
Reviewers: dsanders
Reviewed By: dsanders
Differential Revision: http://reviews.llvm.org/D4071
llvm-svn: 210546
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This patch slightly changes the algorithm introduced at revision 210477
to fix a problem where the algorithm was producing incorrect code for
the VEX.256 encoded versions of horizontal add/sub.
For these cases, we now try to split the two 256-bit vectors into
128-bit chunks before emitting horizontal add/sub dag nodes.
Added a new test case into haddsub-2.ll.
llvm-svn: 210545
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il is legal for Hexagon, so I should have marked this as Expand for
SELECT_CC when I removed setOperationAction(ISD::SELECT_CC, MVT::Other,
Expand); in r210541.
llvm-svn: 210544
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Along with the corresponding intrinsic and tests.
llvm-svn: 210543
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Previously, the basic block was searched for future uses of the base register,
and if necessary any writeback to the base register was reset using a SUB
instruction (e.g. before calling a function) just before such a use. However,
this step happened *before* the merged LDM/STM instruction was built. So if
there was (e.g.) a function call directly after the not-yet-formed LDM/STM,
the pass would first insert a SUB instruction to reset the base register,
and then (at the same location, incorrectly) insert the LDM/STM itself.
This patch fixes PR19972. Patch by Moritz Roth.
llvm-svn: 210542
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The SelectionDAG bad a special case for ISD::SELECT_CC, where it would
allow targets to specify:
setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
to indicate that they wanted to expand ISD::SELECT_CC for all types.
This wasn't applied correctly everywhere, and it makes writing new
DAG patterns with ISD::SELECT_CC difficult.
llvm-svn: 210541
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vectors
This prevents a future commit from regressing:
test/CodeGen/R600/setcc-equivalent.ll
llvm-svn: 210540
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This consolidates code from the Hexagon, R600, and XCore targets.
No functionality change intended.
llvm-svn: 210539
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llvm-svn: 210538
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Before:
return {
link:
function() {
f(); //
}
};
return {
a: a,
link: function() {
f(); //
}
}
After:
return {
link: function() {
f(); //
}
};
return {
a: a,
link: function() {
f(); //
}
};
llvm-svn: 210537
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Various masks on shufflevector instructions are recognizable as
specific PowerPC instructions (vector pack, vector merge, etc.).
There is existing code in PPCISelLowering.cpp to recognize the correct
patterns for big endian code. The masks for these instructions are
different for little endian code due to the big-endian numbering
employed by these instructions. This patch adds the recognition code
for little endian.
I've added a new test case test/CodeGen/PowerPC/vec_shuffle_le.ll for
this. The existing recognizer test (vec_shuffle.ll) is unnecessarily
verbose and difficult to read, so I felt it was better to add a new
test rather than modify the old one.
llvm-svn: 210536
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Patch by Ana Pazos<apazos@codeaurora.org>!
llvm-svn: 210535
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Clang's lit cfg already detects the currently selected SDK via
"xcrun --show-sdk-path". The same thing should be done for compiler-rt tests,
to make them work on recent OS X versions. Instead of duplicating the detection
code, this patch extracts the detection function into a lit.util method.
Patch by Kuba Brecka (kuba.brecka@gmail.com),
reviewed at http://reviews.llvm.org/D4072
llvm-svn: 210534
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Standard KVM ioctls don't pass currect ioctl_decode().
llvm-svn: 210533
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No functional changes.
llvm-svn: 210532
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No functional changes.
llvm-svn: 210531
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is around non-archive.
llvm-svn: 210530
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Before:
aaaaaaaaaaa aaaaaaaaaaaaaaa = aaaaaaaaaaaaaaaaaaaaaaaaaa->aaaaaaaaa[0].aaaaaaa
[0].aaaaaaaaaaaaaaaaaaaaaa();
After:
aaaaaaaaaaa aaaaaaaaaaaaaaa = aaaaaaaaaaaaaaaaaaaaaaaaaa->aaaaaaaaa[0]
.aaaaaaa[0]
.aaaaaaaaaaaaaaaaaaaaaa();
llvm-svn: 210529
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inverted condition codes (CINC, CINV, CNEG, CSET, and CSETM).
Matching aliases based on "immediate classes", when disassembling,
wasn't previously supported, hence adding MCOperandPredicate
into class Operand, and implementing the support for it
in AsmWriterEmitter.
The parsing for those aliases was already custom, so just adding
the missing condition into AArch64AsmParser::parseCondCode.
llvm-svn: 210528
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llvm-svn: 210527
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llvm-svn: 210526
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As Ana Pazos pointed out, these have to be restored to their incoming values
before a function returns; i.e. before the tail call. So they can't be used
correctly as the destination register.
llvm-svn: 210525
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This reverts commit r210523. It was committed prematurely without waiting for
review.
llvm-svn: 210524
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