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* [clang-tidy] Rewrite a for-range loop in the old style.Benjamin Kramer2014-08-041-3/+3
| | | | | | | | Haven't thought that I ever needed to do this, but in this case comparing the index using pointer arithmetic turns out to be really ugly. It also generates nasty sign-compare warnings on 32 bit targets. llvm-svn: 214705
* [asan] intercept sized operator delete[]Kostya Serebryany2014-08-042-14/+47
| | | | llvm-svn: 214704
* [clang-tidy] Fix unnamed parameter comment insertion with multiple parameters.Benjamin Kramer2014-08-042-4/+11
| | | | llvm-svn: 214703
* [x86] Implement more aggressive use of PACKUS chains for lowering commonChandler Carruth2014-08-042-14/+111
| | | | | | | | | | | | | | patterns of v16i8 shuffles. This implements one of the more important FIXMEs for the SSE2 support in the new shuffle lowering. We now generate the optimal shuffle sequence for truncate-derived shuffles which show up essentially everywhere. Unfortunately, this exposes a weakness in other parts of the shuffle logic -- we can no longer form PSHUFB here. I'll add the necessary support for that and other things in a subsequent commit. llvm-svn: 214702
* [clang-tidy] Make the named parameter check only warn on declarations if a ↵Benjamin Kramer2014-08-042-32/+56
| | | | | | | | | | | | | | | | definition is visible. Summary: This allows us to copy the parameter name from the definition (as a comment) or insert /*unused*/ in both places. Reviewers: alexfh, klimek Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D4772 llvm-svn: 214701
* Update links to the gcc and java documentation that 404'd.Benjamin Kramer2014-08-041-2/+2
| | | | llvm-svn: 214700
* AST: Fix the mangling for unqualified-blocksDavid Majnemer2014-08-042-9/+8
| | | | | | | | | | | | | | | | CXXNameMangler::mangleUnqualifiedBlock believed that MangleContext::getBlockId returned something that used Itanium-style discriminator numbers. Discriminator numbers start their numberign from 1 and the first mangling that actually gets any sort of number mangled in is the second discriminator. However, Block IDs start from zero. The logic for omitting the mangling number did a ' > 1' instead of a ' > 0' comparison; this could potentially cause mangling conflicts. llvm-svn: 214699
* AST: Propagate 'AlignIsRequired' though many levels of typedefsDavid Majnemer2014-08-042-1/+32
| | | | | | | A typedef of a typedef should have AlignIsRequired if *either* typedef has an AlignAttr attached to it. llvm-svn: 214698
* Revert "r214669 - MachineCombiner Pass for selecting faster instruction"Kevin Qin2014-08-049-567/+26
| | | | | | This commit broke "make check" for several hours, so get it reverted. llvm-svn: 214697
* MemoryBuffer: Don't use mmap when FileSize is multiple of 4k on Cygwin.NAKAMURA Takumi2014-08-041-0/+8
| | | | | | | | | | | On Cygwin, getpagesize() returns 64k(AllocationGranularity). In r214580, the size of X86GenInstrInfo.inc became 1499136. FIXME: We should reorganize again getPageSize() on Win32. MapFile allocates address along AllocationGranularity but view is mapped by physical page. llvm-svn: 214681
* [x86] Handle single input shuffles in the SSSE3 case more intelligently.Chandler Carruth2014-08-042-4/+4
| | | | | | | | | | I spent some time looking into a better or more principled way to handle this. For example, by detecting arbitrary "unneeded" ORs... But really, there wasn't any point. We just shouldn't build blatantly wrong code so late in the pipeline rather than adding more stages and logic later on to fix it. Avoiding this is just too simple. llvm-svn: 214680
* [x86] Fix the test case added in r214670 and tweaked in r214674 further.Chandler Carruth2014-08-041-13/+11
| | | | | | | | | | | | | Fundamentally, there isn't a really portable way to test the constant pool contents. Instead, pin this test to the bare-metal triple. This also makes it a 64-bit triple which allows us to only match a single constant pool rather than two. It can also just hard code the '.' prefix as the format should be stable now that it has a fixed triple. Finally, I've switched it to use CHECK-NEXT to be more precise in the instruction sequence expected and to use variables rather than hard coding decisions by the register allocator. llvm-svn: 214679
* PR11778: Fix the rejects-valid half of this bug. We still produce the sameRichard Smith2014-08-042-64/+57
| | | | | | | poorly-worded warning for a case value that is not a possible value of the switched-on expression. llvm-svn: 214678
* [OCaml] Add Llvm.{string_of_const,const_element}.Peter Zotov2014-08-034-2/+40
| | | | llvm-svn: 214677
* [LLVM-C] Add LLVM{IsConstantString,GetAsString,GetElementAsConstant}.Peter Zotov2014-08-032-0/+37
| | | | llvm-svn: 214676
* Don't destroy MacroInfos if we find the macro definition is invalid; it'll getRichard Smith2014-08-033-17/+2
| | | | | | destroyed on shutdown regardless. Fixes a double-delete. llvm-svn: 214675
* Account for possible leading '.' in label string.Sanjay Patel2014-08-031-2/+2
| | | | llvm-svn: 214674
* [x86] Don't add nodes to the combined set (and prune subsequentChandler Carruth2014-08-031-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | combines) until they are legal. Doing it the old way could, when the stars align *just* right, cause a node to get into the combine set prior to being legalized. Then, when the same node showed up as an operand to another node later on (but not so much later on that it had been deleted as dead) we would fail to add it back to the worklist thinking it had already been combined. This would in turn cause it to not be legalized. Fortunately, we can also walk the operands looking for uncombined (and thus potentially un-legalized) nodes late. It will still ensure that we walk all operands of all nodes and send all of them through both the legalizer without changes and the combiner at least once. (Which was the original goal of this). I have a test case for this bug, but it is terribly brittle. For example, it will stop finding the bug the moment I enable the new shuffle lowering. I don't yet have any test case that reliably exercises this bug, and it isn't clear that it will be possible to craft one. It is entirely possible that with the new shuffle lowering the two forms of doing this are precisely equivalent. That doesn't mean we shouldn't take the more conservative approach of insisting on things in the combined set having survived the legalizer. llvm-svn: 214673
* X86: silence warning (-Wparentheses)Saleem Abdulrasool2014-08-031-1/+1
| | | | | | | | | GCC 4.8.2 points out the ambiguity in evaluation of the assertion condition: lib/Target/X86/X86FloatingPoint.cpp:949:49: warning: suggest parentheses around ‘&&’ within ‘||’ [-Wparentheses] assert(STReturns == 0 || isMask_32(STReturns) && N <= 2); llvm-svn: 214672
* CodeGen: silence a warningSaleem Abdulrasool2014-08-031-2/+1
| | | | | | | | GCC 4.8.2 objects to the tautological condition in the assert as the unsigned value is guaranteed to be >= 0. Simplify the assertion by dropping the tautological condition. llvm-svn: 214671
* fix for PR20354 - Miscompile of fabs due to vectorizationSanjay Patel2014-08-032-6/+32
| | | | | | | | | | This is intended to be the minimal change needed to fix PR20354 ( http://llvm.org/bugs/show_bug.cgi?id=20354 ). The check for a vector operation was wrong; we need to check that the fabs itself is not a vector operation. This patch will not generate the optimal code. A constant pool load and 'and' op will be generated instead of just returning a value that we can calculate in advance (as we do for the scalar case). I've put a 'TODO' comment for that here and expect to have that patch ready soon. There is a very similar optimization that we can do in visitFNEG, so I've put another 'TODO' there and expect to have another patch for that too. llvm-svn: 214670
* MachineCombiner Pass for selecting faster instructionGerolf Hoflehner2014-08-039-26/+567
| | | | | | | | | | | | | | | | | | | | | | sequence - AArch64 target support This patch turns off madd/msub generation in the DAGCombiner and generates them in the MachineCombiner instead. It replaces the original code sequence with the combined sequence when it is beneficial to do so. When there is no machine model support it always generates the madd/msub instruction. This is true also when the objective is to optimize for code size: when the combined sequence is shorter is always chosen and does not get evaluated. When there is a machine model the combined instruction sequence is evaluated for critical path and resource length using machine trace metrics and the original code sequence is replaced when it is determined to be faster. rdar://16319955 llvm-svn: 214669
* Driver: Simplify a use of the path APIJustin Bogner2014-08-031-1/+1
| | | | | | | It's a bit more obvious what's going on if we use path::filename rather than decrementing an iterator here. llvm-svn: 214668
* Change ProcessGDBRemote::DidLaunchOrAttach to Jason Molenda2014-08-031-2/+2
| | | | | | | | call Target::SetArchitecture instead of modifying a reference to the target's architecture so that the target logging can show that the arch has been changed. llvm-svn: 214667
* MachineCombiner Pass for selecting faster instructionGerolf Hoflehner2014-08-0311-16/+586
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sequence - target independent framework When the DAGcombiner selects instruction sequences it could increase the critical path or resource len. For example, on arm64 there are multiply-accumulate instructions (madd, msub). If e.g. the equivalent multiply-add sequence is not on the crictial path it makes sense to select it instead of the combined, single accumulate instruction (madd/msub). The reason is that the conversion from add+mul to the madd could lengthen the critical path by the latency of the multiply. But the DAGCombiner would always combine and select the madd/msub instruction. This patch uses machine trace metrics to estimate critical path length and resource length of an original instruction sequence vs a combined instruction sequence and picks the faster code based on its estimates. This patch only commits the target independent framework that evaluates and selects code sequences. The machine instruction combiner is turned off for all targets and expected to evolve over time by gradually handling DAGCombiner pattern in the target specific code. This framework lays the groundwork for fixing rdar://16319955 llvm-svn: 214666
* Do allow negative offsets in the outermost array dimensionTobias Grosser2014-08-034-23/+18
| | | | | | | | | | There is no needed for neither 1-dimensional nor higher dimensional arrays to require positive offsets in the outermost array dimension. We originally introduced this assumption with the support for delinearizing multi-dimensional arrays. llvm-svn: 214665
* MC: virtualise EmitWindowsUnwindTablesSaleem Abdulrasool2014-08-033-5/+8
| | | | | | | | | This makes EmitWindowsUnwindTables a virtual function and lowers the implementation of the function to the X86WinCOFFStreamer. This method is a target specific operation. This enables making the behaviour target dependent by isolating it entirely to the target specific streamer. llvm-svn: 214664
* MC: rename Win64EHFrameInfo to WinEH::FrameInfoSaleem Abdulrasool2014-08-036-50/+78
| | | | | | | | | | | | | | The frame information stored in this structure is driven by the requirements for Windows NT unwinding rather than Windows 64 specifically. As a result, this type can be shared across multiple architectures (ARM, AXP, MIPS, PPC, SH). Rename this class in preparation for adding support for supporting unwinding information for Windows on ARM. Take the opportunity to constify the members as everything except the ChainedParent is read-only. This required some adjustment to the label handling. llvm-svn: 214663
* [Mips] Add the `mips64-linux-gnu` target to the test case to check `in128`Simon Atanasyan2014-08-031-0/+1
| | | | | | type handling. llvm-svn: 214662
* R600/SI: Fix extra whitespace in asm strMatt Arsenault2014-08-032-1/+16
| | | | | | | | | This slipped in in r214467, so something like V_MOV_B32_e32 v0, ... is now printed with 2 spaces between the instruction name and first operand. llvm-svn: 214660
* Fix the modifiable access creationJohannes Doerfert2014-08-038-199/+127
| | | | | | | | | | | | + Remove the class IslGenerator which duplicates the functionality of IslExprBuilder. + Use the IslExprBuilder to create code for memory access relations. + Also handle array types during access creation. + Enable scev codegen for one of the transformed memory access tests, thus access creation without canonical induction variables available. + Update one test case to the new output. llvm-svn: 214659
* Allow the IslExprBuilder to generate access operationsJohannes Doerfert2014-08-032-1/+35
| | | | llvm-svn: 214658
* Update the jscop tests and port them to isl codegen.Johannes Doerfert2014-08-0316-12/+12
| | | | | | | | The updated tests use a different context than the old ones did. Other than that only their path and the code generation we use changed. llvm-svn: 214657
* Tools.cpp: Avoid std::to_string() on -fbuild-session-timestamp to appease ↵NAKAMURA Takumi2014-08-031-3/+4
| | | | | | mingw32 builder. llvm-svn: 214656
* [SimplifyCFG] fix accessing deleted PHINodes in switch-to-table conversion.Manman Ren2014-08-022-1/+54
| | | | | | | | | When we have a covered lookup table, make sure we don't delete PHINodes that are cached in PHIs. rdar://17887153 llvm-svn: 214642
* [Mips] Replace assembler code by YAML to make the 'gotsym.test' testSimon Atanasyan2014-08-021-13/+24
| | | | | | target independent. llvm-svn: 214641
* tlbia supportJoerg Sonnenberger2014-08-024-0/+11
| | | | llvm-svn: 214640
* mfdcr / mtdcr supportJoerg Sonnenberger2014-08-023-0/+18
| | | | llvm-svn: 214639
* fix bug 20513 - Crash in SLP VectorizerErik Eckstein2014-08-022-10/+61
| | | | llvm-svn: 214638
* Update test to use a more modern AArch64 triple, as requested by Renato.James Molloy2014-08-021-1/+1
| | | | llvm-svn: 214637
* Don't use additional arguments for dss and friends to satisfy DSS_Form,Joerg Sonnenberger2014-08-024-63/+87
| | | | | | | | | when let can do the same thing. Keep the 64bit variants as codegen-only. While they have a different register class, the encoding is the same for 32bit and 64bit mode. Having both present would otherwise confuse the disassembler. llvm-svn: 214636
* vcfsx and dss instructions require immediates, variables are not valid.Joerg Sonnenberger2014-08-021-2/+2
| | | | llvm-svn: 214635
* [AArch64] Teach DAGCombiner that converting two consecutive loads into a ↵James Molloy2014-08-022-0/+23
| | | | | | | | vector load is not a good transform when paired loads are available. The combiner was creating Q-register loads and stores, which then had to be spilled because there are no callee-save Q registers! llvm-svn: 214634
* Mark a GPGPU test case as XFAILTobias Grosser2014-08-021-0/+2
| | | | | | | This area of code is currently not very much tested. It will hopefully be superseeded by Yabin's GSoC project. llvm-svn: 214633
* No need to run -mem2reg twiceTobias Grosser2014-08-021-1/+0
| | | | llvm-svn: 214632
* [x86] Remove the FIXME that was implemented in r214628. Managed toChandler Carruth2014-08-021-4/+0
| | | | | | forget to update the comment here... =/ llvm-svn: 214630
* [x86] Give this test a bare metal triple so it doesn't use the weirdChandler Carruth2014-08-021-1/+1
| | | | | | | Darwin x86 asm comment prefix designed to work around GAS on that platform. That makes the comment-matching of the test much more stable. llvm-svn: 214629
* [x86] Largely complete the use of PSHUFB in the new vector shuffleChandler Carruth2014-08-025-129/+340
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | lowering with a small addition to it and adding PSHUFB combining. There is one obvious place in the new vector shuffle lowering where we should form PSHUFBs directly: when without them we will unpack a vector of i8s across two different registers and do a potentially 4-way blend as i16s only to re-pack them into i8s afterward. This is the crazy expensive fallback path for i8 shuffles and we can just directly use pshufb here as it will always be cheaper (the unpack and pack are two instructions so even a single shuffle between them hits our three instruction limit for forming PSHUFB). However, this doesn't generate very good code in many cases, and it leaves a bunch of common patterns not using PSHUFB. So this patch also adds support for extracting a shuffle mask from PSHUFB in the X86 lowering code, and uses it to handle PSHUFBs in the recursive shuffle combining. This allows us to combine through them, combine multiple ones together, and generally produce sufficiently high quality code. Extracting the PSHUFB mask is annoyingly complex because it could be either pre-legalization or post-legalization. At least this doesn't have to deal with re-materialized constants. =] I've added decode routines to handle the different patterns that show up at this level and we dispatch through them as appropriate. The two primary test cases are updated. For the v16 test case there is still a lot of room for improvement. Since I was going through it systematically I left behind a bunch of FIXME lines that I'm hoping to turn into ALL lines by the end of this. llvm-svn: 214628
* [x86] Switch to using the variable we extracted this operand into.Chandler Carruth2014-08-021-1/+1
| | | | | | | Spotted this missed refactoring by inspection when reading code, and it doesn't changethe functionality at all. llvm-svn: 214627
* [x86] Fix a few typos in my comments spotted in passing.Chandler Carruth2014-08-021-3/+3
| | | | llvm-svn: 214626
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