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* [CodeGen] Move printing MO_MachineBasicBlock operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-081-4/+2
| | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. llvm-svn: 320141
* [CodeGen] Move printing MO_CImmediate operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-084-6/+32
| | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. llvm-svn: 320140
* [change-namespace] Fix crash when injected base-class name is used in friend ↵Eric Liu2017-12-082-0/+58
| | | | | | | | | | | | declarations. Reviewers: hokein Subscribers: klimek, cfe-commits Differential Revision: https://reviews.llvm.org/D41001 llvm-svn: 320139
* [cmake] Make setting of CMAKE_C(XX)_COMPILER flags overridable for cross-buildsPavel Labath2017-12-081-5/+9
| | | | | | | | | | | | | | | | | | | | | | | Summary: r319898 made it possible to override these variables via the CROSS_TOOLCHAIN_FLAGS setting, but this only worked if one explicitly specifies these variables there. If, instead, one uses CROSS_TOOLCHAIN_FLAGS to specify a toolchain file (as our internal builds do, to point cmake to a checked-in toolchain), the CMAKE_C(XX)_COMPILER flags would still win over the ones specified by the toolchain file. To fix is to make the mere presence of these flags overridable. I do this by putting them as a default value for the CROSS_TOOLCHAIN_FLAGS setting, so they can be overridden at cmake configuration time. Reviewers: hintonda, beanz Subscribers: bogner, llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D40947 llvm-svn: 320138
* [X86][Haswell]: Updating the scheduling information for the Haswell subtarget.Gadi Haber2017-12-0829-2683/+2796
| | | | | | | | | | | | | | Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
* [FuzzMutate] Correctly insert sinks and sources around invoke instructionsIgor Laevsky2017-12-082-1/+44
| | | | | | Differential Revision: https://reviews.llvm.org/D40840 llvm-svn: 320136
* In stdbool.h, define bool, false, true only in gnu++98Stephan Bergmann2017-12-082-6/+15
| | | | | | | | | | GCC has meanwhile corrected that with the similar <https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=216679> "C++11 explicitly forbids macros for bool, true and false." Differential Revision: https://reviews.llvm.org/D40167 llvm-svn: 320135
* [X86] Always consider inserting a vXi1 vector into the lsbs of a zero vector ↵Craig Topper2017-12-082-27/+104
| | | | | | | | | | | | to be legal during lowering. Add isel patterns to emit shifts. Previously we only allowed these through if the subvector came from a compare or test instruction which we would again check for during isel. With this change we only check for the compare and test instructions during isel and have fallback patterns that emit the shifts if needed. I noticed that in a lot of cases we don't actually see the compare during lowering and rely on an odd legalization of concat_vectors with a zero vector as the second argument. This keeps the concat_vectors around long enough for a later dag combine to expose the compare then we re-legalize the concat_vectors and catch the compare. llvm-svn: 320134
* Revert r320124 "Fold together the in-range and out-of-range portions of ↵Hans Wennborg2017-12-081-35/+98
| | | | | | | | | | | | | | | | | | | | -Wtautological-compare." This broke Chromium: ../../base/trace_event/trace_log.cc:1545:29: error: comparison of constant 64 with expression of type 'unsigned int' is always true [-Werror,-Wtautological-constant-out-of-range-compare] DCHECK(handle.event_index < TraceBufferChunk::kTraceBufferChunkSize); ~~~~~~~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The 'unsigned int' is really a 6-bit bitfield, which is why it's always less than 63. Did this use to fall under the "in-range" case before? I thought we didn't use to warn when comparing against the boundaries of a type. llvm-svn: 320133
* [Blocks] Inherit sanitizer options from parent declVedant Kumar2017-12-082-2/+5
| | | | | | | | | | | | There is no way to apply sanitizer suppressions to ObjC blocks. A reasonable default is to have blocks inherit their parent's sanitizer options. rdar://32769634 Differential Revision: https://reviews.llvm.org/D40668 llvm-svn: 320132
* Add a test that the __STDC_VERSION__ macro reports the correct value for ↵Aaron Ballman2017-12-081-0/+4
| | | | | | -std=c17. llvm-svn: 320131
* Use lambda to simplify code.Rui Ueyama2017-12-081-26/+25
| | | | | | Differential Revision: https://reviews.llvm.org/D40994 llvm-svn: 320130
* [ubsan] Test for pass_object_size bounds checksVedant Kumar2017-12-081-0/+16
| | | | llvm-svn: 320129
* [ubsan] Use pass_object_size info in bounds checksVedant Kumar2017-12-083-0/+128
| | | | | | | | | Teach UBSan's bounds check to opportunistically use pass_object_size information to check array accesses. rdar://33272922 llvm-svn: 320128
* [MachException] Avoid alignment UB, NFCVedant Kumar2017-12-082-4/+11
| | | | | | | | | | | Fix alignment UB in some Mach exception-handling logic. This lets us build lldb and debugserver with UBSan in trapping mode, and get further along in the testing process before a trap is encountered. rdar://35923991 llvm-svn: 320127
* Remove extant references to g_message_mutex, NFCVedant Kumar2017-12-082-17/+6
| | | | | | Thanks to Jim Ingham for providing the explanation! llvm-svn: 320126
* Prefer `ArrayRef` over `const std::vector&`Sam Clegg2017-12-0812-25/+25
| | | | | | Differential Revision: https://reviews.llvm.org/D40993 llvm-svn: 320125
* Fold together the in-range and out-of-range portions of -Wtautological-compare.Richard Smith2017-12-081-98/+35
| | | | llvm-svn: 320124
* [AArch64] Avoid SIMD interleaved store instruction for Exynos.Abderrazek Zaafrani2017-12-085-122/+597
| | | | | | | Replace interleaved store instructions by equivalent and more efficient instructions based on latency cost model. Https://reviews.llvm.org/D38196 llvm-svn: 320123
* Unify implementation of our two different flavours of -Wtautological-compare.Richard Smith2017-12-084-245/+295
| | | | | | | | In so doing, fix a handful of remaining bugs where we would report false positives or false negatives if we promote a signed value to an unsigned type for the comparison. llvm-svn: 320122
* Revert "[WebAssemby] Support main functions with alternate signatures."Derek Schuff2017-12-082-63/+1
| | | | | | | | | This reverts commit 959e37e669b0c3cfad4cb9f1f7c9261ce9f5e9ae. That commit doesn't handle the case where main is declared rather than defined, in particular the even-more special case where main is a prototypeless declaration (which is of course the one actually used by musl currently). llvm-svn: 320121
* [X86] Handle alls version of vXi1 insert_vector_elt with a constant index ↵Craig Topper2017-12-087-8092/+6462
| | | | | | | | | | | | without falling back to shuffles. We previously only supported inserting to the LSB or MSB where it was easy to zero to perform an OR to insert. This change effectively extracts the old value and the new value, xors them together and then xors that single bit with the correct location in the original vector. This will cancel out the old value in the first xor leaving the new value in the position. The way I've implemented this uses 3 shifts and two xors and uses an additional register. We can avoid the additional register at the cost of another shift. llvm-svn: 320120
* [X86] Fix indentation. NFCCraig Topper2017-12-081-2/+2
| | | | llvm-svn: 320119
* [WebAssembly] Add check to ensure symbol VA is only set once. NFC.Sam Clegg2017-12-082-12/+2
| | | | | | | | Also remove resulting unneeded function. Differential Revision: https://reviews.llvm.org/D40990 llvm-svn: 320118
* Fix a test that didn't actually test anything.Rui Ueyama2017-12-081-2/+2
| | | | llvm-svn: 320117
* [ORC] Mark SymbolStringPool methods as inline to avoid linkage errors, add aLang Hames2017-12-072-5/+13
| | | | | | less-than comparison to SymbolStringPtr and a corresponding unit test. llvm-svn: 320116
* Correct line endings that got mixed up in r320088; NFC.Aaron Ballman2017-12-071-12/+12
| | | | llvm-svn: 320115
* Fix more line endings changed in r320089. NFC.Ahmed Bougacha2017-12-071-1918/+1918
| | | | llvm-svn: 320114
* Correct line endings that got mixed up in r320089; NFC.Aaron Ballman2017-12-075-718/+718
| | | | llvm-svn: 320113
* Remove line-endings added by r320089. NFC.Ahmed Bougacha2017-12-071-185/+185
| | | | llvm-svn: 320112
* [dump] Make LLVM_ENABLE_DUMP independent, and move to llvm-config.hDon Hinton2017-12-073-8/+4
| | | | | | | | | Summary: Make LLVM_ENABLE_DUMP independent LLVM_ENABLE_ASSERTIONS, move it to llvm-config.h, and update description. Differential Revision: https://reviews.llvm.org/D38406 llvm-svn: 320111
* [PowerPC][asan] Update asan to handle changed memory layouts in newer kernelsBill Seurer2017-12-072-7/+14
| | | | | | | | | | | | | | | In more recent Linux kernels with 47 bit VMAs the layout of virtual memory for powerpc64 changed causing the address sanitizer to not work properly. This patch adds support for 47 bit VMA kernels for powerpc64 and fixes up test cases. https://reviews.llvm.org/D40908 There is an associated patch for trunk. Tested on several 4.x and 3.x kernel releases. llvm-svn: 320110
* [PowerPC][asan] Update asan to handle changed memory layouts in newer kernelsBill Seurer2017-12-072-2/+2
| | | | | | | | | | | | | | | In more recent Linux kernels with 47 bit VMAs the layout of virtual memory for powerpc64 changed causing the address sanitizer to not work properly. This patch adds support for 47 bit VMA kernels for powerpc64 and fixes up test cases. https://reviews.llvm.org/D40907 There is an associated patch for compiler-rt. Tested on several 4.x and 3.x kernel releases. llvm-svn: 320109
* [DebugInfo] Fix register variables not showing up in pdb.Zachary Turner2017-12-072-3/+15
| | | | | | | | | | | | | Previously, when linking against libcmt from the MSVC runtime, lld-link /verbose would show "Ignoring unknown symbol record with kind 0x1006". It turns out this was because TypeIndexDiscovery did not handle S_REGISTER records, so these records were not getting properly remapped. Patch by: Alexnadre Ganea Differential Revision: https://reviews.llvm.org/D40919 llvm-svn: 320108
* [ModRefInfo] Make enum ModRefInfo an enum class [NFC].Alina Sbirlea2017-12-0714-171/+183
| | | | | | | | | | | | | | | Summary: Make enum ModRefInfo an enum class. Changes to ModRefInfo values should be done using inline wrappers. This should prevent future bit-wise opearations from being added, which can be more error-prone. Reviewers: sanjoy, dberlin, hfinkel, george.burgess.iv Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40933 llvm-svn: 320107
* Temporarily revert "[PowerPC] Allow tail calls of fastcc functions from C ↵Eric Christopher2017-12-072-13/+8
| | | | | | | | | | CallingConv functions." It is causing sanitizer failures on llvm tests in a bootstrapped compiler. No bot link since it's currently down, but following up to get the bot up. This reverts commit r319218. llvm-svn: 320106
* Test case update for D40873Xinliang David Li2017-12-071-2/+2
| | | | llvm-svn: 320105
* [PGO] detect infinite loop and form MST properlyXinliang David Li2017-12-076-38/+56
| | | | | | Differential Revision: http://reviews.llvm.org/D40873 llvm-svn: 320104
* [Analysis] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-12-075-374/+442
| | | | | | other minor fixes (NFC). llvm-svn: 320091
* [MachineOutliner] Fix offset overflow checkJessica Paquette2017-12-072-4/+9
| | | | | | | | | | | | The offset overflow check before was incorrect. It would always give the correct result, but it was comparing the SCALED potential fixed-up offset against an UNSCALED minimum/maximum. As a result, the outliner was missing a bunch of frame setup/destroy instructions that ought to have been safe to outline. This fixes that, and adds an instruction to the .mir test that failed the old test. llvm-svn: 320090
* Add new language mode flags for C17.Aaron Ballman2017-12-077-876/+901
| | | | | | This adds -std=c17, -std=gnu17, and -std=iso9899:2017 as language mode flags for C17 and updates the value of __STDC_VERSION__ to the value based on the C17 FDIS. Given that this ballot cannot succeed until 2018, it is expected that we (and GCC) will add c18 flags as aliases once the ballot passes. llvm-svn: 320089
* Add support for the __has_c_attribute builtin preprocessor macro.Aaron Ballman2017-12-075-1913/+1965
| | | | | | This behaves similar to the __has_cpp_attribute builtin macro in that it allows users to detect whether an attribute is supported with the [[]] spelling syntax, which can be enabled in C with -fdouble-square-bracket-attributes. llvm-svn: 320088
* [AMDGPU] Fix typo in Kernel Descriptor for GFX6-GFX9Mark Searles2017-12-071-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D40981 llvm-svn: 320087
* [AMDGPU] Revert "[AMDGPU] Add options for waitcnt pass debugging; add instr ↵Mark Searles2017-12-072-103/+8
| | | | | | | | | | | | | | count in debug output." Patch caused a buildbot failure; http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/15733/steps/build_Lld/logs/stdio : lib/Target/AMDGPU/SIInsertWaitcnts.cpp:396:11: error: private field 'InstCnt' is not used [-Werror,-Wunused-private-field] int32_t InstCnt = 0; ^ 1 error generated. " This reverts commit 71627f79010aafe74fdcba901bba28dd7caa0869. llvm-svn: 320086
* [libclang] Record code-completion invocations to a temporary file whenAlex Lorenz2017-12-077-4/+52
| | | | | | | | | | | | | requested by client This is a follow up to r319702 which records parsing invocations. These files are not emitted by default, and the client has to specify the invocation emission path first. rdar://35322543 llvm-svn: 320085
* [AMDGPU] Add options for waitcnt pass debugging; add instr count in debug ↵Mark Searles2017-12-072-8/+103
| | | | | | | | | | | | | output. -amdgpu-waitcnt-forcezero={1|0} Force all waitcnt instrs to be emitted as s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -amdgpu-waitcnt-forceexp=<n> Force emit a s_waitcnt expcnt(0) before the first <n> instrs -amdgpu-waitcnt-forcelgkm=<n> Force emit a s_waitcnt lgkmcnt(0) before the first <n> instrs -amdgpu-waitcnt-forcevm=<n> Force emit a s_waitcnt vmcnt(0) before the first <n> instrs Differential Revision: https://reviews.llvm.org/D40091 llvm-svn: 320084
* [AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and ↵Mark Searles2017-12-073-17/+88
| | | | | | | | GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards(). Differential Revision: https://reviews.llvm.org/D40098 llvm-svn: 320083
* [OpenMP] NVPTX: Set default/minimum compute capability to sm_35George Rokos2017-12-071-6/+7
| | | | | | | | | The current implementation of the nvptx runtime (to be upstreamed shortly) uses the atomicMax operation on 64-bit integers. This is only supported in compute capabilities 3.5 and later. I've changed the clang default to sm_35. Differential Revision: https://reviews.llvm.org/D40977 llvm-svn: 320082
* [X86] Fix InsertBitToMaskVector to only issue KSHIFTS of native size so that ↵Craig Topper2017-12-074-219/+167
| | | | | | | | | | | | upper bits are properly zeroed. There's no v2i1 or v4i1 kshift, and v8i1 is only supported with AVXDQ. Isel has fake patterns to extend these types to native shifts, but makes no guarantees about the value of any bits shifted in when shifting right. This patch promotes the vector to a type that supports a native shift first and only allows inserting into the msb of a native sized shift. I've constructed this in a way that doesn't do the promotion if we're going to fallback to using a xmm/ymm/zmm shuffle. I think I have a plan to remove the shuffle fall back entirely. In which case we this can be simplified, but I wanted to fix the correctness issue first. llvm-svn: 320081
* [X86] Fix typo in variable name. NFCCraig Topper2017-12-071-4/+4
| | | | llvm-svn: 320080
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