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* [OPENMP] Update docs for OpenMP status, NFC.Alexey Bataev2018-01-151-1/+1
| | | | llvm-svn: 322502
* [OPENMP] Add codegen for `depend` clauses on `target` directive.Alexey Bataev2018-01-1515-194/+581
| | | | | | | Added basic support for codegen of `depend` clauses on `target` directive. llvm-svn: 322501
* [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32Stanislav Mekhanoshin2018-01-157-41/+85
| | | | | | Differential Revision: https://reviews.llvm.org/D41617 llvm-svn: 322500
* [Hexagon] Implement signed and unsigned multiply-high for vectorsKrzysztof Parzyszek2018-01-154-3/+166
| | | | llvm-svn: 322499
* [Hexagon] Rewrite LowerVECTOR_SHUFFLE for 32-/64-bit vectorsKrzysztof Parzyszek2018-01-153-38/+267
| | | | | | | The old implementation was not always correct. The new one recognizes more shuffles that match specific instructions. llvm-svn: 322498
* [clang-tidy] Expand readability-redundant-smartptr-get to understand ↵Samuel Benzaquen2018-01-152-9/+36
| | | | | | | | | | | | | | implicit converions to bool in more contexts. Summary: Expand readability-redundant-smartptr-get to understand implicit converions to bool in more contexts. Reviewers: hokein Subscribers: klimek, xazax.hun, cfe-commits Differential Revision: https://reviews.llvm.org/D41998 llvm-svn: 322497
* [AMDGPU] Copy impdefs from pseudo to real instructionsStanislav Mekhanoshin2018-01-154-0/+4
| | | | | | | | | | In some cases we do not copy implicit defs from pseudo to real VOP instructions. It has no visible impact at the moment thus no tests are affected or added. Differential Revision: https://reviews.llvm.org/D41783 llvm-svn: 322496
* [X86] Fix typos in WriteVMOVNTDQSt and WriteVMOVNTPYSt pattern names. NFCI.Simon Pilgrim2018-01-151-5/+5
| | | | llvm-svn: 322495
* [RISCV] Implement RISCV ABI loweringAlex Bradbury2018-01-155-0/+1126
| | | | | | | | | | | | | | | | | | | | RISCVABIInfo is implemented in terms of XLen, supporting both RV32 and RV64. Unfortunately we need to count argument registers in the frontend in order to determine when to emit signext and zeroext attributes. Integer scalars are extended according to their type up to 32-bits and then sign-extended to XLen when passed in registers, but are anyext when passed on the stack. This patch only implements the base integer (soft float) ABIs. For more information on the RISC-V ABI, see [the ABI doc](https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md), my [golden model](https://github.com/lowRISC/riscv-calling-conv-model), and the [LLVM RISC-V calling convention patch](https://reviews.llvm.org/D39898#2d1595b4) (specifically the comment documenting frontend expectations). Differential Revision: https://reviews.llvm.org/D40023 llvm-svn: 322494
* partition_point gets the P0202 treatmentMarshall Clow2018-01-154-6/+23
| | | | llvm-svn: 322493
* More constexpr algorithms from P0202. any_of/all_of/none_of.Marshall Clow2018-01-154-9/+54
| | | | llvm-svn: 322492
* [docs] Fix mention of GCC frontendJan Korous2018-01-151-1/+1
| | | | llvm-svn: 322491
* [WebAssembly] Make WasmObjectWriter's destructor public; NFCDan Gohman2018-01-151-5/+2
| | | | | | This fixes the FIXME introduced in r315327. llvm-svn: 322490
* First part of P0202: Adding constexpr modifiers to functions in <algorithm> ↵Marshall Clow2018-01-1513-62/+222
| | | | | | and <utility>. This commit is all the is_XXX algorithms. llvm-svn: 322489
* [SystemZ] Check for legality before doing LOAD AND TEST transformations.Jonas Paulsson2018-01-152-52/+131
| | | | | | | | | | Since a load and test instruction treat its operands as signed, it can only replace a logical compare for EQ/NE uses. Review: Ulrich Weigand https://bugs.llvm.org/show_bug.cgi?id=35662 llvm-svn: 322488
* Allow function_ref(nullptr) like std::function, since it's nullable alreadySam McCall2018-01-151-0/+1
| | | | llvm-svn: 322487
* [X86] Add missing predicates for VRNDSCALES{D,S}{m,r}Clement Courbet2018-01-151-1/+1
| | | | | | | | | | | | Summary: This is similar to https://reviews.llvm.org/D41983. Reviewers: gchatelet Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42069 llvm-svn: 322486
* Update BTVER2 sched numbers for some AVX instructions (xmm version).Andrew V. Tischenko2018-01-154-32/+71
| | | | | | Differential Revision: https://reviews.llvm.org/D40067 llvm-svn: 322485
* [X86]Add missing predicates for VMOVDQUYrm,VMOVDQUYmr.Clement Courbet2018-01-151-6/+3
| | | | | | | | | | | | | | | Summary: Due to missing parentheses. This is similar to https://reviews.llvm.org/D41983. Reviewers: gchatelet Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42062 llvm-svn: 322483
* [AArch64][AsmParser] Cleanup isSImm7s4, isSImm7s8, (etc) functions.Sander de Smalen2018-01-152-44/+22
| | | | | | | | | | | | Reviewers: fhahn, rengolin, t.p.northover, echristo, olista01, samparker Reviewed By: fhahn, samparker Subscribers: samparker, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D41899 llvm-svn: 322481
* [clangd] Merge results from static/dynamic index.Sam McCall2018-01-1510-35/+204
| | | | | | | | | | | | | | | | Summary: We now hide the static/dynamic split from the code completion, behind a new implementation of the SymbolIndex interface. This will reduce the complexity of the sema/index merging that needs to be done by CodeComplete, at a fairly small cost in flexibility. Reviewers: hokein Subscribers: klimek, mgorny, ilya-biryukov, cfe-commits Differential Revision: https://reviews.llvm.org/D42049 llvm-svn: 322480
* [clang-format] Adds a FormatStyleSetKrasimir Georgiev2018-01-152-9/+88
| | | | | | | | | | | | | | | | Summary: This patch adds a FormatStyleSet for storing per-language FormatStyles for the purposes of formatting code blocks inside the main code. Reviewers: bkramer Reviewed By: bkramer Subscribers: klimek, djasper, bkramer, cfe-commits Differential Revision: https://reviews.llvm.org/D41487 llvm-svn: 322479
* [X86] Fix missing predicates HasAVX512 Predicates in avx512_sqrt_scalar.Clement Courbet2018-01-151-38/+39
| | | | | | | | | | | | | | Summary: For example, VSQRTSDZr and VSQRTSSZr were missing the predicate. Also fix braces indentation and braces for consistency. Reviewers: craig.topper, RKSimon Suscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41983 llvm-svn: 322478
* One more attempt to fix NetBSD buildPavel Labath2018-01-151-1/+1
| | | | llvm-svn: 322477
* Fix NetBSD build for llvm r322475Pavel Labath2018-01-151-3/+3
| | | | llvm-svn: 322476
* [Support] Remove MemoryBuffer::getNewMemBufferPavel Labath2018-01-152-10/+0
| | | | | | | all callers have been switched the the Writable version (which does not require const_casting to be useful). llvm-svn: 322475
* Revert "[DAG] Elide overlapping stores"Benjamin Kramer2018-01-152-22/+24
| | | | | | | This reverts commit r322085. Internal PPC testing is still showing the same symptoms as when this patch landed the last time. llvm-svn: 322474
* [LV] Don't call recordVectorLoopValueForInductionCast for newly-created IV ↵Andrei Elovikov2018-01-152-2/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | from a trunc. Summary: This method is supposed to be called for IVs that have casts in their use-def chains that are completely ignored after vectorization under PSE. However, for truncates of such IVs the same InductionDescriptor is used during creation/widening of both original IV based on PHINode and new IV based on TruncInst. This leads to unintended second call to recordVectorLoopValueForInductionCast with a VectorLoopVal set to the newly created IV for a trunc and causes an assert due to attempt to store new information for already existing entry in the map. This is wrong and should not be done. Fixes PR35773. Reviewers: dorit, Ayal, mssimpso Reviewed By: dorit Subscribers: RKSimon, dim, dcaballe, hsaito, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D41913 llvm-svn: 322473
* Fix HostInfoBase::ComputeSharedLibraryDirectory commentPavel Labath2018-01-151-4/+2
| | | | | | | | The comment seems to indicate that this function would return the "bin" directory on linux. I've verified that this is not the case, so I'm updating the comment to match. llvm-svn: 322472
* [X86][AVX512F_512]: Adding full coverage of MC encoding for the AVX512F 512 ↵Gadi Haber2018-01-152-0/+70464
| | | | | | | | | | | | | | | bits isa sets.<NFC> NFC. Adding MC regressions tests to cover the AVX512F_512 isa sets both 32 and 64 bit. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets. started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, craig.topper, RKSimon, AndreiGrischenko Differential Revision: https://reviews.llvm.org/D41172 Change-Id: I46aa33dd967d63d33f67d1988ad42d8df2081e39 llvm-svn: 322471
* [GlobalsAA] Don't let dbg intrinsics affect analysis resultMikael Holmen2018-01-152-0/+61
| | | | | | | | | | | | | | | | | | Summary: This fixes PR35899. Debug info intrinsics shouldn't affect code generation so ignore them in GlobalsAA. Reviewers: hfinkel, aprantl Reviewed By: aprantl Subscribers: aprantl, llvm-commits Differential Revision: https://reviews.llvm.org/D41984 llvm-svn: 322470
* Clang counterpart change for fuzzer FreeBSD supportKamil Rytarowski2018-01-151-0/+2
| | | | | | | | | | | | | | | | Summary: Providing fuzzer sanitizer support for FreeBSD (but only for X86/64 architectures). Reviewers: kimgr, EricWF, martell Reviewed By: martell Patch by David CARLIER. Subscribers: krytarowski, kimgr, emaste, cfe-commits Differential Revision: https://reviews.llvm.org/D41809 llvm-svn: 322469
* [NFC] Fix comment to adjust to realityMax Kazantsev2018-01-151-1/+1
| | | | llvm-svn: 322468
* [BasicAA] Stop crashing when dealing with pointers > 64 bits.Davide Italiano2018-01-152-0/+19
| | | | | | | | | | | | | | | An alternative (and probably better) fix would be that of making `Scale` an APInt, and there's a patch floating around to do this. As we're still discussing it, at least stop crashing in the meanwhile (added bonus, we now have a regression test for this situation). Fixes PR35843. Thanks to Eli for suggesting the fix and Simon for reporting and reducing the bug. llvm-svn: 322467
* [GlobalISel][Legalizer] Convert some typedefs to using. NFC.Amara Emerson2018-01-151-3/+3
| | | | llvm-svn: 322466
* [X86][SSE] Tag PR21137 test caseSimon Pilgrim2018-01-141-1/+2
| | | | | | The test was added ages ago, but we didn't comment where it came from. llvm-svn: 322465
* [X86] Add test cases for D41794.Craig Topper2018-01-142-0/+408
| | | | llvm-svn: 322464
* [X86][SSE] Add PR22391 test caseSimon Pilgrim2018-01-141-0/+45
| | | | llvm-svn: 322463
* [X86] Autoupgrade kunpck intrinsics using vector operations instead of ↵Craig Topper2018-01-145-77/+84
| | | | | | | | | | | | | | | | scalar operations Summary: This patch changes the kunpck intrinsic autoupgrade to use vXi1 shufflevector operations to perform vector extracts and concats. This more closely matches the definition of the kunpck instructions. Currently we rely on a DAG combine to turn the scalar shift/and/or code into a concat vectors operation. By doing it in the IR we get this for free. Reviewers: spatel, RKSimon, zvi, jina.nahias Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42018 llvm-svn: 322462
* [X86] Implement old kunpck intrinsics using vector ops on vXi1 instead of ↵Craig Topper2018-01-145-21/+44
| | | | | | | | | | | | | | | | | | | integer shift/and/or Summary: kunpck intrinsics were removed in favor of native IR a few months ago. The implementation lowers them as by operation on the integer types passed to the intrinsic and then just shifting, masking, and oring them together. A special X86 DAG combine was added to recognize this patter and turn it into a concat_vector operation. I think it makes more sense to keep the IR implementation closer to vector operations on vXi1. Given that we expect these builtins to be used around other builtins that operate on k-registers which we try to represent in IR with vXi1. InstCombine should be able to get rid of the bitcasts between integers and vXi1 leaving only the vector operations. Reviewers: RKSimon, spatel, zvi, jina.nahias Reviewed By: RKSimon Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D42016 llvm-svn: 322461
* [X86] Regenerate fp128 testSimon Pilgrim2018-01-141-11/+18
| | | | llvm-svn: 322460
* [X86][SSE] Support combining MOVLHPS undef inputsSimon Pilgrim2018-01-142-2/+2
| | | | llvm-svn: 322459
* [X86][SSE] Add v2f64 3u shuffle testSimon Pilgrim2018-01-141-0/+14
| | | | | | Shows a missed opportunity to remove a unnecessary move compared to 31 shuffle mask. llvm-svn: 322458
* [x86] auto-generate complete checks; NFCSanjay Patel2018-01-142-21/+73
| | | | llvm-svn: 322457
* [InstSimplify] fix code comments; NFCSanjay Patel2018-01-141-8/+8
| | | | llvm-svn: 322456
* [X86] Use ISD::TRUNCATE instead of X86ISD::VTRUNC when input and output ↵Craig Topper2018-01-1411-374/+87
| | | | | | types have the same number of elements. llvm-svn: 322455
* [X86] Add X86ISD::VTRUNC to computeKnownBitsForTargetNode.Craig Topper2018-01-142-2/+14
| | | | | | | | We have to take special care to avoid the cases where the result of the truncate would be padded with zero elements. Ideally we'd just use ISD::TRUNCATE for these cases instead. llvm-svn: 322454
* Remove dead code.Rui Ueyama2018-01-141-7/+0
| | | | | | | | | parseInt assumed that it could take a negative number literal (e.g. "-123"). However, such number is in reality already handled as a unary operator '-' followed by a number literal, so the number literal is always non-negative. Thus, this code is dead. llvm-svn: 322453
* Reland "[Driver] Update default sanitizer blacklist location"Petr Hosek2018-01-145-1/+1
| | | | | | | | | This is related to moving the sanitizer blacklists to share/ subdirectory. Differential Revision: https://reviews.llvm.org/D41706 llvm-svn: 322452
* Reland "Install resource files into a share/ directory"Petr Hosek2018-01-142-4/+7
| | | | | | | | | | | Currently these files are being installed into a root installation directory, but this triggers an error when the installation directory is set to an empty string which is often the case when DESTDIR is used to control the installation destination. Differential Revision: https://reviews.llvm.org/D41673 llvm-svn: 322451
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