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* [Hexagon] Better detection of identity and undef masks in shufflesKrzysztof Parzyszek2017-12-122-9/+21
| | | | llvm-svn: 320523
* Add an #include to appease an older clang, NFCVedant Kumar2017-12-121-0/+1
| | | | | | | Add in a missing #include that AppleClang-900 complains about when building with -DLLVM_ENABLE_MODULES. llvm-svn: 320522
* [OpenMP] Diagnose function name on the link clauseKelvin Li2017-12-125-9/+22
| | | | | | | | | | | This patch is to add diagnose when a function name is specified on the link clause. According to the OpenMP spec, only the list items that exclude the function name are allowed on the link clause. Differential Revision: https://reviews.llvm.org/D40968 llvm-svn: 320521
* Remove trailing whitespace.Rui Ueyama2017-12-1238-1068/+1068
| | | | llvm-svn: 320520
* [cmake] Follow-up to rL320494.Don Hinton2017-12-121-2/+2
| | | | | | EXISTS requires full paths. llvm-svn: 320519
* [MinGW] Don't pass -dynamicbase:no by default for arm/arm64Martin Storsjo2017-12-122-7/+9
| | | | | | | | | | | The linker refuses using -dynamicbase:no on these architectures. Stop passing -dynamicbase (which just reinforces the lld-link default) for simplicity. Differential Revision: https://reviews.llvm.org/D41052 llvm-svn: 320518
* [COFF] Disallow -dynamicbase:no for arm and arm64Martin Storsjo2017-12-123-0/+16
| | | | | | | | This matches what MSVC link.exe does. Differential Revision: https://reviews.llvm.org/D41051 llvm-svn: 320517
* [Hexagon] Fix wrong order of operands for vmuxKrzysztof Parzyszek2017-12-122-1/+16
| | | | | | | | | | | | Shuffle generation uses vmux to collapse vectors resulting from two individual shuffles into one. The indexes of the elements selected from the first operand were indicated by 0xFF in the constant vector used in the compare instruction, but the compare (veqb) set the bits corresponding to the 0x00 elements, thus inverting the selection. Reverse the order of operands to vmux to get the correct output. llvm-svn: 320516
* Reassociate: add global reassociation algorithmFiona Glaser2017-12-125-6/+137
| | | | | | | | | | | | | | | | | | | | | | | This algorithm (explained more in the source code) takes into account global redundancies by building a "pair map" to find common subexprs. The primary motivation of this is to handle situations like foo = (a * b) * c bar = (a * d) * c where we currently don't identify that "a * c" is redundant. Accordingly, it prioritizes the emission of a * c so that CSE can remove the redundant calculation later. Does not change the actual reassociation algorithm -- only the order in which the reassociated operand chain is reconstructed. Gives ~1.5% floating point math instruction count reduction on a large offline suite of graphics shaders. llvm-svn: 320515
* [msan] LIT: Add lld testing configRoman Lebedev2017-12-122-6/+26
| | | | | | | | | | | | | | | | Summary: A follow-up for D39508, with memory sanitizer changes. Reviewers: eugenis, vitalybuka Reviewed By: eugenis Subscribers: mgorny, mehdi_amini, kcc, #sanitizers, llvm-commits Tags: #sanitizers, #lld Differential Revision: https://reviews.llvm.org/D40768 llvm-svn: 320514
* Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load ↵Alexey Bataev2017-12-122-59/+11
| | | | | | | | bitcast." This reverts commit r320510 - again sanitizers bbots. llvm-svn: 320513
* Reapply "[X86] Flag BroadWell scheduler model as complete"Sanjoy Das2017-12-128-40/+43
| | | | | | | This reverts commit r320508, in effect re-applying r320308. Simon has already reverted the parts that caused the crash that motivated the revert in r320492. llvm-svn: 320512
* Split IndirectBr critical edges before PGO gen/use passes.Hiroshi Yamauchi2017-12-126-14/+87
| | | | | | | | | | | | | | | | | | | | | | Summary: The PGO gen/use passes currently fail with an assert failure if there's a critical edge whose source is an IndirectBr instruction and that edge needs to be instrumented. To avoid this in certain cases, split IndirectBr critical edges in the PGO gen/use passes. This works for blocks with single indirectbr predecessors, but not for those with multiple indirectbr predecessors (splitting an IndirectBr critical edge isn't always possible.) Reviewers: davidxl, xur Reviewed By: davidxl Subscribers: efriedma, llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D40699 llvm-svn: 320511
* [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev2017-12-122-11/+59
| | | | | | | | | | | | | | | | | Summary: If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 llvm-svn: 320510
* [libcxx] P0604, invoke_result and is_invocableZhihao Yuan2017-12-1210-319/+407
| | | | | | | | | | | | | | | | | | | | Summary: Introduce a new form of `result_of` without function type encoding. Rename and split `is_callable/is_nothrow_callable` into `is_invocable/is_nothrow_invocable/is_invocable_r/is_nothrow_invocable_r` (and associated types accordingly) Change function type encoding of previous `is_callable/is_nothrow_callable` traits to conventional template type parameter lists. Reviewers: EricWF, mclow.lists, bebuch Reviewed By: EricWF, bebuch Subscribers: lichray, bebuch, cfe-commits Differential Revision: https://reviews.llvm.org/D38831 llvm-svn: 320509
* Revert "[X86] Flag BroadWell scheduler model as complete"Sanjoy Das2017-12-128-43/+40
| | | | | | | This reverts commit r320308. r320308 crashes LLC, please see the llvm-commits thread for a reproducer. llvm-svn: 320508
* [X86] Add a couple TODOs about missing coverage/features motivated by D40335Craig Topper2017-12-121-0/+4
| | | | | | D40335 was wanting to add FMSUBADD support, but it discovered that there are two pieces of code to make FMADDSUB and only one of those is tested. So I've asked that review to implement the one path until we get tests that test the existing code. llvm-svn: 320507
* Add --cuda-path to mock a CUDA Toolkit installation to avoidKelvin Li2017-12-121-1/+1
| | | | | | | | | unexpected error messages for incompatibility between the default SM level and the support in the installed toolkit. Differential Revision: https://reviews.llvm.org/D40996 llvm-svn: 320506
* [X86] Cleanup type conversion of 64-bit load-store pairs.Nirav Dave2017-12-122-102/+69
| | | | | | | | | | | | | | | | Summary: Simplify and generalize chain handling and search for 64-bit load-store pairs. Nontemporal test now converts 64-bit integer load-store into f64 which it realizes directly instead of splitting into two i32 pairs. Reviewers: craig.topper, spatel Reviewed By: craig.topper Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40918 llvm-svn: 320505
* Test commit.Alexandre Ganea2017-12-121-0/+1
| | | | llvm-svn: 320504
* [MachineOperand][MIR] Add isRenamable to MachineOperand.Geoff Berry2017-12-1226-64/+176
| | | | | | | | | | | | | | | | | | Summary: Add isRenamable() predicate to MachineOperand. This predicate can be used by machine passes after register allocation to determine whether it is safe to rename a given register operand. Register operands that aren't marked as renamable may be required to be assigned their current register to satisfy constraints that are not captured by the machine IR (e.g. ABI or ISA constraints). Reviewers: qcolombet, MatzeB, hfinkel Subscribers: nemanjai, mcrosier, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D39400 llvm-svn: 320503
* Fix line endings. NFC.Rafael Espindola2017-12-122-11/+11
| | | | llvm-svn: 320502
* Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load ↵Alexey Bataev2017-12-122-51/+4
| | | | | | | | | bitcast." This reverts commit r320499 again to resolve the problem with the sanitizers bbots. llvm-svn: 320501
* workaround PR 28385 in __find_exactly_one_checkedCasey Carter2017-12-121-3/+3
| | | | | | | | Fixes #35578. Differential Revision: D41048 llvm-svn: 320500
* [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev2017-12-122-4/+51
| | | | | | | | | | | | | | | | | Summary: If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 llvm-svn: 320499
* Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load ↵Alexey Bataev2017-12-122-59/+11
| | | | | | | | | bitcast." This reverts commit r320496 to solve the problems with sanitizer buildbots. llvm-svn: 320498
* [cmake] Support moving debuginfo-tests to llvm/projectsDon Hinton2017-12-122-2/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D40972 llvm-svn: 320497
* [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev2017-12-122-11/+59
| | | | | | | | | | | | | | | | | Summary: If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 llvm-svn: 320496
* [debuginfo-tests] Support moving debuginfo-tests to llvm/projectsDon Hinton2017-12-125-0/+197
| | | | | | | | | | | | | | | | | | | | Summary: Add cmake and lit files needed to run these tests as an external project. Also, copy test_debuginfo.pl from llvm/utils since it's only used here. The copy in llvm/utils must be maintained as long as bots continue to include debuginfo-tests in clang/test. This patch depends on clang patch https://reviews.llvm.org/D41055. Reviewers: zturner, aprantl Reviewed By: aprantl Subscribers: mgorny, llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D40971 llvm-svn: 320495
* [debuginfo-tests] Add support for moving debuginfo-tests from clang/test to ↵Don Hinton2017-12-122-2/+19
| | | | | | | | | | | | | | | | | | | | | llvm/projects or monorepo. Summary: The new version of debuginfo-tests will have it's own lit.cfg.py file which is incompatible with the one in clang/test. This change supports both the old and new versions, and can be used until the bots actually move debuginfo-tests to either clang/test or the monorepo. This is a prerequisite for D40971. Reviewers: zturner, aprantl Subscribers: mgorny, JDevlieghere, llvm-commits, cfe-commits Differential Revision: https://reviews.llvm.org/D41055 llvm-svn: 320494
* Revert a part of 320489 that was submitted unintentionally.Erich Keane2017-12-121-2/+1
| | | | llvm-svn: 320493
* [X86] Remove CompleteModel tags from CPU targets until we have better error ↵Simon Pilgrim2017-12-125-0/+53
| | | | | | | | | | checking (PR35636) The checks we have for complete models are not great and miss many cases - e.g. in PR35636 it failed to recognise that only the first output (of 2) was actually tagged by the InstRW Raised PR35639 and PR35643 as examples llvm-svn: 320492
* [RISCV][NFC] Formatting fix in RISCVInstrInfo.tdAlex Bradbury2017-12-121-4/+4
| | | | llvm-svn: 320491
* Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load ↵Alexey Bataev2017-12-122-50/+4
| | | | | | | | bitcast." This reverts commit r320488 because of the failed asan buildbots.. llvm-svn: 320490
* Fix ICE when __has_unqiue_object_representations called with invalid declErich Keane2017-12-123-1/+13
| | | | llvm-svn: 320489
* [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev2017-12-122-4/+50
| | | | | | | | | | | | | | | | | Summary: If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 llvm-svn: 320488
* [RISCV] Implement assembler pseudo instructions for RV32I and RV64IAlex Bradbury2017-12-128-1/+288
| | | | | | | | | | | | | | | | | | | | Adds the assembler pseudo instructions of RV32I and RV64I which can be mapped to a single canonical instruction. The missing pseudo instructions (e.g., call, tail, ...) are marked as TODO. Other things, like for example PCREL_LO, have to be implemented first. Currently, alias emission is disabled by default to keep the patch minimal. Alias emission by default will be enabled in a subsequent patch which also updates all affected tests. Note that this patch should actually break the floating point MC tests. However, the used FileCheck configuration is not tight enought to detect the breakage. Differential Revision: https://reviews.llvm.org/D40902 Patch by Mario Werner. llvm-svn: 320487
* [clangd] Introduce a "Symbol" class.Haojian Wu2017-12-127-0/+443
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: * The "Symbol" class represents a C++ symbol in the codebase, containing all the information of a C++ symbol needed by clangd. clangd will use it in clangd's AST/dynamic index and global/static index (code completion and code navigation). * The SymbolCollector (another IndexAction) will be used to recollect the symbols when the source file is changed (for ASTIndex), or to generate all C++ symbols for the whole project. In the long term (when index-while-building is ready), clangd should share a same "Symbol" structure and IndexAction with index-while-building, but for now we want to have some stuff working in clangd. Reviewers: ioeric, sammccall, ilya-biryukov, malaperle Reviewed By: sammccall Subscribers: malaperle, klimek, mgorny, cfe-commits Differential Revision: https://reviews.llvm.org/D40897 llvm-svn: 320486
* Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load ↵Alexey Bataev2017-12-122-47/+2
| | | | | | | | bitcast." This reverts commit r320483 because of the failed Windows buildbots. llvm-svn: 320485
* [RISCV] MC layer support for the instructions added in the privileged specAlex Bradbury2017-12-123-0/+81
| | | | | | | | | | | | | | | Adds support for the instructions added in the RISC-V privileged ISA (https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf): uret, sret, mret, wfi, and sfence.vma. Note from the committer: I made very minor formatting changes prior to commit, which didn't seem worth creating another review round-trip for. Differential Revision: https://reviews.llvm.org/D40383 Patch by David Craven. llvm-svn: 320484
* [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev2017-12-122-2/+47
| | | | | | | | | | | | | | | | If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 llvm-svn: 320483
* [clangd] Removed unused variable. NFCIlya Biryukov2017-12-121-1/+1
| | | | llvm-svn: 320482
* [X86] Recognize constant arrays with special values and replace loads from ↵Ayman Musa2017-12-122-22/+135
| | | | | | | | | | | | | | | | | | | it with subtract and shift instructions, which then will be replaced by X86 BZHI machine instruction. Recognize constant arrays with the following values: 0x0, 0x1, 0x3, 0x7, 0xF, 0x1F, .... , 2^(size - 1) -1 where //size// is the size of the array. the result of a load with index //idx// from this array is equivalent to the result of the following: (0xFFFFFFFF >> (sub 32, idx)) (assuming the array of type 32-bit integer). And the result of an 'AND' operation on the returned value of such a load and another input, is exactly equivalent to the X86 BZHI instruction behavior. See test cases in the LIT test for better understanding. Differential Revision: https://reviews.llvm.org/D34141 llvm-svn: 320481
* [InstComineLoadStoreAlloca] Optimize stores to GEP off null baseAnna Thomas2017-12-122-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Currently, in InstCombineLoadStoreAlloca, we have simplification rules for the following cases: 1. load off a null 2. load off a GEP with null base 3. store to a null This patch adds support for the fourth case which is store into a GEP with null base. Since this is UB as well (and directly analogous to the load off a GEP with null base), we can substitute the stored val with undef in instcombine, so that SimplifyCFG can optimize this code into unreachable code. Note: Right now, simplifyCFG hasn't been taught about optimizing this to unreachable and adding an llvm.trap (this is already done for the above 3 cases). Reviewers: majnemer, hfinkel, sanjoy, davide Reviewed by: sanjoy, davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41026 llvm-svn: 320480
* [clang-format] Improve ObjC headers detection.Krasimir Georgiev2017-12-122-1/+14
| | | | | | | | | | | This patch improves detection of ObjC header files. Right now many ObjC headers, especially short ones, are categorized as C/C++. Way of filtering still isn't the best, as most likely it should be token-based. Contributed by jolesiak! llvm-svn: 320479
* [ELF] Refactor to remove loop copying all Sections in OS->finalize() [NFC]Peter Smith2017-12-121-10/+11
| | | | | | | | | | Moving the SHF_LINK_ORDER processing out of OutputSection::finalize() means that we no longer need to copy all InputSections as we now only need the first one. Differential Revision: https://reviews.llvm.org/D40966 llvm-svn: 320478
* [ELF] Move SHF_LINK_ORDER processing earlier in Writer.cpp [NFC]Peter Smith2017-12-122-24/+43
| | | | | | | | | | By moving this step before thunk creation and other processing that depends on the size of sections, we permit removal of duplicates in the .ARM.exidx section. Differential Revision: https://reviews.llvm.org/D40964 llvm-svn: 320477
* [clangd] clang-format the code. NFCIlya Biryukov2017-12-123-5/+5
| | | | llvm-svn: 320476
* [PowerPC] Add branch flag on asm parser-only branch instructionsNemanja Ivanovic2017-12-121-1/+1
| | | | | | | | | | | This flag was missing but it wasn't an issue as nothing depended on it for these asm parser-only instructions. Now that LLDB support is slowly landing, it is important to get this right. Committing on behalf of Leonardo Bianconi. Differential revision: https://reviews.llvm.org/D40846 llvm-svn: 320475
* [clangd] Document highlights for clangdIlya Biryukov2017-12-1213-46/+315
| | | | | | | | | | | | | | | | | Summary: Implementation of Document Highlights Request as described in LSP. Contributed by William Enright (nebiroth). Reviewers: malaperle, krasimir, bkramer, ilya-biryukov Reviewed By: malaperle Subscribers: mgrang, sammccall, klimek, ioeric, rwols, cfe-commits, arphaman, ilya-biryukov Differential Revision: https://reviews.llvm.org/D38425 llvm-svn: 320474
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