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* Suppress all uses of LLVM_END_WITH_NULL. NFC.Serge Guelton2017-05-0922-157/+122
| | | | | | | | | Use variadic templates instead of relying on <cstdarg> + sentinel. This enforces better type checking and makes code more readable. Differential Revision: https://reviews.llvm.org/D32541 llvm-svn: 302571
* [mips] XFAIL dfsan's custom.cc test on mips64.Simon Dardis2017-05-091-1/+1
| | | | | | | Test was already marked as failing for mips64el. Now that it's being tested on mips64, it has to be XFAILed there as well. llvm-svn: 302570
* [WebAssembly] Fix failing wasm-toolchain testSam Clegg2017-05-091-3/+3
| | | | | | | | This test was broken in r302558. Differential Revision: https://reviews.llvm.org/D33015 llvm-svn: 302569
* [lanai] Add computeKnownBitsForTargetNode for Lanai.Jacques Pienaar2017-05-094-5/+77
| | | | | | | | | | | | | | Summary: computeKnownBitsForTargetNode was not defined for Lanai which resulted in additional AND's with 0x1 for the output of SETCC instructions. Reviewers: eliben, majnemer Reviewed By: majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29605 llvm-svn: 302568
* [mips] Remove XFAIL from sanitizer_coverage_no_prune.ccSimon Dardis2017-05-091-1/+1
| | | | | | Test is XPASSing, so remove the XFAIL marker. llvm-svn: 302567
* [NewGVN] Explain why sorting by pointer values doesn't introduce ↵Davide Italiano2017-05-091-0/+4
| | | | | | | | non-determinism. Thanks to Eli for pointing out in a post-commit review comment. llvm-svn: 302566
* [SystemZ] Support missing relocation types in RuntimeDyldELFUlrich Weigand2017-05-091-3/+18
| | | | | | | | | Handle some more relocation types in RuntimeDyldELF::resolveSystemZRelocation This fixes a number of failing LLDB test cases. llvm-svn: 302565
* Add memory ORIGIN and LENGTH expression supportRui Ueyama2017-05-092-0/+45
| | | | | | | | | | | | | | | Adds support for the ORIGIN and LENGTH linker script built in functions. ORIGIN(memory) Return the origin of the memory region LENGTH(memory) Return the length of the memory region Redo of D29775 for refactored linker script parsing. Patch by Robert Clarke Differential Revision: https://reviews.llvm.org/D32934 llvm-svn: 302564
* [SystemZ] Remove XFAIL on sanitizer_coverage_no_prune.ccUlrich Weigand2017-05-091-1/+1
| | | | | | This test case works fine on SystemZ as well. llvm-svn: 302563
* [SystemZ] Fix failures after D32542Ulrich Weigand2017-05-091-0/+3
| | | | | | | | This commit made ubsan use the fast unwinder. On SystemZ this requires test cases to be compiled with -mbackchain. That was already done for asan, but not ubsan. Add the flag for ubsan as well. llvm-svn: 302562
* [compiler-rt][mips] Fix a test for mips.Simon Dardis2017-05-091-1/+1
| | | | | | | GCC 4.9.2 likes the specialize one of the memcpys in msan_interceptors.cc, leading to test failure. llvm-svn: 302561
* [WebAssembly] Fix validation of start functionSam Clegg2017-05-094-4/+21
| | | | | | | | | | The check for valid start function was inverted. Added a new test in test/Object to check this case and fixed the existing tests in for ObjectYAML. Differential Revision: https://reviews.llvm.org/D32986 llvm-svn: 302560
* [X86][LWP] Remove MSVC LWP intrinsics stubs.Simon Pilgrim2017-05-091-6/+0
| | | | | | Now provided in lwpintrin.h llvm-svn: 302559
* [WebAssembly] Fix location and -flavor when running lldSam Clegg2017-05-091-1/+4
| | | | | | | | | | | | | Add the toolchain installation directory to the program path so that lld can be found. Change -flavor to wasm. Although this new flavor hasn't yet landed in upstream lld yet there are no point in passing wasm objects the gnu flavor. Differential Revision: https://reviews.llvm.org/D32976 llvm-svn: 302558
* [X86][LWP] Removing LWP todo comment. NFCI.Simon Pilgrim2017-05-091-2/+0
| | | | | | LWP / lwpintrin.h is now supported llvm-svn: 302557
* Build the Apple-style stage2 with modulesAdrian Prantl2017-05-091-0/+1
| | | | | | | | | | | | | | | Green dragon had a green stage2 modules bot for a long time now[1] and it is time to retire it and make a modules build the default for Apple-style stage2 builds. This patch turns on LLVM_ENABLE_MODULES. [1] http://green.lab.llvm.org/green/job/clang-stage2-cmake-modulesRDA_build/ rdar://problem/28672159 Differential Revision: https://reviews.llvm.org/D32603 llvm-svn: 302556
* Revert r302547 ([mips] Impose a threshold for coercion of aggregates)Petar Jovanovic2017-05-092-46/+0
| | | | | | | | | | Reverting Modified MipsABIInfo::classifyArgumentType so that it now coerces aggregate structures only if the size of said aggregate is less than 16/64 bytes, depending on the ABI. as it broke clang-with-lto-ubuntu builder. llvm-svn: 302555
* [RegScavenger] Rangify a loop, NFCKrzysztof Parzyszek2017-05-091-4/+3
| | | | llvm-svn: 302554
* Adding VSCode syntax colorizer to utils (generated from textmate colorizer).Puyan Lotfi2017-05-098-0/+263
| | | | | | | | | | | | | | | | | | | --This line, and those below, will be igored-- A utils/vscode A utils/vscode/README A utils/vscode/tablegen A utils/vscode/tablegen/.vscode A utils/vscode/tablegen/.vscode/launch.json A utils/vscode/tablegen/CHANGELOG.md A utils/vscode/tablegen/README.md A utils/vscode/tablegen/language-configuration.json A utils/vscode/tablegen/package.json A utils/vscode/tablegen/syntaxes A utils/vscode/tablegen/syntaxes/TableGen.tmLanguage A utils/vscode/tablegen/vsc-extension-quickstart.md llvm-svn: 302553
* [NewGVN] Fix a consistent order for phi nodes operands.Davide Italiano2017-05-092-7/+61
| | | | | | | | | | | | | | | | | | | | | | | | | The way we currently define congruency for two PHIExpression(s) is: 1) The operands to the phi functions are congruent 2) The PHIs are defined in the same BasicBlock. NewGVN works under the assumption that phi operands are in predecessor order, or at least in some consistent order. OTOH, is valid IR: patatino: %meh = phi i16 [ %0, %winky ], [ %conv1, %tinky ] %banana = phi i16 [ %0, %tinky ], [ %conv1, %winky ] br label %end and the in-memory representations of the two SSA registers have an inconsistent order. This violation of NewGVN assumptions results into two PHIs found congruent when they're not. While we think it's useful to have always a consistent order enforced, let's fix this in NewGVN sorting uses in predecessor order before creating a PHI expression. Differential Revision: https://reviews.llvm.org/D32990 llvm-svn: 302552
* [APInt] Remove return value from tcFullMultiply.Craig Topper2017-05-092-15/+8
| | | | | | | | The description says it returns the number of words needed to represent the results. But the way it was coded it always returns (lhsWords + rhsWords) or (lhsWords + rhsWords - 1). But the result could be even smaller than that and it wouldn't tell you. No one uses the result today so rather than try to fix it, just remove it. llvm-svn: 302551
* NewGVN: Make all of symbolic evaluation logically const.Daniel Berlin2017-05-091-64/+74
| | | | llvm-svn: 302550
* [X86] Add more patterns for BZHI iselCraig Topper2017-05-092-0/+108
| | | | | | | | | | | | | | | | | | | | | | This patch adds more patterns that a reasonable person might write that can be compiled to BZHI. This adds support for (~0U >> (32 - b)) & a; and a << (32 - b) >> (32 - b); This was inspired by the code in APInt::clearUnusedBits. This can pass an index of 32 to the bzhi instruction which a quick test of Haswell hardware shows will not mask any bits. Though the description text in the Intel manual says the "index is saturated to OperandSize-1". The pseudocode in the same manual indicates no bits will be zeroed for this case. I think this is still missing cases where the subtract portion is an 8-bit operation. Differential Revision: https://reviews.llvm.org/D32616 llvm-svn: 302549
* [InstCombineCasts] Fix checks in sext->lshr->trunc pattern.Sanjay Patel2017-05-092-12/+20
| | | | | | | | | | | | | | | The comment says to avoid the case where zero bits are shifted into the truncated value, but the code checks that the shift is smaller than the truncated value instead of the number of bits added by the sign extension. Fixing this allows a shift by more than the value size to be introduced, which is undefined behavior, so the shift is capped at the value size minus one, which has the expected behavior of filling the value with the sign bit. Patch by Jacob Young! Differential Revision: https://reviews.llvm.org/D32285 llvm-svn: 302548
* [mips] Impose a threshold for coercion of aggregatesPetar Jovanovic2017-05-092-0/+46
| | | | | | | | | | | | Modified MipsABIInfo::classifyArgumentType so that it now coerces aggregate structures only if the size of said aggregate is less than 16/64 bytes, depending on the ABI. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D32900 llvm-svn: 302547
* VX512] Only look at lower bit in constant scalar masksGuy Blank2017-05-092-8/+10
| | | | | | | | | for scalar masked instructions only the lower bit of the mask is relevant. so for constant masks we should either do an unmasked operation or no operation, depending on the value of the lower bit. This patch handles cases where the lower bit is '1'. Differential Revision: https://reviews.llvm.org/D32805 llvm-svn: 302546
* [CodeCompletion] Complete platform names in @available expressionsAlex Lorenz2017-05-094-0/+43
| | | | | | rdar://32074504 llvm-svn: 302545
* Re-land "Use the frame index side table for byval and inalloca arguments"Reid Kleckner2017-05-098-108/+285
| | | | | | This re-lands r302483. It was not the cause of PR32977. llvm-svn: 302544
* Re-land "Don't add DBG_VALUE instructions for static allocas in dbg.declare"Reid Kleckner2017-05-094-208/+0
| | | | | | This re-lands commit r302461. It was not the cause of PR32977. llvm-svn: 302543
* Revert r302476 "Update testcase for upstream LLVM changes."Hans Wennborg2017-05-091-4/+2
| | | | | | That test update was for r302469, which was reverted in r302533 due to PR32977. llvm-svn: 302542
* Allow compiler-rt to find lld and libc++ parallel to LLVM, as in the monorepoReid Kleckner2017-05-091-2/+12
| | | | llvm-svn: 302541
* Add support for pretty platform names to `@available`/Alex Lorenz2017-05-097-27/+61
| | | | | | | | | | | | | `__builtin_available` This commit allows us to use the macOS/iOS/tvOS/watchOS platform names in `@available`/`__builtin_available`. rdar://32067795 Differential Revision: https://reviews.llvm.org/D33000 llvm-svn: 302540
* [Atomic] Remove IsStore/IsLoad in the interface, and pass the instruction ↵Tim Shen2017-05-098-51/+70
| | | | | | | | | | | | | | | | | instead. NFC. Now both emitLeadingFence and emitTrailingFence take the instruction itself, instead of taking IsLoad/IsStore pairs. Instruction::mayReadFromMemory and Instrucion::mayWriteToMemory are used for determining those two booleans. The instruction argument is also useful for later D32763, in emitTrailingFence. For emitLeadingFence, it seems to have cleaner interface with the proposed change. Differential Revision: https://reviews.llvm.org/D32762 llvm-svn: 302539
* [scudo] CRC32 optimizationsKostya Kortchinsky2017-05-094-98/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change optimizes several aspects of the checksum used for chunk headers. First, there is no point in checking the weak symbol `computeHardwareCRC32` everytime, it will either be there or not when we start, so check it once during initialization and set the checksum type accordingly. Then, the loading of `HashAlgorithm` for SSE versions (and ARM equivalent) was not optimized out, while not necessary. So I reshuffled that part of the code, which duplicates a tiny bit of code, but ends up in a much cleaner assembly (and faster as we avoid an extraneous load and some calls). The following code is the checksum at the end of `scudoMalloc` for x86_64 with full SSE 4.2, before: ``` mov rax, 0FFFFFFFFFFFFFFh shl r10, 38h mov edi, dword ptr cs:_ZN7__scudoL6CookieE ; __scudo::Cookie and r14, rax lea rsi, [r13-10h] movzx eax, cs:_ZN7__scudoL13HashAlgorithmE ; __scudo::HashAlgorithm or r14, r10 mov rbx, r14 xor bx, bx call _ZN7__scudo20computeHardwareCRC32Ejm ; __scudo::computeHardwareCRC32(uint,ulong) mov rsi, rbx mov edi, eax call _ZN7__scudo20computeHardwareCRC32Ejm ; __scudo::computeHardwareCRC32(uint,ulong) mov r14w, ax mov rax, r13 mov [r13-10h], r14 ``` After: ``` mov rax, cs:_ZN7__scudoL6CookieE ; __scudo::Cookie lea rcx, [rbx-10h] mov rdx, 0FFFFFFFFFFFFFFh and r14, rdx shl r9, 38h or r14, r9 crc32 eax, rcx mov rdx, r14 xor dx, dx mov eax, eax crc32 eax, rdx mov r14w, ax mov rax, rbx mov [rbx-10h], r14 ``` Reviewers: dvyukov, alekseyshl, kcc Reviewed By: alekseyshl Subscribers: aemerson, rengolin, llvm-commits Differential Revision: https://reviews.llvm.org/D32971 llvm-svn: 302538
* Amend r302535; ifndef and ifdef are different, as it turns out.Aaron Ballman2017-05-091-1/+1
| | | | llvm-svn: 302537
* [clang-tidy] Allow disabling compatibility check for generated fixes.Alexander Kornienko2017-05-092-5/+11
| | | | llvm-svn: 302536
* ARMRegisterBankInfo.h requires LLVM_BUILD_GLOBAL_ISEL to be defined. If it ↵Aaron Ballman2017-05-091-0/+2
| | | | | | is not defined, then ARMGenRegisterBank.inc is not table generated and the inclusion of this header causes the build to fail. llvm-svn: 302535
* Change EOL style to LF. NFCAlexander Kornienko2017-05-095-858/+858
| | | | llvm-svn: 302534
* Revert r302469 "Make it illegal for two Functions to point to the same ↵Hans Wennborg2017-05-097-220/+79
| | | | | | | | | | | | | | | | | | | | | | | | DISubprogram" This caused PR32977. Original commit message: > Make it illegal for two Functions to point to the same DISubprogram > > As recently discussed on llvm-dev [1], this patch makes it illegal for > two Functions to point to the same DISubprogram and updates > FunctionCloner to also clone the debug info of a function to conform > to the new requirement. To simplify the implementation it also factors > out the creation of inlineAt locations from the Inliner into a > general-purpose utility in DILocation. > > [1] http://lists.llvm.org/pipermail/llvm-dev/2017-May/112661.html > <rdar://problem/31926379> > > Differential Revision: https://reviews.llvm.org/D32975 llvm-svn: 302533
* [LV] Fix insertion point for shuffle vectors in first order recurrenceAnna Thomas2017-05-092-2/+50
| | | | | | | | | | | | | | | | | | Summary: In first order recurrence vectorization, when the previous value is a phi node, we need to set the insertion point to the first non-phi node. We can have the previous value being a phi node, due to the generation of new IVs as part of trunc optimization [1]. [1] https://reviews.llvm.org/rL294967 Reviewers: mssimpso, mkuper Subscribers: mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D32969 llvm-svn: 302532
* Removing a file that is not necessary (and was causing link diagnostics with ↵Aaron Ballman2017-05-092-11/+0
| | | | | | MSVC 2015); NFC. llvm-svn: 302531
* Avoid unnecessary calls to vm_region_recurseFrancis Ricci2017-05-091-0/+5
| | | | | | | | | | | | Summary: This should significantly improve darwin lsan performance in cases where root regions are not used. Reviewers: alekseyshl, kubamracek Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32966 llvm-svn: 302530
* [X86][AVX512] Refine some avx512er intrinsics tests. NFC.Guy Blank2017-05-091-24/+24
| | | | | | | | The modified tests should test the masked intrinsics. Currently the mask is constant, which with a future patch (https://reviews.llvm.org/D32805) will cause the intrinsics to be replaced with an unmasked version. This patch changes the constant mask to be a variable one. llvm-svn: 302529
* Use a simpler heuristic for placing orphans.Rafael Espindola2017-05-091-27/+30
| | | | | | | | This is a bit easier to read and a lot faster in some cases. A version of many-sections.s with linker scripts goes from 0m41.232s to 0m19.575s. llvm-svn: 302528
* Add extra operand to CALLSEQ_START to keep frame part set up previouslySerge Pavlov2017-05-0963-169/+190
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using arguments with attribute inalloca creates problems for verification of machine representation. This attribute instructs the backend that the argument is prepared in stack prior to CALLSEQ_START..CALLSEQ_END sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size stored in CALLSEQ_START in this case does not count the size of this argument. However CALLSEQ_END still keeps total frame size, as caller can be responsible for cleanup of entire frame. So CALLSEQ_START and CALLSEQ_END keep different frame size and the difference is treated by MachineVerifier as stack error. Currently there is no way to distinguish this case from actual errors. This patch adds additional argument to CALLSEQ_START and its target-specific counterparts to keep size of stack that is set up prior to the call frame sequence. This argument allows MachineVerifier to calculate actual frame size associated with frame setup instruction and correctly process the case of inalloca arguments. The changes made by the patch are: - Frame setup instructions get the second mandatory argument. It affects all targets that use frame pseudo instructions and touched many files although the changes are uniform. - Access to frame properties are implemented using special instructions rather than calls getOperand(N).getImm(). For X86 and ARM such replacement was made previously. - Changes that reflect appearance of additional argument of frame setup instruction. These involve proper instruction initialization and methods that access instruction arguments. - MachineVerifier retrieves frame size using method, which reports sum of frame parts initialized inside frame instruction pair and outside it. The patch implements approach proposed by Quentin Colombet in https://bugs.llvm.org/show_bug.cgi?id=27481#c1. It fixes 9 tests failed with machine verifier enabled and listed in PR27481. Differential Revision: https://reviews.llvm.org/D32394 llvm-svn: 302527
* Revert "[MIPS] Add support to match more patterns for DINS instruction"Simon Dardis2017-05-093-133/+30
| | | | | | This reverts commit rL302512. This broke the mips buildbots. llvm-svn: 302526
* [X86][SSE42] Lower v2i64/v4i64 ASHR(X, 63) as PCMPGTQ(0, X)Simon Pilgrim2017-05-096-96/+98
| | | | | | | | | | Similar to what we do for vXi8 ASHR(X, 7), use SSE42's PCMPGTQ to splat the sign instead of using the PSRAD+PSHUFD. Avoiding bitcasts this improves combines that utilize computeNumSignBits, permits memory folding and reduces pipe pressure. Although it does require a second register, given that this is a (cheap) zero register the impact is minimal. Differential Revision: https://reviews.llvm.org/D32973 llvm-svn: 302525
* Revert "[Dwarf] Disable reference verification for now (PR32972)"Diana Picus2017-05-091-2/+1
| | | | | | This reverts commit r302520 because it break the unit tests. llvm-svn: 302524
* clang-format: [JS] keep triple slash directives intact.Martin Probst2017-05-092-3/+5
| | | | | | | | | | | | | | | | | | | Summary: TypeScript uses triple slash directives of the form: /// <reference path="..."/> For various non-source instructions that should not be wrapped. Reference: https://www.typescriptlang.org/docs/handbook/triple-slash-directives.html Reviewers: djasper Subscribers: cfe-commits, klimek Differential Revision: https://reviews.llvm.org/D32997 llvm-svn: 302523
* [clang-tidy] Minor cleanup + a disabled test case for PR26228. NFCAlexander Kornienko2017-05-092-5/+16
| | | | llvm-svn: 302522
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