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* Count how many phis we are creating.Rafael Espindola2011-06-081-0/+2
| | | | llvm-svn: 132748
* Fix a bunch more notes that were emitted even when the diagnostic theyChandler Carruth2011-06-081-6/+9
| | | | | | were intended for was suppressed. llvm-svn: 132746
* Revert "hack in my new variables for GCC"Chandler Carruth2011-06-083-44/+24
| | | | | | Very sorry for the accidental commit of WIP code. llvm-svn: 132745
* Fix a regression in the two-phase lookup diagnostics that switching theChandler Carruth2011-06-082-0/+24
| | | | | | | | namespace set algorithm (re-)introduced. We may not have seen the 'std' namespace, but we should still suggested associated namespaces. Easy fix, but a bit annoying to test. llvm-svn: 132744
* hack in my new variables for GCCChandler Carruth2011-06-083-24/+44
| | | | llvm-svn: 132743
* Fix an issue where the two-address conversion pass incorrectly rewrites untiedCameron Zwarich2011-06-072-9/+52
| | | | | | operands to an early clobber register. This fixes <rdar://problem/9566076>. llvm-svn: 132738
* Clang support for ARM Uv/Uy/Uq inline-asm constraints.Stuart Hastings2011-06-074-8/+37
| | | | | | rdar://problem/9037836 llvm-svn: 132737
* Sort -lgcc after -lgcc_s for NetBSD, otherwise shared libraries on i386Joerg Sonnenberger2011-06-071-1/+1
| | | | | | may pick it up. This would create bad text relocations. llvm-svn: 132736
* Fix a silly error I introduce in r131951.Rafael Espindola2011-06-072-6/+12
| | | | | | Fixes PR10095. llvm-svn: 132735
* Create a new ARM directory for FrontendC tests and use it.Eric Christopher2011-06-071-0/+0
| | | | llvm-svn: 132734
* Fixed a few illegal paths with llvm_unreachable. Patch by Cameron McInally.Chad Rosier2011-06-071-7/+5
| | | | llvm-svn: 132732
* More coherent diagnostic when a stack variable isFariborz Jahanian2011-06-073-3/+9
| | | | | | declared __weak objc-gc mode. // rdar://9666091. llvm-svn: 132731
* Typo.Chad Rosier2011-06-071-1/+1
| | | | llvm-svn: 132730
* tabs to spacesHoward Hinnant2011-06-073-39/+39
| | | | llvm-svn: 132729
* Refactor MipsTargetLowering::EmitInstrWithCustomInserter.Akira Hatanaka2011-06-071-92/+90
| | | | llvm-svn: 132726
* Put back removed line.Akira Hatanaka2011-06-071-0/+1
| | | | llvm-svn: 132725
* Coding style fixes.Akira Hatanaka2011-06-073-44/+31
| | | | | | | | | - Fix indentation. - Move comments. - Fit lines in 80 columns. - Remove dead code. llvm-svn: 132724
* Add support for the ARM EABI variant of the __cxa_guard methods, controlled byNick Lewycky2011-06-072-6/+68
| | | | | | the LIBCXXABI_ARMEABI macro. llvm-svn: 132723
* Use tabs to separate opcode and operand strings.Akira Hatanaka2011-06-071-21/+21
| | | | llvm-svn: 132718
* Add comments for wrapper node patterns in MipsInstrInfo.td.Akira Hatanaka2011-06-071-1/+10
| | | | llvm-svn: 132717
* Test that ".byte 1, 2, 3, 4" does the right thing.Roman Divacky2011-06-071-0/+7
| | | | | | Requested by nbjoerg! llvm-svn: 132716
* Make EmitIntValue() work properly on big-endian targets.Roman Divacky2011-06-071-3/+6
| | | | llvm-svn: 132715
* Tweak this test for ARM-hosted 'bot.Stuart Hastings2011-06-071-1/+1
| | | | llvm-svn: 132711
* The macros defined by the language standard are still available even when theNick Lewycky2011-06-072-26/+41
| | | | | | | -undef flag is passed in. Also __ASSEMBLER__ with -x assembler-with-cpp. (Don't ask.) llvm-svn: 132708
* Switched to DenseMap for allowed sets in PBQP. Reduces total LLC time by 15% ↵Lang Hames2011-06-071-1/+1
| | | | | | on CINT2006 for x86-32. llvm-svn: 132707
* Move the legalizer tests to the X86 directory because the test uses the x86Nadav Rotem2011-06-071-1/+8
| | | | | | codegen. Thanks Galina. llvm-svn: 132706
* Downgrade the warning about the use of typedefs for class templateDouglas Gregor2011-06-072-3/+3
| | | | | | | | specializations within an explicit instantiation to default to off (enabled by -pedantic). Nobody else seem to implement C++ [temp.explicit]p3. Fixes PR10093. llvm-svn: 132704
* Add test case for C++ exception handling and fix the following mistakes in ↵Akira Hatanaka2011-06-072-30/+138
| | | | | | | | | | | | | | | | | | MipsFrameLowering::emitPrologue: - cfi directives are not inserted at the right location or in the right order. - The source MachineLocation for the cfi directive that changes the cfa register to $fp should be MachineLocation::VirtualFP. - A PROLOG_LABEL that marks the beginning of cfi_offset directives for callee-saved register is emitted even when no callee-saved registers are saved. - When a callee-saved double precision register is saved, two cfi_offset directives, one for each of the paired single precision registers, should be emitted. llvm-svn: 132703
* Fix a merge bug in preRAsched for handling physreg aliases.Andrew Trick2011-06-071-4/+6
| | | | | | | I've been sitting on this long enough trying to find a test case. I think the fix should go in now, but I'll keep working on the test case. llvm-svn: 132701
* Catch the memory leak in a bucketAlexis Hunt2011-06-071-1/+2
| | | | llvm-svn: 132700
* Fix for setjmp/longjmp exception handling on ARM. setjmp clobbers CPSR.Andrew Trick2011-06-073-5/+5
| | | | | | rdar://problem/9556069 llvm-svn: 132699
* Simplify local live range splitting's safeguard to fix PR10070.Jakob Stoklund Olesen2011-06-062-89/+68
| | | | | | | | | | | | | | | When local live range splitting creates a live range with the same number of instructions as the old range, mark it as RS_Local. When such a range is seen again, require that it be split in a way that reduces the number of instructions. That guarantees we are making progress while still being able to perform 3 -> 2+3 splits as required by PR10070. This also means that the PrevSlot map is no longer needed. This was also used to estimate new spill weights, but that is no longer necessary after slotIndexes::insertMachineInstrInMaps() got the extra Late insertion argument. llvm-svn: 132697
* Followup to 132458, omit unnecessary stack copy when x87 input is aStuart Hastings2011-06-063-7/+56
| | | | | | load. rdar://problem/6373334 llvm-svn: 132696
* Add -O1/2/3 to bugpoint, so when you conclude opt -O2 reproduces an issue, ↵Eli Friedman2011-06-061-2/+28
| | | | | | you can just run bugpoint -O2. :) My implementation isn't precisely equivalent to what opt does, but as far as I can tell, it's close enough. llvm-svn: 132695
* Second try at fixing this test, this time without breaking 32-bit Darwin ↵Eli Friedman2011-06-061-1/+1
| | | | | | builders. llvm-svn: 132694
* We only do always-inlining at -O1; make opt reflect that.Eli Friedman2011-06-061-1/+1
| | | | llvm-svn: 132693
* Remove extra whitespace.Johnny Chen2011-06-061-1/+0
| | | | llvm-svn: 132692
* Start fixing up clang tests to work on the clang-native-arm-cortex-a9 builder.Eli Friedman2011-06-066-15/+18
| | | | llvm-svn: 132691
* Get allocation orders from RegisterClassInfo when possible.Jakob Stoklund Olesen2011-06-062-23/+52
| | | | | | | | | | | | Only target-dependent hints require callbacks. The RCI allocation order has CSR aliases last according to their order of appearance in the getCalleeSavedRegs list. This can depend on the calling convention. This way, AllocationOrder::next doesn't have to check for reserved registers, and CSRs are always allocated last, even with weird calling conventions. llvm-svn: 132690
* Add methods to support the integer-promotion of vector types. Methods toNadav Rotem2011-06-064-1/+264
| | | | | | legalize SDNodes such as BUILD_VECTOR, EXTRACT_VECTOR_ELT, etc. llvm-svn: 132689
* Don't put a note in the DiagGroupAlexis Hunt2011-06-061-2/+1
| | | | llvm-svn: 132687
* This directory was missing the dg.exp to cause the tests to run. Some time sinceNick Lewycky2011-06-062-0/+4
| | | | | | it was added, the test has regressed, so XFAIL it. llvm-svn: 132686
* Test case for PR10085.Stuart Hastings2011-06-061-0/+8
| | | | llvm-svn: 132682
* Avoid FGETSIGN of 80-bit types. Fixes PR10085.Stuart Hastings2011-06-061-6/+8
| | | | llvm-svn: 132681
* Don't try to be clever, just preserve the target's allocation order.Jakob Stoklund Olesen2011-06-061-11/+6
| | | | | | | | | | | | | | | The order of registers returned by getCalleeSavedRegs is used to lay out the fixed stack slots for CSRs. Some targets like their CSRs used from one end, and some targets want them used from the other end. When computing an allocation order, simply preserve the relative ordering of CSRs that the target specifies in its allocation order. Reordering CSRs would break some targets, ARM in particular. We still place volatiles before the CSRs, providing slightly better results with different calling conventions. llvm-svn: 132680
* Touchup to comments that weren't quite in sync with codeJonathan D. Turner2011-06-061-2/+3
| | | | llvm-svn: 132679
* www: Add website for the LLVM bugtracker useTobias Grosser2011-06-062-1/+39
| | | | llvm-svn: 132678
* Diagnose the condition in C++ [temp.expl.spec]p16 that prohibitsDouglas Gregor2011-06-064-4/+58
| | | | | | | specializing a member of an unspecialized template, and recover from such errors without crashing. Fixes PR10024 / <rdar://problem/9509761>. llvm-svn: 132677
* PR10077: fix fast-isel of extractvalue of aggregate constants.Eli Friedman2011-06-062-1/+14
| | | | llvm-svn: 132676
* ok now, let's fix that MSVC warning for real.Francois Pichet2011-06-061-1/+1
| | | | llvm-svn: 132675
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