summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
* [clang-apply-replacements] Convert tooling::Replacements to ↵Malcolm Parsons2018-04-1117-521/+215
| | | | | | | | | | | | | | | | | | | | tooling::AtomicChange for conflict resolving of changes, code cleanup, and code formatting. Summary: By converting Replacements by AtomicChange, clang-apply-replacements is able like clang-tidy to automatically cleanup and format changes. This should permits to close this ticket: https://bugs.llvm.org/show_bug.cgi?id=35051 and attempt to follow hints from https://reviews.llvm.org/D43500 comments. Reviewers: klimek, ioeric Reviewed By: ioeric Subscribers: malcolm.parsons, mgorny, cfe-commits Differential Revision: https://reviews.llvm.org/D43764 Patch by Jeremy Demeule. llvm-svn: 329813
* Revert "[llvm-mca][CMake] Remove unused libraries from set LLVM_LINK_COMPONENTS"Andrea Di Biagio2018-04-111-0/+6
| | | | | | It caused a buildbot failure (clang-ppc64le-linux-multistage - build #6424) llvm-svn: 329812
* Revert "[AMDGPU] Ensure there are enough registers for wave dispatch"Tim Renouf2018-04-112-31/+0
| | | | | | | | | This reverts 329808. That change caused a report of a failure in test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir that I didn't see. I suspect it is an expensive-check-only error. Change-Id: I8133f26f15e7d5ec2b09c687c12cd70e918461b0 llvm-svn: 329811
* [Driver] Don't forward -m[no-]unaligned-access options to GCC when ↵Chad Rosier2018-04-112-0/+13
| | | | | | | | assembling/linking Differential Revision: https://reviews.llvm.org/D45092 llvm-svn: 329810
* [AArch64][AsmParser] Split index parsing from vector list.Sander de Smalen2018-04-111-27/+23
| | | | | | | | | | | | | | | | | | | | Summary: Place parsing of a vector index into a separate function to reduce duplication, since the code is duplicated in both the parsing of a Neon vector register operand and a Neon vector list. This is patch [2/6] in a series to add assembler/disassembler support for SVE's contiguous ST1 (scalar+imm) instructions. Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45428 llvm-svn: 329809
* [AMDGPU] Ensure there are enough registers for wave dispatchTim Renouf2018-04-112-0/+31
| | | | | | | | | | | | | | Summary: This fixes the number of SGPRs and VGPRs in the *_RSRC1 register to allow for registers set up in wave dispatch, even if those registers are not used in the shader. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45503 Change-Id: I6575f0e0d2a528d1319d0b289f0ebe4510fa5771 llvm-svn: 329808
* [llvm-mca][CMake] Remove unused libraries from set LLVM_LINK_COMPONENTS.Andrea Di Biagio2018-04-111-6/+0
| | | | llvm-svn: 329807
* [X86] Add variable shuffle schedule classesSimon Pilgrim2018-04-1117-181/+117
| | | | | | | | | | | | | | Split variable index shuffles from immediate index shuffles WriteFVarShuffle - variable 'in-lane' shuffles (VPERMILPS/VPERMIL2PS etc.) WriteVarShuffle - variable 'in-lane' shuffles (PSHUFB/VPPERM etc.) WriteFVarShuffle256 - variable 'cross-lane' shuffles (VPERMPS etc.) WriteVarShuffle256 - variable 'cross-lane' shuffles (VPERMD etc.) Differential Revision: https://reviews.llvm.org/D45404 llvm-svn: 329806
* [AArch64] Add test case for r329797Francis Visoiu Mistrih2018-04-111-0/+17
| | | | | | Forgot to add a test case in the previous commit. llvm-svn: 329805
* [Sema] Fix built-in decrement operator overload resolutionJan Korous2018-04-112-5/+21
| | | | | | | | | | | | | | | | | C++ [over.built] p4: "For every pair (T, VQ), where T is an arithmetic type other than bool, and VQ is either volatile or empty, there exist candidate operator functions of the form VQ T& operator--(VQ T&); T operator--(VQ T&, int); " The bool type is in position LastPromotedIntegralType in BuiltinOperatorOverloadBuilder::getArithmeticType::ArithmeticTypes, but addPlusPlusMinusMinusArithmeticOverloads() was expecting it at position 0. Differential Revision: https://reviews.llvm.org/D44988 rdar://problem/34255516 llvm-svn: 329804
* llgs: Send "rich" errors in response to vAttach packetsPavel Labath2018-04-114-11/+29
| | | | | | | | | | | | | | | | | There are plenty of ways attaching can go wrong. Having the server report the exact error means we can give better feedback to the user. (This patch does not do the second part, it only makes sure the information is sent from the server.) Triggering all possible error conditions in a test would prove challenging, but there is one error that is very easy to reproduce (attempting to attach while debugging), so I write a test based on that. The test immediately exposed a bug where the m_send_error_strings field was being used uninitialized (so it was sometimes true from the get-go), so I fix that as well. llvm-svn: 329803
* [X86][SSE] Tweak cmpps schedule test so that it works properly with just sse1Simon Pilgrim2018-04-111-4/+5
| | | | | | movhps/movlps test are still broken so we can't disable sse2 yet llvm-svn: 329802
* [AMDGPU][MC][GFX9] Added v_screen_partition_4se_b32Dmitry Preobrazhensky2018-04-119-5/+85
| | | | | | | | | See bug 36845: https://bugs.llvm.org/show_bug.cgi?id=36845 Differential Revision: https://reviews.llvm.org/D45443 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 329801
* [AArch64] Fix regression after r329691Francis Visoiu Mistrih2018-04-111-1/+1
| | | | | | | | | | | | In r329691, we would choose FP even if the offset wouldn't fit, just because the offset is smaller than the one from BP. This made many accesses through FP need to scavenge a register, which resulted in slower and bigger code for no good reason. This patch now always picks the offset that fits first, even if FP is preferred. llvm-svn: 329797
* [llvm-mca] Minor code cleanup. NFCAndrea Di Biagio2018-04-115-26/+19
| | | | llvm-svn: 329796
* [PowerPC] Option for secure plt modeStrahinja Petrovic2018-04-114-0/+22
| | | | | | | | | This patch enables option for secure plt mode in clang (-msecure-plt). Differential Revision: https://reviews.llvm.org/D44921 llvm-svn: 329795
* [llvm-mca] Renamed BackendStatistics to RetireControlUnitStatistics.Andrea Di Biagio2018-04-116-32/+87
| | | | | | Also, removed flag -verbose in favor of flag -retire-stats. llvm-svn: 329794
* [llvm-mca] Move the logic that prints scheduler statistics from ↵Andrea Di Biagio2018-04-119-131/+244
| | | | | | | | BackendStatistics to its own view. Added flag -scheduler-stats to print scheduler related statistics. llvm-svn: 329792
* Eliminate a bitwise 'not' op of 'not' min/max by inverting the min/max.Artur Gainullin2018-04-113-4/+177
| | | | | | | | | | | | | | | | | | | | | Bitwise 'not' of the min/max could be eliminated in the pattern: %notx = xor i32 %x, -1 %cmp1 = icmp sgt[slt/ugt/ult] i32 %notx, %y %smax = select i1 %cmp1, i32 %notx, i32 %y %res = xor i32 %smax, -1 https://rise4fun.com/Alive/lCN Reviewers: spatel Reviewed by: spatel Subscribers: a.elovikov, llvm-commits Differential Revision: https://reviews.llvm.org/D45317 llvm-svn: 329791
* [clang-tidy] fix buildbots from hicpp-signed-bitwiseJonas Toth2018-04-111-5/+10
| | | | | | | The applied patch to diagnose assignment operators introduced breakage on some architectures. This patch tries to rectify that. llvm-svn: 329790
* [clang-tidy] add missing assignment operations in hicpp-signed-bitwiseJonas Toth2018-04-114-38/+66
| | | | | | | | | | | | | This patch resolves the bug https://bugs.llvm.org/show_bug.cgi?id=36963. - implement missing assignment operators for hicpp-signed-bitwise - mention fix in release notes Reviewers: aaron.ballman, hokein, alexfh Differential: https://reviews.llvm.org/D45414 llvm-svn: 329789
* [ARM] FP16 VSEL codegenSjoerd Meijer2018-04-112-16/+152
| | | | | | | | | | | | | This is a follow up of rL327695 to instruction select more variants of VSELGT and VSELGE, for which it is necessary to custom lower SELECT. More work is required in this area, which will be addressed soon: - more variants need to be regression tested, but this depends on the next point. - first LowerConstantFP need to be adjusted for fp16 values. Differential Revision: https://reviews.llvm.org/D45205 llvm-svn: 329788
* [ELF] - Reorder local symbols.George Rimar2018-04-114-16/+45
| | | | | | | | | | | This fixes PR36716 (https://bugs.llvm.org/show_bug.cgi?id=36716), Patch sorts local symbols to match the following order: file1, local1, hidden1, file2, local2, hidden2 ... Differential revision: https://reviews.llvm.org/D45325 llvm-svn: 329787
* [Tooling] Correct the "-std" compile command option.Haojian Wu2018-04-112-4/+4
| | | | | | | | | | | | | | | Summary: "-std c++11" is not valid in compiler, we have to use "-std=c++11". Test in vscode with this patch, code completion for header works as expected. Reviewers: sammccall Subscribers: cfe-commits, klimek Differential Revision: https://reviews.llvm.org/D45512 llvm-svn: 329786
* [ELF] - Simplify. NFC.George Rimar2018-04-111-7/+4
| | | | llvm-svn: 329785
* [Tooling] Optimize memory usage in InMemoryToolResults.Haojian Wu2018-04-113-6/+27
| | | | | | | | | | | | | | Avoid storing duplicated "std::string"s. clangd's global-symbol-builder takes 20+GB memory running across LLVM repository. With this patch, the used memory is ~10GB (running on 48 threads, most of meory are AST-related). Subscribers: klimek, cfe-commits Differential Revision: https://reviews.llvm.org/D45479 llvm-svn: 329784
* [Build][NFC] Split off libpfm detection to a separate module.Clement Courbet2018-04-112-11/+24
| | | | llvm-svn: 329783
* [AArch64][AsmParser] Unify code for parsing Neon/SVE vectors.Sander de Smalen2018-04-116-151/+165
| | | | | | | | | | | | | | | | | | | | | | Summary: Merged 'tryMatchVectorRegister' (specific to Neon) and 'tryParseSVERegister' into a single 'tryParseVectorRegister' function, and created a generic 'parseVectorKind()' function that returns the #Elements and ElementWidth of a vector suffix. This reduces the duplication of this functionality between two the vector implementations. This is patch [1/6] in a series to add assembler/disassembler support for SVE's contiguous ST1 (scalar+imm) instructions. Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: fhahn Subscribers: tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45427 llvm-svn: 329782
* [llvm-exegesis] Add a flag to disable libpfm even if present.Clement Courbet2018-04-115-11/+18
| | | | | | | | | | | | Summary: Fixes PR37053. Reviewers: uabelho, gchatelet Subscribers: mgorny, tschuett, llvm-commits Differential Revision: https://reviews.llvm.org/D45436 llvm-svn: 329781
* [Analyzer] SValBuilder Comparison Rearrangement (with Restrictions and ↵Adam Balogh2018-04-116-12/+1223
| | | | | | | | | | | | | | | | Analyzer Option) Since the range-based constraint manager (default) is weak in handling comparisons where symbols are on both sides it is wise to rearrange them to have symbols only on the left side. Thus e.g. A + n >= B + m becomes A - B >= m - n which enables the constraint manager to store a range m - n .. MAX_VALUE for the symbolic expression A - B. This can be used later to check whether e.g. A + k == B + l can be true, which is also rearranged to A - B == l - k so the constraint manager can check whether l - k is in the range (thus greater than or equal to m - n). The restriction in this version is the the rearrangement happens only if both the symbols and the concrete integers are within the range [min/4 .. max/4] where min and max are the minimal and maximal values of their type. The rearrangement is not enabled by default. It has to be enabled by using -analyzer-config aggressive-relational-comparison-simplification=true. Co-author of this patch is Artem Dergachev (NoQ). Differential Revision: https://reviews.llvm.org/D41938 llvm-svn: 329780
* Adding fuzzer flags support to OpenBSD driverDean Michael Berris2018-04-111-1/+4
| | | | | | | | | | | | | | Summary: - Following-up the sanitizer's part commit https://reviews.llvm.org/rCRT329631, we enable fuzzer flags. Reviewers: brad, thakis, dberris Reviewed By: dberris Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D44878 llvm-svn: 329779
* [CMake][runtimes] Process common options in runtimes buildPetr Hosek2018-04-111-0/+7
| | | | | | | | | | | This was removed in D39932 but turned out this is actually needed because runtimes such as compiler-rt and libc++ rely on common options processing for setting certain flags such as -ffunction-sections and -fdata-sections. Differential Revision: https://reviews.llvm.org/D45507 llvm-svn: 329778
* [X86] Fix typo in intrinsic header file __mask16->__mmask16 from r329775.Craig Topper2018-04-111-2/+2
| | | | llvm-svn: 329777
* [XRay][compiler-rt] Fix osx-based buildsDean Michael Berris2018-04-111-11/+22
| | | | | | This is a follow-up to D45474. llvm-svn: 329776
* [X86] Replace 512-bit masked pmaddubsw and pmaddwd intrinsic with unmasked ↵Craig Topper2018-04-113-40/+33
| | | | | | | | | | intrinsic and a select. This makes it consistent with the 128/256-bit functions. Someday maybe we'll have all the masking moved to selects. llvm-svn: 329775
* [X86] Remove 128/256-bit masked pmaddubsw and pmaddwd intrinsics. Replace ↵Craig Topper2018-04-117-84/+201
| | | | | | | | 512-bit masked intrinsic with unmasked intrinsic and a select. The 128/256-bit versions were no longer used by clang. It uses the legacy SSE/AVX2 version and a select. The 512-bit was changed to the same for consistency. llvm-svn: 329774
* [XRay][clang] Only enable test for supported platformsDean Michael Berris2018-04-111-0/+2
| | | | | | This is a follow-up to D45474. llvm-svn: 329773
* [XRay][clang+compiler-rt] Support build-time mode selectionDean Michael Berris2018-04-117-17/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch implements the `-fxray-modes=` flag which allows users building with XRay instrumentation to decide which modes to pre-package into the binary being linked. The default is the status quo, which will link all the available modes. For this to work we're also breaking apart the mode implementations (xray-fdr and xray-basic) from the main xray runtime. This gives more granular control of which modes are pre-packaged, and picked from clang's invocation. This fixes llvm.org/PR37066. Note that in the future, we may change the default for clang to only contain the profiling implementation under development in D44620, when that implementation is ready. Reviewers: echristo, eizan, chandlerc Reviewed By: echristo Subscribers: mgorny, mgrang, cfe-commits, llvm-commits Differential Revision: https://reviews.llvm.org/D45474 llvm-svn: 329772
* [X86] In X86FlagsCopyLowering, when rewriting a memory setcc we need to emit ↵Craig Topper2018-04-112-5/+23
| | | | | | | | | | an explicit MOV8mr instruction. Previously the code only knew how to handle setcc to a register. This should fix a crash in the chromium build. llvm-svn: 329771
* [libcxx] Set ABI version 2 as default for FuchsiaPetr Hosek2018-04-111-1/+5
| | | | | | | | | | This avoids the need for a custom generated config file which is desired because the custom config files differs per-target which means we cannot reuse headers across different targets. Differential Revision: https://reviews.llvm.org/D45304 llvm-svn: 329770
* [X86] Switch a test from grep to FileCheck. NFCCraig Topper2018-04-111-1/+11
| | | | llvm-svn: 329769
* Simplification of libcall like printf->puts must check for RtLibUseGOT metadata.Sriraman Tallam2018-04-102-0/+30
| | | | | | | | | | With -fno-plt, for example, calls to printf when getting converted to puts still use the PLT. This patch checks for the metadata "RtLibUseGOT" and annotates the declaration with the right attributes. Differential Revision: https://reviews.llvm.org/D45180 llvm-svn: 329768
* Use contains_lower() instead of find_lower() != StringRef::npos. NFC.Rui Ueyama2018-04-101-6/+6
| | | | llvm-svn: 329767
* [AST] Fix some Clang-tidy modernize-use-auto and Include What You Use ↵Eugene Zelenko2018-04-105-143/+239
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 329766
* GOTPCREL references must always use RIP.Sriraman Tallam2018-04-103-3/+15
| | | | | | | | With -fno-plt, global value references can use GOTPCREL and RIP must be used. Differential Revision: https://reviews.llvm.org/D45460 llvm-svn: 329765
* AMDGPU: enable 128-bit for local addr space under an optionMarek Olsak2018-04-1013-28/+35
| | | | | | | | | | | | | | | | | | | Author: Samuel Pitoiset ds_read_b128 and ds_write_b128 have been recently enabled under the amdgpu-ds128 option because the performance benefit is unclear. Though, using 128-bit loads/stores for the local address space appears to introduce regressions in tessellation shaders. Not sure what is broken, but as ds_read_b128/ds_write_b128 are not enabled by default, just introduce a global option and enable 128-bit only if requested (until it's fixed/used correctly). v2: - fix regressions in merge-stores.ll and multiple_tails.ll Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105464 llvm-svn: 329764
* Disable flaky tests till they get fixed.Galina Kistanova2018-04-102-1/+2
| | | | llvm-svn: 329763
* Introduce a new builtin, __builtin_dump_struct, that is useful for dumping ↵Aaron Ballman2018-04-105-0/+591
| | | | | | | | structure contents at runtime in circumstances where debuggers may not be easily available (such as in kernel work). Patch by Paul Semel. llvm-svn: 329762
* [AArch64][Falkor] Fix bug in Falkor HWPF collision avoidance pass.Geoff Berry2018-04-102-0/+43
| | | | | | | | | | | | | | | | Summary: When inserting MOVs to avoid Falkor HWPF collisions, the non-base register operand of load instructions (e.g. a register offset) was not being considered live, so it could potentially have been used as a scratch register, clobbering the actual offset value. Reviewers: mcrosier Subscribers: rengolin, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45502 llvm-svn: 329761
* Revert "Handle the default case"Petr Hosek2018-04-101-2/+0
| | | | | | This reverts commit r329758. llvm-svn: 329760
OpenPOWER on IntegriCloud