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* Add a framework for eliminating instructions that produces undemanded bits.Nate Begeman2006-02-033-11/+96
| | | | llvm-svn: 25945
* add a noteChris Lattner2006-02-031-0/+2
| | | | llvm-svn: 25944
* another case Nate came up withChris Lattner2006-02-031-0/+3
| | | | llvm-svn: 25943
* add a noteChris Lattner2006-02-031-0/+4
| | | | llvm-svn: 25942
* remove some #ifdef'd out code, which should properly be in the dag combiner ↵Chris Lattner2006-02-031-30/+0
| | | | | | anyway. llvm-svn: 25941
* remove an old commentChris Lattner2006-02-031-3/+2
| | | | llvm-svn: 25940
* Remove the X86PeepholeOptimizerPass, a truly horrible old hack that is nowChris Lattner2006-02-033-187/+0
| | | | | | obsolete. yaay :) llvm-svn: 25939
* When rewriting frame instructions, emit the appropriate small-immediateChris Lattner2006-02-031-13/+21
| | | | | | instruction when possible. llvm-svn: 25938
* node predicates add to the complexity of a pattern. This ensures that theChris Lattner2006-02-031-2/+9
| | | | | | | X86 backend attempts to match small-immediate versions of instructions before the full size immediate versions. llvm-svn: 25937
* Teach sparc to fold loads/stores into copies.Chris Lattner2006-02-032-37/+47
| | | | | | | Remove the dead getRegClassForType method minor formating changes. llvm-svn: 25936
* remove dead fnChris Lattner2006-02-031-11/+0
| | | | llvm-svn: 25935
* Add common code for reassociating ops in the dag combinerNate Begeman2006-02-031-50/+55
| | | | llvm-svn: 25934
* Added a (store (op (load ...) ...) ...) folding test case.Evan Cheng2006-02-031-0/+14
| | | | llvm-svn: 25933
* Implement isLoadFromStackSlot and isStoreToStackSlotChris Lattner2006-02-032-0/+52
| | | | llvm-svn: 25932
* (store (op (load ...))) folding problem. In the generated matching code,Evan Cheng2006-02-031-23/+30
| | | | | | | | | | | | | | | Chain is initially set to the chain operand of store node, when it reaches load, if it matches the load then Chain is set to the chain operand of the load. However, if the matching code that follows this fails, isel moves on to the next pattern but it does not restore Chain to the chain operand of the store. So when it tries to match the next store / op / load pattern it would fail on the Chain == load.getOperand(0) test. The solution is for each chain operand to get a unique name. e.g. Chain10. llvm-svn: 25931
* remove some target-indep and implemented notesChris Lattner2006-02-032-57/+11
| | | | llvm-svn: 25930
* target independent notesChris Lattner2006-02-031-0/+67
| | | | llvm-svn: 25929
* Flesh out a couple of the items in the READMENate Begeman2006-02-031-14/+41
| | | | llvm-svn: 25928
* Fix VC++ compilation error caused by using a std::map iterator variable to ↵Jeff Cohen2006-02-031-1/+1
| | | | | | | | receive a std::multimap iterator value. For some reason, GCC doesn't have a problem with this. llvm-svn: 25927
* Remove move copies and dead stuff by not clobbering the result reg of a noop ↵Chris Lattner2006-02-031-12/+21
| | | | | | copy. llvm-svn: 25926
* isStoreToStackSlotAndrew Lenharth2006-02-033-3/+20
| | | | llvm-svn: 25925
* Simplify some codeChris Lattner2006-02-031-45/+40
| | | | llvm-svn: 25924
* the X86 backend no longer needs to delete its own noop copiesChris Lattner2006-02-031-10/+2
| | | | llvm-svn: 25923
* Add code that checks for noop copies, which triggers when either:Chris Lattner2006-02-031-0/+13
| | | | | | | | | | | | 1. a target doesn't know how to fold load/stores into copies, or 2. the spiller rewrites the input to a copy to the same register as the dest instead of to the reloaded reg. This will be moved/improved in the near future, but allows elimination of some ancient x86 hacks. This eliminates 92 copies from SMG2000 on X86 and 163 copies from 252.eon. llvm-svn: 25922
* Add a noteChris Lattner2006-02-031-0/+5
| | | | llvm-svn: 25921
* Added case HANDLENODE to getOperationName().Evan Cheng2006-02-031-0/+1
| | | | llvm-svn: 25920
* Physregs may hold multiple stack slot values at the same time. Keep trackChris Lattner2006-02-031-37/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of this, and use it to our advantage (bwahahah). This allows us to eliminate another 60 instructions from smg2000 on PPC (probably significantly more on X86). A common old-new diff looks like this: stw r2, 3304(r1) - lwz r2, 3192(r1) stw r2, 3300(r1) - lwz r2, 3192(r1) stw r2, 3296(r1) - lwz r2, 3192(r1) stw r2, 3200(r1) - lwz r2, 3192(r1) stw r2, 3196(r1) - lwz r2, 3192(r1) + or r2, r2, r2 stw r2, 3188(r1) and - lwz r31, 604(r1) - lwz r13, 604(r1) - lwz r14, 604(r1) - lwz r15, 604(r1) - lwz r16, 604(r1) - lwz r30, 604(r1) + or r31, r30, r30 + or r13, r30, r30 + or r14, r30, r30 + or r15, r30, r30 + or r16, r30, r30 + or r30, r30, r30 Removal of the R = R copies is coming next... llvm-svn: 25919
* update a noteChris Lattner2006-02-021-0/+3
| | | | llvm-svn: 25918
* Fix a deficiency in the spiller that Evan noticed. In particular, considerChris Lattner2006-02-021-1/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this code: store [stack slot #0], R10 = add R14, [stack slot #0] The spiller didn't know that the store made the value of [stackslot#0] available in R10 *IF* the store came from a copy instruction with the store folded into it. This patch teaches VirtRegMap to look at these stores and recognize the values they make available. In one case Evan provided, this code: divsd %XMM0, %XMM1 movsd %XMM1, QWORD PTR [%ESP + 40] 1) movsd QWORD PTR [%ESP + 48], %XMM1 2) movsd %XMM1, QWORD PTR [%ESP + 48] addsd %XMM1, %XMM0 3) movsd QWORD PTR [%ESP + 48], %XMM1 movsd QWORD PTR [%ESP + 4], %XMM0 turns into: divsd %XMM0, %XMM1 movsd %XMM1, QWORD PTR [%ESP + 40] addsd %XMM1, %XMM0 3) movsd QWORD PTR [%ESP + 48], %XMM1 movsd QWORD PTR [%ESP + 4], %XMM0 In this case, instruction #2 was removed because of the value made available by #1, and inst #1 was later deleted because it is now never used before the stack slot is redefined by #3. This occurs here and there in a lot of code with high spilling, on PPC most of the removed loads/stores are LSU-reject-causing loads, which is nice. On X86, things are much better (because it spills more), where we nuke about 1% of the instructions from SMG2000 and several hundred from eon. More improvements to come... llvm-svn: 25917
* add 64b gpr store to the possible list of isStoreToStackSlot opcodes.Nate Begeman2006-02-021-1/+1
| | | | llvm-svn: 25916
* fix operand numbersChris Lattner2006-02-021-4/+4
| | | | llvm-svn: 25915
* implement isStoreToStackSlot for PPCChris Lattner2006-02-022-1/+19
| | | | llvm-svn: 25914
* Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far ↵Chris Lattner2006-02-0213-98/+98
| | | | | | more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913
* Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,Chris Lattner2006-02-022-18/+18
| | | | | | | a far more logical place. Other methods should also be moved if anyone is interested. :) llvm-svn: 25912
* implement isStoreToStackSlotChris Lattner2006-02-021-0/+23
| | | | llvm-svn: 25911
* add a methodChris Lattner2006-02-021-0/+1
| | | | llvm-svn: 25910
* add a new isStoreToStackSlot methodChris Lattner2006-02-021-1/+10
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* more notesChris Lattner2006-02-021-0/+52
| | | | llvm-svn: 25908
* add a note, I have no idea how important this is.Chris Lattner2006-02-021-0/+24
| | | | llvm-svn: 25907
* %fcc is not an alias for %fcc0Chris Lattner2006-02-021-4/+4
| | | | llvm-svn: 25906
* correct an opcodeChris Lattner2006-02-021-2/+2
| | | | llvm-svn: 25905
* new exampleChris Lattner2006-02-021-0/+19
| | | | llvm-svn: 25903
* Update the READMENate Begeman2006-02-021-19/+3
| | | | llvm-svn: 25902
* Turn any_extend nodes into zero_extend nodes when it allows us to remove anChris Lattner2006-02-021-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and instruction. This allows us to compile stuff like this: bool %X(int %X) { %Y = add int %X, 14 %Z = setne int %Y, 12345 ret bool %Z } to this: _X: cmpl $12331, 4(%esp) setne %al movzbl %al, %eax ret instead of this: _X: cmpl $12331, 4(%esp) setne %al movzbl %al, %eax andl $1, %eax ret This occurs quite a bit with the X86 backend. For example, 25 times in lambda, 30 times in 177.mesa, 14 times in galgel, 70 times in fma3d, 25 times in vpr, several hundred times in gcc, ~45 times in crafty, ~60 times in parser, ~140 times in eon, 110 times in perlbmk, 55 on gap, 16 times on bzip2, 14 times on twolf, and 1-2 times in many other SPEC2K programs. llvm-svn: 25901
* Implement MaskedValueIsZero for ANY_EXTEND nodesChris Lattner2006-02-021-0/+5
| | | | llvm-svn: 25900
* implemented, testcase here: test/Regression/CodeGen/X86/compare-add.llChris Lattner2006-02-021-10/+0
| | | | llvm-svn: 25899
* add two dag combines:Chris Lattner2006-02-021-8/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (C1-X) == C2 --> X == C1-C2 (X+C1) == C2 --> X == C2-C1 This allows us to compile this: bool %X(int %X) { %Y = add int %X, 14 %Z = setne int %Y, 12345 ret bool %Z } into this: _X: cmpl $12331, 4(%esp) setne %al movzbl %al, %eax andl $1, %eax ret not this: _X: movl $14, %eax addl 4(%esp), %eax cmpl $12345, %eax setne %al movzbl %al, %eax andl $1, %eax ret Testcase here: Regression/CodeGen/X86/compare-add.ll nukage of the and coming up next. llvm-svn: 25898
* new testcaseChris Lattner2006-02-021-0/+8
| | | | llvm-svn: 25897
* Update.Evan Cheng2006-02-021-12/+5
| | | | llvm-svn: 25896
* make -debug output less newlineyChris Lattner2006-02-021-2/+1
| | | | llvm-svn: 25895
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