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* AMDGPU/GlobalISel: Legalize more odd sized loadsMatt Arsenault2020-01-045-307/+43
| | | | | The attempts to widen sufficently aligned, odd sized loads wasn't consistently applied.
* AMDGPU/GlobalISel: Assume vcc phis for any vcc inputMatt Arsenault2020-01-043-86/+69
| | | | | | | This produces more intelligible looking results, more comparabble to the DAG output in the simplest cases. This is probably wrong in complex control flow, but RegBankSelect doesn't attempt analyzing if this is on a masked path for selecting the bank yet.
* [Pass Registration] XFAIL load_extension.ll test on macOS.Florian Hahn2020-01-041-0/+3
| | | | | | | | | | | This test fails on macOS, causing the following bots to fail http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental/7438/ http://green.lab.llvm.org/green/job/clang-stage1-RA/5034/ Error: Error opening 'build/./lib/libBye.dylib': dlopen(build/./lib/libBye.dylib, 9): image not found -load request ignored.
* AMDGPU/GlobalISel: Implement applyMappingImpl less incorrectlyMatt Arsenault2020-01-041-13/+23
| | | | | | | | | | | We're checking the current register bank of the registers in the instruction, but the mapping may have inserted cross bank copies and is expecting to replace the registers. We mostly get away with this currently, because VGPR->SGPR copies are illegal, and we assume this won't happen. In a future change, we'll start relying on more cross register bank copies being inserted, and this starts to break down.
* [cmake] Remove install from add_llvm_example_library.Florian Hahn2020-01-041-4/+3
| | | | | This should fix http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast/builds/30086
* Re-apply "[Examples] Add IRTransformations directory to examples."Florian Hahn2020-01-0417-0/+1004
| | | | | | This reverts commit 19fd8925a4afe6efd248688cce06aceff50efe0c. Should include a fix for PR44197.
* NFC: Fix trivial typos in commentsKazuaki Ishizaki2020-01-0468-80/+80
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* [AMDGPU] need to insert wait between the scalar load and vector store to the ↵alex-t2020-01-042-0/+50
| | | | | | | | | | same address to avoid WAR conflict. Reviewers: rampitec, vpykhtin, nhaehnle Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D71934
* [NFCI][InstCombine] Refactor 'sink negation into select if that folds one ↵Roman Lebedev2020-01-041-40/+35
| | | | | | | | | | hand of select to 0' fold I would think it's better than having two practically identical folds next to eachother, but then generalization isn't all that pretty due to the fact that we need to produce different `sub` each time.. This change is no-functional-changes-intended refactoring.
* [InstCombine] Sink sub into hands of select if one hand becomes zero. Part 2 ↵Roman Lebedev2020-01-043-22/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | (PR44426) This decreases use count of %Op0, makes one hand of select to be 0, and possibly exposes further folding potential. Name: sub %Op0, (select %Cond, %Op0, %FalseVal) -> select %Cond, 0, (sub %Op0, %FalseVal) %Op0 = %TrueVal %o = select i1 %Cond, i8 %Op0, i8 %FalseVal %r = sub i8 %Op0, %o => %n = sub i8 %Op0, %FalseVal %r = select i1 %Cond, i8 0, i8 %n Name: sub %Op0, (select %Cond, %TrueVal, %Op0) -> select %Cond, (sub %Op0, %TrueVal), 0 %Op0 = %FalseVal %o = select i1 %Cond, i8 %TrueVal, i8 %Op0 %r = sub i8 %Op0, %o => %n = sub i8 %Op0, %TrueVal %r = select i1 %Cond, i8 %n, i8 0 https://rise4fun.com/Alive/aHRt https://bugs.llvm.org/show_bug.cgi?id=44426
* [NFC][InstCombine] 'subtract from one hands of select' pattern tests (PR44426)Roman Lebedev2020-01-042-11/+78
| | | | https://bugs.llvm.org/show_bug.cgi?id=44426
* [InstCombine] Sink sub into hands of select if one hand becomes zero (PR44426)Roman Lebedev2020-01-043-22/+43
| | | | | | | | | | | | | | | | | | | | | | | | | This decreases use count of %Op1, makes one hand of select to be 0, and possibly exposes further folding potential. Name: sub (select %Cond, %Op1, %FalseVal), %Op1 -> select %Cond, 0, (sub %FalseVal, %Op1) %Op1 = %TrueVal %o = select i1 %Cond, i8 %Op1, i8 %FalseVal %r = sub i8 %o, %Op1 => %n = sub i8 %FalseVal, %Op1 %r = select i1 %Cond, i8 0, i8 %n Name: sub (select %Cond, %TrueVal, %Op1), %Op1 -> select %Cond, (sub %TrueVal, %Op1), 0 %Op1 = %FalseVal %o = select i1 %Cond, i8 %TrueVal, i8 %Op1 %r = sub i8 %o, %Op1 => %n = sub i8 %TrueVal, %Op1 %r = select i1 %Cond, i8 %n, i8 0 https://rise4fun.com/Alive/avL https://bugs.llvm.org/show_bug.cgi?id=44426
* [NFC][InstCombine] 'subtract of one hands of select' pattern tests (PR44426)Roman Lebedev2020-01-041-0/+89
| | | | https://bugs.llvm.org/show_bug.cgi?id=44426
* [Transforms][GlobalSRA] huge array causes long compilation time and huge ↵Alexey Lapshin2020-01-042-65/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | memory usage. Summary: For artificial cases (huge array, few usages), Global SRA optimization creates a lot of redundant data. It creates an instance of GlobalVariable for each array element. For huge array, that means huge compilation time and huge memory usage. Following example compiles for 10 minutes and requires 40GB of memory. namespace { char LargeBuffer[64 * 1024 * 1024]; } int main ( void ) { LargeBuffer[0] = 0; printf("\n "); return LargeBuffer[0] == 0; } The fix is to avoid Global SRA for large arrays. Reviewers: craig.topper, rnk, efriedma, fhahn Reviewed By: rnk Subscribers: xbolva00, lebedev.ri, lkail, merge_guards_bot, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71993
* [TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits ↵Simon Pilgrim2020-01-0412-150/+151
| | | | | | | | | | | | | | for ISD::EXTRACT_VECTOR_ELT (REAPPLIED) This patch attempts to peek through vectors based on the demanded bits/elt of a particular ISD::EXTRACT_VECTOR_ELT node, allowing us to avoid dependencies on ops that have no impact on the extract. In particular this helps remove some unnecessary scalar->vector->scalar patterns. The wasm shift patterns are annoying - @tlively has indicated that the wasm vector shift codegen are to be refactored in the near-term and isn't considered a major issue. Reapplied after reversion at rL368660 due to PR42982 which was fixed at rGca7fdd41bda0. Differential Revision: https://reviews.llvm.org/D65887
* [LLD] [COFF] Don't error out on duplicate absolute symbols with the same valueMartin Storsjö2020-01-044-3/+31
| | | | | | | | | Both MS link.exe and GNU ld.bfd handle it this way; one can have multiple object files defining the same absolute symbols, as long as it defines it to the same value. But if there are multiple absolute symbols with differing values, it is treated as an error. Differential Revision: https://reviews.llvm.org/D71981
* [X86] Update MaxIndex test in x86-cmov-converter.ll to return the index and ↵Craig Topper2020-01-031-16/+10
| | | | | | | | | | | | not use the index to look up the array after the loop. This represents a more realistic version of the code being tested. The cmov converter doesn't look at the code after the loop so it doesn't matter for what's being tested. But as noted in this twitter thread https://twitter.com/trav_downs/status/1213311159413161987 gcc can turn the previous MaxIndex code into the MaxValue code. So returning the index makes it a distinct case.
* [OpenMP] NFC: Fix trivial typos in commentsKelvin Li2020-01-0325-36/+36
| | | | | | Submitted by: kiszk Differential Revision: https://reviews.llvm.org/D72171
* [gn build] Port 5d304d68dd5LLVM GN Syncbot2020-01-041-1/+0
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* Revert "[gicombiner] Add GIMatchTree and use it for the code generation"Daniel Sanders2020-01-0313-1928/+17
| | | | | | | | | All the windows bots are failing match-tree.td and there's no obvious cause that I can see. It's not just the %p formatting problem. My best guess is that there's an ordering issue too but I'll need further information to figure that out. Revert while I'm investigating. This reverts commit 64f1bb5cd2c6d69af7c74ec68840029603560238 and 77d4b5f5feff663e70b347516cc4c77fa5cd2a20
* [lldb/Command] Add --force option for `watchpoint delete` commandMed Ismail Bennani2020-01-043-39/+94
| | | | | | | | | | | | | | Currently, there is no option to delete all the watchpoint without LLDB asking for a confirmation. Besides making the watchpoint delete command homogeneous with the breakpoint delete command, this option could also become handy to trigger automated watchpoint deletion i.e. using breakpoint actions. rdar://42560586 Differential Revision: https://reviews.llvm.org/D72096 Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
* [X86] Autogenerate complete checks. NFCCraig Topper2020-01-033-1061/+5484
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* [Remarks] Warn if a remark file is not found when processing static archivesFrancis Visoiu Mistrih2020-01-036-3/+82
| | | | | | | | | | | Static archives contain object files which contain sections pointing to external remark files. When static archives are shipped without the remark files, dsymutil shouldn't generate an error. Instead, generate a warning to inform the user that remarks for that library won't be available in the .dSYM.
* [UserExpression] Clean up `return` after `else`.Davide Italiano2020-01-031-4/+3
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* [gicombiner] Correct 64f1bb5cd2c to account for MSVC's %p formatDaniel Sanders2020-01-031-20/+20
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* [Diagnostic] Add test for previous b4b904e19bb356724b2c6aea0199ce05c6f15cdbTyker2020-01-041-0/+3
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* [gn build] Port 64f1bb5cd2cLLVM GN Syncbot2020-01-041-0/+1
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* [gicombiner] Add GIMatchTree and use it for the code generationDaniel Sanders2020-01-0313-17/+1928
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: GIMatchTree's job is to build a decision tree by zipping all the GIMatchDag's together. Each DAG is added to the tree builder as a leaf and partitioners are used to subdivide each node until there are no more partitioners to apply. At this point, the code generator is responsible for testing any untested predicates and following any unvisited traversals (there shouldn't be any of the latter as the getVRegDef partitioner handles them all). Note that the leaves don't always fit into partitions cleanly and the partitions may overlap as a result. This is resolved by cloning the leaf into every partition it belongs to. One example of this is a rule that can match one of N opcodes. The leaf for this rule would end up in N partitions when processed by the opcode partitioner. A similar example is the getVRegDef partitioner where having rules (add $a, $b), and (add ($a, $b), $c) will result in the former being in the partition for successfully following the vreg-def and failing to do so as it doesn't care which happens. Depends on D69151 Reviewers: bogner, volkan Reviewed By: volkan Subscribers: lkail, mgorny, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69152
* Add missing mlir-headers target and add tablegen'd deps to it.Stella Laurenzo2020-01-031-0/+5
| | | | | | | | | | | | | Summary: Prior to this, "ninja install-mlir-headers" failed with an error indicating the missing target. Verified that from a clean build, the installed headers include generated files. Subscribers: mgorny, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72045
* [fuchsia] Enable Clang Static AnalyzerGabor Horvath2020-01-032-2/+2
| | | | Differential Revision: https://reviews.llvm.org/D72188
* [AMDGPU] Revert scheduling to reduce spillingStanislav Mekhanoshin2020-01-031-2/+11
| | | | | | | | | | We can revert region schedule if new schedule decreases occupancy. However, if we already have only one wave we would accept any new schedule even if it blows up register pressure. Such schedule may result in quite heavy spilling which can be avoided if we reject this new schedule. Differential Revision: https://reviews.llvm.org/D72181
* [lldb/Utility] YAML validation should be orthogonal to packet semantics.Jonas Devlieghere2020-01-031-3/+0
| | | | | | It's not up to YAML to validate the semantics of the GDB remote packet struct. This is especially wrong here as there's nothing that says that the amount of bytes transmitted matches the packet payload size.
* [lldb/Docs] Include the man page on the websiteJonas Devlieghere2020-01-031-4/+5
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* [PowerPC][LoopVectorize] Add tests for fp128 and fp16Jinsong Ji2020-01-031-0/+58
| | | | Add two tests to reg-usage.ll
* [globalisel] Fix another mismatch between %d and the RuleID typeDaniel Sanders2020-01-031-1/+1
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* [lldb/Docs] Include how to generate the man pageJonas Devlieghere2020-01-031-0/+1
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* [clang-tidy] fix linkage with clangSema for FixitHintUtils, undo previous ↵Jonas Toth2020-01-032-1/+1
| | | | wrong fix
* [mlir] Compilation fix: use LLVM_ATTRIBUTE_UNUSED following ↵Alexandre Ganea2020-01-031-6/+2
| | | | | | 6656e961c08393c3949412ef945ade0272b66fca Differential Revision: https://reviews.llvm.org/D72124
* [mlir] Fix indexed_accessor_range to properly forward the derived class.River Riddle2020-01-036-25/+70
| | | | | | | | Summary: This fixes the return value of helper methods on the base range class. Reviewed By: jpienaar Differential Revision: https://reviews.llvm.org/D72127
* GlobalISel: Add type argument to getRegBankFromRegClassMatt Arsenault2020-01-0313-30/+43
| | | | | | AMDGPU can't unambiguously go back from the selected instruction register class to the register bank without knowing if this was used in a boolean context.
* [bindings/go] Add Subprogram methodAyke van Laethem2020-01-031-0/+5
| | | | | | | This method allows getting the subprogram metadata object from a function value. Differential Revision: https://reviews.llvm.org/D71528
* [amdgpu] Skip non-instruction values in CF user tracing.Michael Liao2020-01-031-0/+2
| | | | | | | | | | | | | | | | Summary: - CF users won't be non-instruction values. Skip them to save the compilation time. It's especially true when there are multiple functions in that module, where, says, a constant may be used in most functions. The current CF user tracing adds significant overhead. Reviewers: alex-t, rampitec Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72174
* [clang-tidy] quickfix: add -fno-delayed-template-parsing as default argument ↵Jonas Toth2020-01-031-0/+1
| | | | for runCheckOnCode unit-tests to unbreak windows
* [clang-tidy] fix broken linking for AddConstTest with adding clangSema as ↵Jonas Toth2020-01-031-0/+1
| | | | dependency (DeclSpec)
* [NFC][ORC] Fix typos and whitespaces in commentsStefan Gränitz2020-01-035-41/+41
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* [gn build] Port 9861a8538c0LLVM GN Syncbot2020-01-031-0/+1
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* [SystemZ] Don't allow CL option -mpacked-stack with -mbackchain.Jonas Paulsson2020-01-034-3/+19
| | | | | | | -mpacked-stack is currently not supported with -mbackchain, so this should result in a compilation error message instead of being silently ignored. Review: Ulrich Weigand
* AMDGPU: Add gfx9 run lines to a testcaseMatt Arsenault2020-01-031-5/+13
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* AMDGPU/GlobalISel: Add new utils fileMatt Arsenault2020-01-034-33/+77
| | | | | | There are some things that are shareable between the legalizer, regbankselect, and the selector that don't have an obvious place to go.
* AMDGPU: Only allow regs for s_movrel_{b32|b64}Matt Arsenault2020-01-031-2/+13
| | | | | This would incorrectly allowing folding immediates. These currently aren't selectable, but will be from GlobalISel soon.
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