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* [ARM] Add bitcast/extract_subvec. of fp16 vectorsDiogo N. Sampaio2019-04-293-93/+866
| | | | | | | | | | | | | | | | | | | | Summary: This patch adds some basic operations for fp16 vectors, such as bitcast from fp16 to i16, required to perform extract_subvector (also added here) and extract_element. Reviewers: SjoerdMeijer, DavidSpickett, t.p.northover, ostannard Reviewed By: ostannard Subscribers: javed.absar, kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60618 llvm-svn: 359433
* [clangd] Surface diagnostics from headers inside main fileKadir Cetinkaya2019-04-295-19/+198
| | | | | | | | | | | | Reviewers: ioeric, ilya-biryukov Subscribers: MaskRay, jkorous, arphaman, jdoerfert, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59302 llvm-svn: 359432
* [ARM] Add v4f16 and v8f16 types to the CallingConvDiogo N. Sampaio2019-04-292-18/+244
| | | | | | | | | | | | | | | | | | | | | Summary: The Procedure Call Standard for the Arm Architecture states that float16x4_t and float16x8_t behave just as uint16x4_t and uint16x8_t for argument passing. This patch adds the fp16 vectors to the ARMCallingConv.td file. Reviewers: miyuki, ostannard Reviewed By: ostannard Subscribers: ostannard, javed.absar, kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60720 llvm-svn: 359431
* vs integration: Use llvm-lib for librarianRussell Gallop2019-04-293-0/+24
| | | | | | | | | | | | | | This uses llvm-lib.exe for the librarian instead of Visual Studio provided lib.exe. Without this it is not possible to create static libraries with -flto using the plugin. Original patch by Steven Noonan This fixes: PR41147 Differential Revision: https://reviews.llvm.org/D61193 llvm-svn: 359430
* gn: Fix check-clang build after r359179Hans Wennborg2019-04-291-0/+1
| | | | llvm-svn: 359429
* [clangd] Delete config.clangd_xpc_support from test/ to unbreak check-llvm-toolsFangrui Song2019-04-292-5/+0
| | | | | | | D61187 didn't delete config.clangd_xpc_support from test/ CLANGD_BUILD_XPC is defined in clangd/CMakeLists.txt and not available in test/lit.site.cfg.py.in llvm-svn: 359428
* Try to use /proc on FreeBSD for getExecutablePathDavid Chisnall2019-04-291-1/+14
| | | | | | | | | | | Currently, clang's libTooling passes this function a fake argv0, which means that no libTooling tools can find the standard headers on FreeBSD. With this change, these will now work on any FreeBSD systems that have procfs mounted. This isn't the right fix for the libTooling issue, but it does bring the FreeBSD implementation of getExecutablePath closer to the Linux and macOS implementations. llvm-svn: 359427
* [DebugInfo] Terminate more location-list ranges at the end of blocksJeremy Morse2019-04-296-35/+464
| | | | | | | | | | | | | | | | This patch fixes PR40795, where constant-valued variable locations can "leak" into blocks placed at higher addresses. The root of this is that DbgEntityHistoryCalculator terminates all register variable locations at the end of each block, but not constant-value variable locations. Fixing this requires constant-valued DBG_VALUE instructions to be broadcast into all blocks where the variable location remains valid, as documented in the LiveDebugValues section of SourceLevelDebugging.rst, and correct termination in DbgEntityHistoryCalculator. Differential Revision: https://reviews.llvm.org/D59431 llvm-svn: 359426
* [DWARF] Fix dump of local/foreign TU lists in .debug_namesFangrui Song2019-04-292-2/+110
| | | | | | Differential Revision: https://reviews.llvm.org/D61241 llvm-svn: 359425
* [clangd] Move clangd tests to clangd directory. check-clangd is no longer ↵Sam McCall2019-04-29112-58/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | part of check-clang-tools. Summary: Motivation: - this layout is a pain to work with - without a common root, it's painful to express things like "disable clangd" (D61122) - CMake/lit configs are a maintenance hazard, and the more the one-off hacks for various tools are entangled, the more we see apathy and non-ownership. This attempts to use the bare-minimum configuration needed (while still supporting the difficult cases: windows, standalone clang build, dynamic libs). In particular the lit.cfg.py and lit.site.cfg.py.in are merged into lit.cfg.in. The logic in these files is now minimal. (Much of clang-tools-extra's lit configs can probably be cleaned up by reusing lit.llvm.llvm_config.use_clang(), and every llvm project does its own version of LDPATH mangling. I haven't attempted to fix any of those). Docs are still in clang-tools-extra/docs, I don't have any plans to touch those. Reviewers: gribozavr Subscribers: mgorny, javed.absar, MaskRay, jkorous, arphaman, kadircet, jfb, cfe-commits, ilya-biryukov, thakis Tags: #clang Differential Revision: https://reviews.llvm.org/D61187 llvm-svn: 359424
* [builtins] Use __APPLE__ instead of __MACH__ in checkPetr Hosek2019-04-291-1/+1
| | | | | | | The latter doesn't seem to be working for all targets. This addresses the issue introduced in r359413. llvm-svn: 359423
* [DWARF] Delete a redundant check in getFileNameByIndex()Fangrui Song2019-04-291-2/+1
| | | | llvm-svn: 359422
* [builtins] Fix the missing assembly on DarwinPetr Hosek2019-04-291-1/+1
| | | | | | This was introduced in r359413. llvm-svn: 359421
* [Windows] Dump more information about access violation exceptionAleksandr Urakov2019-04-294-1/+110
| | | | | | | | | | | | | | | | | | | | Summary: Dump more information about "access violation" and "in page error" exceptions to description. Description now contains data about read/write violation type and actual address as described at https://docs.microsoft.com/en-us/windows/desktop/api/winnt/ns-winnt-_exception_record Reviewers: asmith, stella.stamenova Reviewed By: stella.stamenova Subscribers: teemperor, amccarth, abidh, lldb-commits, aleksandr.urakov Tags: #lldb Differential Revision: https://reviews.llvm.org/D60519 llvm-svn: 359420
* [builtins] Fix the typo in the preprocessor checkPetr Hosek2019-04-291-1/+1
| | | | | | This was introduced in r359413. llvm-svn: 359419
* [X86] Remove some intel syntax aliases on (v)cvtpd2(u)dq, (v)cvtpd2ps, ↵Craig Topper2019-04-296-202/+3085
| | | | | | | | | | | | | | | | | | | (v)cvt(u)qq2ps. Add 'x' and'y' suffix aliases to masked version of the same in att syntax. The 128/256 bit version of these instructions require an 'x' or 'y' suffix to disambiguate the memory form in att syntax. We were allowing the same suffix in intel syntax, but it appears gas does not do that. gas does allow the 'x' and 'y' suffix on register and broadcast forms even though its not needed. We were allowing it on unmasked register form, but not on masked versions or on masked or unmasked broadcast form. While there fix some test coverage holes so they can be extended with the 'x' and 'y' suffix tests. llvm-svn: 359418
* [llvm-nm] -print-size => --print-sizeFangrui Song2019-04-291-1/+1
| | | | llvm-svn: 359417
* [llvm-nm] Simplify and fix a buffer overflowFangrui Song2019-04-291-149/+107
| | | | | | | | | | | | | * char SymbolAddrStr[18] can't hold "%" PRIo64 which may need 22 characters. * Use range-based for * Delete unnecessary typedef * format(...).print(Str, sizeof(Str)) + outs() << Str => outs() << format(...) * Use cascading outs() << .. << .. * Use iterator_range(Container &&c) * (A & B) == B => A & B if B is a power of 2 * replace null sentinel in constants with makeArrayRef llvm-svn: 359416
* Remove XFail for new GCC. They fixed itEric Fiselier2019-04-291-1/+1
| | | | llvm-svn: 359415
* llvm-cvtres: Attempt to make llvm-cvtres/duplicate.test work on big-endian ↵Nico Weber2019-04-291-12/+14
| | | | | | systems llvm-svn: 359414
* [builtins] Use aliases for function redirectsPetr Hosek2019-04-2941-95/+85
| | | | | | | | | | | | | Symbol aliases are supported by all platforms that compiler-rt builtins target, and we can use these instead of function redirects to avoid the extra indirection. This is part of the cleanup proposed in "[RFC] compiler-rt builtins cleanup and refactoring". Differential Revision: https://reviews.llvm.org/D60931 llvm-svn: 359413
* Add some lld-link 9.0 release notesNico Weber2019-04-291-0/+11
| | | | llvm-svn: 359412
* [builtins] Use single line C++/C99 comment stylePetr Hosek2019-04-28240-3869/+3489
| | | | | | | | | | | Use the uniform single line C++/99 style for code comments. This is part of the cleanup proposed in "[RFC] compiler-rt builtins cleanup and refactoring". Differential Revision: https://reviews.llvm.org/D60352 llvm-svn: 359411
* [builtins] Reformat builtins with clang-formatPetr Hosek2019-04-28193-5873/+5341
| | | | | | | | | | | Update formatting to use the LLVM style. This is part of the cleanup proposed in "[RFC] compiler-rt builtins cleanup and refactoring". Differential Revision: https://reviews.llvm.org/D60351 llvm-svn: 359410
* [X86] Add PR39921 HADD pairwise reduction test and AVX2 test coverageSimon Pilgrim2019-04-281-22/+107
| | | | llvm-svn: 359409
* [X86][AVX] Add fast-hops target for add/fadd reduction testsSimon Pilgrim2019-04-284-509/+1319
| | | | llvm-svn: 359408
* [X86] Add PR39936 HADD TestsSimon Pilgrim2019-04-281-0/+112
| | | | llvm-svn: 359407
* [X86][SSE] combineExtractVectorElt - add early-out to return zero/undef for ↵Simon Pilgrim2019-04-281-2/+4
| | | | | | out-of-range extraction indices. llvm-svn: 359406
* Fix permission error while running botsEric Fiselier2019-04-281-0/+1
| | | | llvm-svn: 359405
* attempt to unbreak build botsEric Fiselier2019-04-282-5/+7
| | | | llvm-svn: 359404
* Attempt to switch to auto-scaling botsEric Fiselier2019-04-283-0/+117
| | | | llvm-svn: 359403
* [ConstantRange] Add makeExactNoWrapRegion()Nikita Popov2019-04-284-10/+32
| | | | | | | | | | | | | | | | | | | | | | | I got confused on the terminology, and the change in D60598 was not correct. I was thinking of "exact" in terms of the result being non-approximate. However, the relevant distinction here is whether the result is * Largest range such that: Forall Y in Other: Forall X in Result: X BinOp Y does not wrap. (makeGuaranteedNoWrapRegion) * Smallest range such that: Forall Y in Other: Forall X not in Result: X BinOp Y wraps. (A hypothetical makeAllowedNoWrapRegion) * Both. (makeExactNoWrapRegion) I'm adding a separate makeExactNoWrapRegion method accepting a single APInt (same as makeExactICmpRegion) and using it in the places where the guarantee is relevant. Differential Revision: https://reviews.llvm.org/D60960 llvm-svn: 359402
* [X86][AVX] Enabled AVX512F tests and add PR40815 test caseSimon Pilgrim2019-04-281-0/+75
| | | | llvm-svn: 359401
* [X86][AVX] Combine non-lane crossing binary shuffles using X86ISD::VPERMV3Simon Pilgrim2019-04-2824-677/+1329
| | | | | | Some of the combines might be further improved if we lower more shuffles with X86ISD::VPERMV3 directly, instead of waiting to combine the results. llvm-svn: 359400
* [SelectionDAG] include FP min/max variants as binary operatorsSanjay Patel2019-04-282-20/+25
| | | | | | | The x86 test diffs don't look great because of extra move ops, but FP min/max should clearly be included in the list. llvm-svn: 359399
* [DAGCombiner] try repeated fdiv divisor transform before building estimateSanjay Patel2019-04-282-42/+30
| | | | | | | | | | | | | | | | | | This was originally part of D61028, but it's an independent diff. If we try the repeated divisor reciprocal transform before producing an estimate sequence, then we have an opportunity to use scalar fdiv. On x86, the trade-off is 1 divss vs. 5 vector FP ops in the default estimate sequence. On recent chips (Skylake, Ryzen), the full-precision division is only 3 cycle throughput, so that's probably the better perf default option and avoids problems from x86's inaccurate estimates. The last 2 tests show that users still have the option to override the defaults by using the function attributes for reciprocal estimates, but those patterns are potentially made faster by converting the vector ops (including ymm ops) to scalar math. Differential Revision: https://reviews.llvm.org/D61149 llvm-svn: 359398
* [MCA] Fix typo in AVX2 gather tests. NFCAndrea Di Biagio2019-04-286-18/+18
| | | | llvm-svn: 359397
* [X86][SSE] Optimize llvm.experimental.vector.reduce.xor.vXi1 parity ↵Simon Pilgrim2019-04-282-1566/+667
| | | | | | | | | | reduction (PR38840) An xor reduction of a bool vector can be optimized to a parity check of the MOVMSK/BITCAST'd integer - if the population count is odd return 1, else return 0. Differential Revision: https://reviews.llvm.org/D61230 llvm-svn: 359396
* [X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584)Simon Pilgrim2019-04-284-156/+2444
| | | | llvm-svn: 359395
* [CMake] Don't modify `FUZZER_SUPPORTED_ARCH` is place.Dan Liew2019-04-281-2/+3
| | | | | | | | | | | | | | On a Darwin host we were modifying the `FUZZER_SUPPORTED_ARCH` in place which would strip out non-x86 architectures. This unhelpful if we want to use `FUZZER_SUPPORTED_ARCH` later. To fix this we introduce `FUZZER_TEST_ARCH` which is similar to what we have for for the other sanitizers. For non-Darwin host platforms `FUZZER_TEST_ARCH` is the same as `FUZZER_SUPPORTED_ARCH` but for Darwin host platforms we use `darwin_filter_host_archs(...)` as the previous code did. llvm-svn: 359394
* [PowerPC][Clang] Add tests for PowerPC MMX intrinsicsQiu Chaofan2019-04-281-41/+1243
| | | | | | | | Add the rest of test cases covering functions defined in mmintrin.h on PowerPC. Reviewed By: Jinsong Ji llvm-svn: 359393
* [X86] Remove (V)MOV64toSDrr/m and (V)MOVDI2SSrr/m. Use 128-bit result ↵Craig Topper2019-04-287-133/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MOVD/MOVQ and COPY_TO_REGCLASS instead Summary: The register form of these instructions are CodeGenOnly instructions that cover GR32->FR32 and GR64->FR64 bitcasts. There is a similar set of instructions for the opposite bitcast. Due to the patterns using bitcasts these instructions get marked as "bitcast" machine instructions as well. The peephole pass is able to look through these as well as other copies to try to avoid register bank copies. Because FR32/FR64/VR128 are all coalescable to each other we can end up in a situation where a GR32->FR32->VR128->FR64->GR64 sequence can be reduced to GR32->GR64 which the copyPhysReg code can't handle. To prevent this, this patch removes one set of the 'bitcast' instructions. So now we can only go GR32->VR128->FR32 or GR64->VR128->FR64. The instruction that converts from GR32/GR64->VR128 has no special significance to the peephole pass and won't be looked through. I guess the other option would be to add support to copyPhysReg to just promote the GR32->GR64 to a GR64->GR64 copy. The upper bits were basically undefined anyway. But removing the CodeGenOnly instruction in favor of one that won't be optimized seemed safer. I deleted the peephole test because it couldn't be made to work with the bitcast instructions removed. The load version of the instructions were unnecessary as the pattern that selects them contains a bitcasted load which should never happen. Fixes PR41619. Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61223 llvm-svn: 359392
* Revert rL359389: [X86][SSE] Add support for <64 x i1> bool reductionSimon Pilgrim2019-04-273-67/+195
| | | | | | | | Minor generalization of the existing <32 x i1> pre-AVX2 split code. ........ Causing irregular buildbot failures. llvm-svn: 359391
* [X86][AVX] Add additional SSE/AVX expandload and compressstore targetsSimon Pilgrim2019-04-272-3268/+8447
| | | | llvm-svn: 359390
* [X86][SSE] Add support for <64 x i1> bool reductionSimon Pilgrim2019-04-273-195/+67
| | | | | | Minor generalization of the existing <32 x i1> pre-AVX2 split code. llvm-svn: 359389
* [X86][AVX] Cleanup and add additional expandload and compressstore testsSimon Pilgrim2019-04-272-764/+2331
| | | | | | sort order by types and add vXi32/vXi16/vXi8 test coverage llvm-svn: 359388
* Fix UNPREDICTABLE check in EmulateInstructionARM::EmulateADDRegShiftRaphael Isemann2019-04-271-1/+1
| | | | | | | | | | | | | | | | | | | Summary: As reported in LLVM bug 41487, the check in this function is wrong and should be the same as the described check in the comment (which is correctly copied from the ARM ISA reference). Reviewers: #lldb, davide, JDevlieghere Reviewed By: #lldb, davide, JDevlieghere Subscribers: davide, javed.absar, kristof.beyls, lldb-commits Tags: #lldb Differential Revision: https://reviews.llvm.org/D60654 llvm-svn: 359387
* [X86][AVX512] Improve vector bool reductionsSimon Pilgrim2019-04-275-1373/+333
| | | | | | As predicate masks are legal on AVX512 targets, we avoid MOVMSK in these cases, but we can just bitcast the bool vector to the integer equivalent directly - avoiding expansion of the reduction to a shuffle pattern. llvm-svn: 359386
* [X86] Add vector boolean reduction tests (PR38840)Simon Pilgrim2019-04-273-0/+6304
| | | | | | | | AND/OR/XOR tests for the @llvm.experimental.vector.reduce intrinsics AND/OR are pretty good (pre-AVX512), XOR (not so common but used for parity reduction) is still pretty bad. llvm-svn: 359385
* [lli] Fix a typo in a cl::opt description.Lang Hames2019-04-271-1/+1
| | | | | | | | Patch by Wasiher. Thanks Wasiher! Differential Revision: https://reviews.llvm.org/D61135 llvm-svn: 359384
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