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* [WinEH] Allow for multiple terminatepadsReid Kleckner2018-01-024-24/+68
| | | | | | | | | Fixes verifier errors with Windows EH and OpenMP, which injects a terminate scope around parallel blocks. Fixes PR35778 llvm-svn: 321676
* [OMPT] Build runtime with OMPT support by defaultJoachim Protze2018-01-023-7/+23
| | | | | | | | This patch enables OMPT by default if version 50 or later is built and the config says, that OMPT will be supported. Differential Revision: https://reviews.llvm.org/D41508 llvm-svn: 321675
* Handle the case of live 16-bit subregisters in X86FixupBWInstsAndrew Kaylor2018-01-022-82/+121
| | | | | | | Differential Revision: https://reviews.llvm.org/D40524 Change-Id: Ie3a405b28503ceae999f5f3ba07a68fa733a2400 llvm-svn: 321674
* [AArch64] fix typos in comments; NFCSanjay Patel2018-01-021-2/+2
| | | | llvm-svn: 321673
* [ValueTracking] recognize min/max of min/max patternsSanjay Patel2018-01-022-224/+239
| | | | | | | | | | | | | | | | | | | | | | This is part of solving PR35717: https://bugs.llvm.org/show_bug.cgi?id=35717 The larger IR optimization is proposed in D41603, but we can show the improvement in ValueTracking using codegen tests because SelectionDAG creates min/max nodes based on ValueTracking. Any target with min/max ops should show wins here. I chose AArch64 vector ops because they're clean and uniform. Some Alive proofs for the tests (can't put more than 2 tests in 1 page currently because the web app says it's too long): https://rise4fun.com/Alive/WRN https://rise4fun.com/Alive/iPm https://rise4fun.com/Alive/HmY https://rise4fun.com/Alive/CNm https://rise4fun.com/Alive/LYf llvm-svn: 321672
* [DOXYGEN] Fix doxygen and content issues in smmintrin.hDouglas Yung2018-01-021-3/+3
| | | | | | | | | | | - Fix formatting issue due to hyphenated terms at line breaks. - Fix typo This patch was made by Craig Flores Differential Revision: https://reviews.llvm.org/D41520 llvm-svn: 321671
* [DOXYGEN] Fix doxygen and content issues in pmmintrin.hDouglas Yung2018-01-021-3/+3
| | | | | | | | | | - Fix incorrect wording in various intrinsic descriptions. Previously the descriptions used "low-order" and "high-order" when the intended meaning was "even-indexed" and "odd-indexed". This patch was made by Craig Flores Differential Revision: https://reviews.llvm.org/D41518 llvm-svn: 321670
* [DOXYGEN] Fix doxygen and content issues in emmintrin.hDouglas Yung2018-01-021-48/+63
| | | | | | | | | | | | | | | - Fixed innaccurate instruction mappings for various intrinsics. - Fixed description of NaN handling in comparison intrinsics. - Unify description of _mm_store_pd1 to match _mm_store1_pd. - Fix incorrect wording in various intrinsic descriptions. Previously the descriptions used "low-order" and "high-order" when the intended meaning was "even-indexed" and "odd-indexed". - Fix typos. - Add missing italics command (\a) for params and fixed some parameter spellings. This patch was made by Craig Flores Differential Revision: https://reviews.llvm.org/D41516 llvm-svn: 321669
* [AArch64] add tests for min/max of min/max (PR35717); NFCSanjay Patel2018-01-021-0/+1096
| | | | llvm-svn: 321668
* [PPC64] Port to ppc64le - initial versionMartin Storsjo2018-01-0210-5/+931
| | | | | | | | | | | | | | | | | | Initial working version of libunwind for PowerPC 64. Tested on little-endian ppc64 host only. Based on the existing PowerPC 32 code. It supports: - context save/restore (unw_getcontext, unw_init_local, unw_resume) - read/write from/to saved registers - backtrace (unw_step) Patch by Leandro Lupori! Differential Revision: https://reviews.llvm.org/D41386 llvm-svn: 321667
* One more (should be) inline variable that is defined in the dylibMarshall Clow2018-01-021-3/+3
| | | | llvm-svn: 321666
* Suppress undefined-template warnings when the pattern is declared in a ↵Nick Lewycky2018-01-022-2/+15
| | | | | | | | system header. The way to fix an undefined-template warning is to add lines to the header file that defines the template pattern. We should suppress the warnings when the template pattern is in a system header because we don't expect users to edit those. llvm-svn: 321665
* Un-inline a few more variables that are exported from the dylib.Marshall Clow2018-01-022-11/+11
| | | | llvm-svn: 321664
* Temporarily revert the inlining of 'piecewise_construct' because it is ↵Marshall Clow2018-01-021-1/+1
| | | | | | exported from the dylib. llvm-svn: 321663
* [AArch64][GlobalISel] Fix assert fail with unknown intrinsic.Amara Emerson2018-01-022-5/+18
| | | | | | | | A call may have an intrinsic name but not have a valid intrinsic ID, for example with llvm.invariant.group.barrier. If so, treat it as a normal call like FastISel does. llvm-svn: 321662
* A couple more inlined variables that I missed the first timeMarshall Clow2018-01-022-8/+14
| | | | llvm-svn: 321661
* [Sema] Don't emit the -Wstrict-prototypes warning for variadic functions.Volodymyr Sapsai2018-01-022-1/+7
| | | | | | | | | | | | | | rdar://problem/33251668 Reviewers: arphaman, ahatanak Reviewed By: arphaman Subscribers: ptitei, cfe-commits Differential Revision: https://reviews.llvm.org/D41528 llvm-svn: 321660
* [opt-viewer] Check for pygments.lexer.c_cppJonas Hahnfeld2018-01-021-2/+6
| | | | | | | | | Some systems still don't have this module which was introduced in version 2.0 (CentOS 7, sigh). Differential Revision: https://reviews.llvm.org/D41611 llvm-svn: 321659
* Implement most of P0607: Inline Variables for the Standard Library. This ↵Marshall Clow2018-01-0215-217/+295
| | | | | | involved marking a lot of variables as inline (but only for C++17 and later). llvm-svn: 321658
* Align SHT_NOBITS sections is they are the first on a PT_LOAD.Rafael Espindola2018-01-022-10/+34
| | | | | | | | | | | | | | | | | | | We normally want to ignore SHT_NOBITS sections when computing offsets. The sh_offset of section itself seems to be irrelevant and - If the section is in the middle of a PT_LOAD, it will make no difference on the computed offset of the followup section. - If it is in the end of a PT_LOAD, we want to avoid its alignment changing the offset of the followup sections. The issue is if it is at the start of the PT_LOAD. In that case we do have to align it so that the following sections have congruent address and offset module the page size. We were not handling this case. This should fix freebsd kernel link. llvm-svn: 321657
* [x86] allow pairs of PCMPEQ for vector-sized integer equality comparisons ↵Sanjay Patel2018-01-022-95/+227
| | | | | | | | | | | | | | | | | | (PR33325) This is an extension of D31156 with the goal that we'll allow memcmp() == 0 expansion for x86 to use 2 pairs of loads per block. The memcmp expansion pass (formerly part of CGP) will generate this kind of pattern with oversized integer compares, so we want to transform these into x86-specific vector nodes before legalization splits things into scalar chunks. See PR33325 for more details: https://bugs.llvm.org/show_bug.cgi?id=33325 Differential Revision: https://reviews.llvm.org/D41618 llvm-svn: 321656
* [AArch64][GlobalISel] Enable GlobalISel at -O0 by defaultAmara Emerson2018-01-0244-56/+67
| | | | | | | | | | | Tests updated to explicitly use fast-isel at -O0 instead of implicitly. This change also allows an explicit -fast-isel option to override an implicitly enabled global-isel. Otherwise -fast-isel would have no effect at -O0. Differential Revision: https://reviews.llvm.org/D41362 llvm-svn: 321655
* [Core/Debugger] Remove some code that doesn't compile anymore.Davide Italiano2018-01-021-69/+0
| | | | llvm-svn: 321654
* [BasicBlockUtils] Check for unreachable preds before updating LI in ↵Anna Thomas2018-01-022-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | UpdateAnalysisInformation Summary: We are incorrectly updating the LI when loop-simplify generates dedicated exit blocks for a loop. The issue is that there's an implicit assumption that the Preds passed into UpdateAnalysisInformation are reachable. However, this is not true and breaks LI by incorrectly updating the header of a loop. One such case is when we generate dedicated exits when the exit block is a landing pad (through SplitLandingPadPredecessors). There maybe other cases as well, since we do not guarantee that Preds passed in are reachable basic blocks. The added test case shows how loop-simplify breaks LI for the outer loop (and DT in turn) after we try to generate the LoopSimplifyForm. Reviewers: davide, chandlerc, sanjoy Reviewed By: davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41519 llvm-svn: 321653
* [MacOSX-Kernel] Remove broken KDP_IMAGEPATH support.Davide Italiano2018-01-021-37/+0
| | | | llvm-svn: 321652
* [ARM64] Remove unused function. NFCI.Davide Italiano2018-01-021-13/+0
| | | | llvm-svn: 321651
* [Hexagon] Fix generation of vector sign extensionsKrzysztof Parzyszek2018-01-023-33/+75
| | | | llvm-svn: 321650
* Revert r321089: "[DAG] Elide overlapping store" (and subsequent fix in r321204)Daniel Jasper2018-01-022-23/+24
| | | | | | | Our internal testing has revealed has discovered bugs in PPC builds. I have forward reproduction instructions to the original author (Nirav). llvm-svn: 321649
* NFC. Add description comments to Function headerDmitry Venikov2018-01-021-0/+7
| | | | | | | | | | | | Reviewers: ruiu, davidxl, silvas, brzycki Reviewed By: brzycki Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41609 llvm-svn: 321648
* Revert "ASan+operator new[]: Fix operator new[] cookie poisoning"Filipe Cabecinhas2018-01-022-10/+3
| | | | | | | | This reverts r321645. I missed a compiler-rt test that needs updating. llvm-svn: 321647
* [AArch64][AsmParser] Add isScalarReg() and repurpose isReg()Sander de Smalen2018-01-021-10/+14
| | | | | | | | | | | | | | | | | Summary: isReg() in AArch64AsmParser.cpp is a bit of a misnomer, and would be better named 'isScalarReg()' instead. Patch [1/3] in a series to add operand constraint checks for SVE's predicated ADD/SUB. Reviewers: rengolin, mcrosier, evandro, fhahn, echristo Reviewed By: fhahn Subscribers: aemerson, javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D41445 llvm-svn: 321646
* ASan+operator new[]: Fix operator new[] cookie poisoningFilipe Cabecinhas2018-01-022-3/+10
| | | | | | | | | | | | | | | | | | Summary: The C++ Itanium ABI says: No cookie is required if the new operator being used is ::operator new[](size_t, void*). We should only avoid poisoning the cookie if we're calling this operator, not others. This is dealt with before the call to InitializeArrayCookie. Reviewers: rjmccall, kcc, rsmith Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D41301 llvm-svn: 321645
* Strip trailing whitespace. NFCISimon Pilgrim2018-01-021-2/+2
| | | | llvm-svn: 321644
* [RISCV] Add Defs Uses information for c.jal and c.addi4spnAlex Bradbury2018-01-021-2/+2
| | | | | | | Differential Revision: https://reviews.llvm.org/D41339 Patch by Shiva Chen. llvm-svn: 321643
* [RISCV][NFC] Resolve unused variable warning in RISCVISelLoweringAlex Bradbury2018-01-021-2/+1
| | | | | | XLenVT in LowerFormalArguments is used only in an assert. llvm-svn: 321642
* [DAGCombine] Fix for PR35765Sam Parker2018-01-022-2/+2
| | | | | | | | | | | Remove the acceptance of ANY_EXTEND nodes while trying to move and nodes back to loads. Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=35765 Differential Revision: https://reviews.llvm.org/D41625 llvm-svn: 321641
* [X86] Codegen test for pr35765Sam Parker2018-01-021-0/+44
| | | | | | Committing reproducer test for pr35765, fix to follow. llvm-svn: 321640
* [Driver] Fix unused variables and test-writing-into-workdir after r321621Sam McCall2018-01-022-7/+7
| | | | llvm-svn: 321639
* [SelectionDAG] Teach WidenVecOp_Convert to widen the operation if a widened ↵Craig Topper2018-01-023-111/+73
| | | | | | result type would still be legal. llvm-svn: 321638
* [InstCombine] Missed optimization in math expression: squashing sqrt functionsDmitry Venikov2018-01-022-0/+84
| | | | | | | | | | | | | | Summary: This patch enables folding under -ffast-math flag sqrt(a) * sqrt(b) -> sqrt(a*b) Reviewers: hfinkel, spatel, davide Reviewed By: spatel, davide Subscribers: davide, llvm-commits Differential Revision: https://reviews.llvm.org/D41322 llvm-svn: 321637
* Test commitDmitry Venikov2018-01-021-1/+1
| | | | | | | | | | Reviewers: Quolyk Reviewed By: Quolyk Differential Revision: https://reviews.llvm.org/D41561 llvm-svn: 321636
* [SelectionDAG] Remove ifs on getTypeAction being TypeWidenVector from some ↵Craig Topper2018-01-021-9/+11
| | | | | | | | of the WideVecOp handlers. We should only be in the handler if the tyep action is TypeWidenVector. There's no reason to try to do anything else. llvm-svn: 321635
* [ValueTracking] Don't assume shift values are in rangeSimon Pilgrim2018-01-012-4/+25
| | | | | | Reduced (as best I could...) from oss-fuzz #4857 test case llvm-svn: 321634
* [InstCombine] Regenerate udiv tests.Simon Pilgrim2018-01-011-9/+9
| | | | llvm-svn: 321633
* [X86] Promote vXi1 fp_to_uint/fp_to_sint to vXi32 to avoid scalarization.Craig Topper2018-01-012-3417/+137
| | | | llvm-svn: 321632
* [X86] Add test cases for vXi1 fptosi/fptoui.Craig Topper2018-01-011-0/+3680
| | | | | | Currently we do a lot of scalarization in these test cases. llvm-svn: 321631
* [X86] Replace custom lowering of vXi1 SINT_TO_FP/UINT_TO_FP with promotion.Craig Topper2018-01-011-32/+20
| | | | | | The custom lowering was just doing the same thing promotion would do. llvm-svn: 321630
* [SelectionDAG][X86][AArch64] Require targets to specify the promotion type ↵Craig Topper2018-01-013-51/+35
| | | | | | | | | | | | | | | | when using setOperationAction Promote for INT_TO_FP and FP_TO_INT Currently the promotion for these ignores the normal getTypeToPromoteTo and instead just tries to double the element width. This is because the default behavior of getTypeToPromote to just adds 1 to the SimpleVT, which has the affect of increasing the element count while keeping the scalar size the same. If multiple steps are required to get to a legal operation type, int_to_fp will be promoted multiple times. And fp_to_int will keep trying wider types in a loop until it finds one that works. getTypeToPromoteTo does have the ability to query a promotion map to get the type and not do the increasing behavior. It seems better to just let the target specify the promotion type in the map explicitly instead of letting the legalizer iterate via widening. FWIW, it's worth I think for any other vector operations that need to be promoted, we have to specify the type explicitly because the default behavior of getTypeToPromote isn't useful for vectors. The other types of promotion already require either the element count is constant or the total vector width is constant, but neither happens by incrementing the SimpleVT enum. Differential Revision: https://reviews.llvm.org/D40664 llvm-svn: 321629
* Again reverting an attempt to convert the DeclSpec enums into scoped enums.Faisal Vali2018-01-0122-298/+260
| | | | | | | | | | | | - reverts r321622, r321625, and r321626. - the use of bit-fields is still resulting in warnings - even though we can use static-asserts to harden the code and ensure the bit-fields are wide enough. The bots still complain of warnings being seen. - to silence the warnings requires specifying the bit-fields with the underlying enum type (as opposed to the enum type itself), which then requires lots of unnecessary static casts of each enumerator within DeclSpec to the underlying-type, which even though could be seen as implementation details, it does hamper readability - and given the additional litterings, makes me question the value of the change. So in short - I give up (for now at least). Sorry about the noise. llvm-svn: 321628
* [scudo] Touch memory to count as RSSJonas Hahnfeld2018-01-011-5/+10
| | | | | | | | This should fix the test from https://reviews.llvm.org/D41128. Differential Revision: https://reviews.llvm.org/D41649 llvm-svn: 321627
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