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* AMDGPU/GlobalISel: Select fmed3Matt Arsenault2019-09-096-1/+303
| | | | llvm-svn: 371435
* [IfConversion] Correctly handle cases where analyzeBranch fails.Eli Friedman2019-09-092-3/+8
| | | | | | | | | | | | | | | | If analyzeBranch fails, on some targets, the out parameters point to some blocks in the function. But we can't use that information, so make sure to clear it out. (In some places in IfConversion, we assume that any block with a TrueBB is analyzable.) The change to the testcase makes it trigger a bug on builds without this fix: IfConvertDiamond tries to perform a followup "merge" operation, which isn't legal, and we somehow end up with a branch to a deleted MBB. I'm not sure how this doesn't crash the compiler. Differential Revision: https://reviews.llvm.org/D67306 llvm-svn: 371434
* [x86] add test for false dependency with minsize (PR43239); NFCSanjay Patel2019-09-091-1/+17
| | | | llvm-svn: 371433
* AMDGPU: Use PatFrags to allow selecting custom nodes or intrinsicsMatt Arsenault2019-09-0916-10/+954
| | | | | | | | | | | | | | | | | This enables GlobalISel to handle various intrinsics. The custom node pattern will be ignored, and the intrinsic will work. This will also allow SelectionDAG to directly select the intrinsics, but as they are all custom lowered to the nodes, this ends up leaving dead code in the table. Eventually either GlobalISel should add the equivalent of custom nodes equivalent, or intrinsics should be directly used. These each have different tradeoffs. There are a few more to handle, but these are easy to handle ones. Some others fail for other reasons. llvm-svn: 371432
* [SelectionDAG] Remove ISD::FP_ROUND_INREGCraig Topper2019-09-0910-68/+3
| | | | | | | | | | | | I don't think anything in tree creates this node. So all of this code appears to be dead. Code coverage agrees http://lab.llvm.org:8080/coverage/coverage-reports/llvm/coverage/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp.html Differential Revision: https://reviews.llvm.org/D67312 llvm-svn: 371431
* [X86] Allow _MM_FROUND_CUR_DIRECTION and _MM_FROUND_NO_EXC to be used ↵Craig Topper2019-09-094-4/+27
| | | | | | | | | | together on instructions that only support SAE and not embedded rounding. Current for SAE instructions we only allow _MM_FROUND_CUR_DIRECTION(bit 2) or _MM_FROUND_NO_EXC(bit 3) to be used as the immediate passed to the inrinsics. But these instructions don't perform rounding so _MM_FROUND_CUR_DIRECTION is just sort of a default placeholder when you don't want to suppress exceptions. Using _MM_FROUND_NO_EXC by itself is really bit equivalent to (_MM_FROUND_NO_EXC | _MM_FROUND_TO_NEAREST_INT) since _MM_FROUND_TO_NEAREST_INT is 0. Since we aren't rounding on these instructions we should also accept (_MM_FROUND_CUR_DIRECTION | _MM_FROUND_NO_EXC) as equivalent to (_MM_FROUND_NO_EXC). icc allows this, but gcc does not. Differential Revision: https://reviews.llvm.org/D67289 llvm-svn: 371430
* [Remarks] Add parser for bitstream remarksFrancis Visoiu Mistrih2019-09-0911-8/+1217
| | | | | | | | | | | | | | | | | | | | | | | | | | The bitstream remark serializer landed in r367372. This adds a bitstream remark parser that parser bitstream remark files to llvm::remarks::Remark objects through the RemarkParser interface. A few interesting things to point out: * There are parsing helpers to parse the different types of blocks * The main parsing helper allows us to parse remark metadata and open an external file containing the encoded remarks * This adds a dependency from the Remarks library to the BitstreamReader library * The testing strategy is to create a remark entry through YAML, parse it, serialize it to bitstream, parse that back and compare the objects. * There are close to no tests for malformed bitstream remarks, due to the lack of textual format for the bitstream format. * This adds a new C API for parsing bitstream remarks: LLVMRemarkParserCreateBitstream. * This bumps the REMARKS_API_VERSION to 1. Differential Revision: https://reviews.llvm.org/D67134 llvm-svn: 371429
* [mips] Fix decoding of microMIPS JALX instructionSimon Atanasyan2019-09-095-6/+25
| | | | | | | | | | | | | microMIPS jump and link exchange instruction stores a target in a 26-bits field. Despite other microMIPS JAL instructions these bits are target address shifted right 2 bits [1]. The patch fixes the JALX instruction decoding and uses 2-bit shift. [1] MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set Differential Revision: https://reviews.llvm.org/D67320 llvm-svn: 371428
* AMDGPU: Move MnemonicAlias out of instruction def hierarchyMatt Arsenault2019-09-097-85/+73
| | | | | | | | | | | | | | | | | | Unfortunately MnemonicAlias defines a "Predicates" field just like an instruction or pattern, with a somewhat different interpretation. This ends up overriding the intended Predicates set by PredicateControl on the pseudoinstruction defintions with an empty list. This allowed incorrectly selecting instructions that should have been rejected due to the SubtargetPredicate from patterns on the instruction definition. This does remove the divergent predicate from the 64-bit shift patterns, which were already not used for the 32-bit shift, so I'm not sure what the point was. This also removes a second, redundant copy of the 64-bit divergent patterns. llvm-svn: 371427
* [SLP] add test for over-vectorization (PR33958); NFCSanjay Patel2019-09-091-0/+16
| | | | llvm-svn: 371426
* [GlobalISel][AArch64] Handle tail calls with non-void return typesJessica Paquette2019-09-093-23/+12
| | | | | | | | | | | | | | | Just return once you emit the call, which is exactly what SelectionDAG does in this situation. Update call-translator-tail-call.ll. Also update dllimport.ll to show that we tail call here in GISel again. Add -verify-machineinstrs to the GISel line too, to defend against verifier failures. Differential revision: https://reviews.llvm.org/D67282 llvm-svn: 371425
* AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUEMatt Arsenault2019-09-099-1/+102
| | | | | | Handle the simple case that lowers to a constant. llvm-svn: 371424
* AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR_TRUNCMatt Arsenault2019-09-095-0/+172
| | | | | | | | | | Treat this as legal on gfx9 since it can use S_PACK_* instructions for this. This isn't used by anything yet. The same will probably apply to 16-bit G_BUILD_VECTOR without the trunc. llvm-svn: 371423
* [clangd] Attempt to fix failing Windows buildbots.Ilya Biryukov2019-09-091-3/+6
| | | | | | | | | The assertion is failing on Windows, probably because path separator is different. For the failure see: http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast/builds/28072/steps/test/logs/stdio llvm-svn: 371422
* Revert "[MachineCopyPropagation] Remove redundant copies after TailDup via ↵Dmitri Gribenko2019-09-094-70/+7
| | | | | | | | | machine-cp" This reverts commit 371359. I'm suspecting a miscompile, I posted a reproducer to https://reviews.llvm.org/D65267. llvm-svn: 371421
* [yaml2obj] Simplify p_filesz/p_memsz computingFangrui Song2019-09-092-28/+39
| | | | | | | | | | | | | | | This fixes a bug as well. When "FileSize:" (p_filesz) is specified and different from the actual value, the following code probably should not use PHeader.p_filesz: if (SHeader->sh_offset == PHeader.p_offset + PHeader.p_filesz) PHeader.p_memsz += SHeader->sh_size; Reviewed By: jhenderson Differential Revision: https://reviews.llvm.org/D67256 llvm-svn: 371420
* [ARM] Fix loads and stores for predicate vectorsDavid Green2019-09-097-775/+3091
| | | | | | | | | | | | | | | | | | | | | | | | These predicate vectors can usually be loaded and stored with a single instruction, a VSTR_P0. However this instruction will store the entire P0 predicate, 16 bits, zeroextended to 32bits. Each lane of the the v4i1/v8i1/v16i1 representing 4/2/1 bits. As far as I understand, when llvm says "store this v4i1", it really does need to store 4 bits (or 8, that being the size of a byte, with this bottom 4 as the interesting bits). For example a bitcast from a v8i1 to a i8 is defined as a store followed by a load, which is how the code is expanded. So this instead lowers the v4i1/v8i1 load/store through some shuffles to get the bits into the correct positions. This, as you might imagine, is not as efficient as a single instruction. But I believe it is needed for correctness. v16i1 equally should not load/store 32bits, only storing the 16bits of data. Stack loads/stores are still using the VSTR_P0 (as can be seen by the test not changing). This is fine as they are self-consistent, it is only "externally observable loads/stores" (from our point of view) that need to be corrected. Differential revision: https://reviews.llvm.org/D67085 llvm-svn: 371419
* AMDGPU/GlobalISel: Select atomic loadsMatt Arsenault2019-09-0910-158/+1014
| | | | | | | A new check for an explicitly atomic MMO is needed to avoid incorrectly matching pattern for non-atomic loads llvm-svn: 371418
* LLDB - Simplify GetProgramFileSpecDavid Carlier2019-09-091-7/+4
| | | | | | | | | | Reviewers: zturner, emaste Reviewed By: emaste Differential Revision: https://reviews.llvm.org/D46518 llvm-svn: 371417
* AMDGPU/GlobalISel: Fix RegBankSelect for unaligned, uniform constant loadsMatt Arsenault2019-09-092-6/+56
| | | | llvm-svn: 371416
* Fix typo in comment noticed in D60295. NFCI.Simon Pilgrim2019-09-091-1/+1
| | | | llvm-svn: 371415
* AMDGPU/GlobalISel: Fix regbankselect for uniform extloadsMatt Arsenault2019-09-092-22/+89
| | | | | | There are no scalar extloads. llvm-svn: 371414
* AMDGPU: Remove code address space predicatesMatt Arsenault2019-09-096-29/+400
| | | | | | | Fixes 8-byte, 8-byte aligned LDS loads. 16-byte case still broken due to not be reported as legal. llvm-svn: 371413
* AMDGPU/GlobalISel: Select G_PTR_MASKMatt Arsenault2019-09-094-0/+545
| | | | llvm-svn: 371412
* AMDGPU/GlobalISel: Fix reg bank for uniform LDS loadsMatt Arsenault2019-09-092-10/+49
| | | | | | | The pointer is always a VGPR. Also fix hardcoding the pointer size to 64. llvm-svn: 371411
* [NFC] Add aacps bitfields access testDiogo N. Sampaio2019-09-091-0/+824
| | | | llvm-svn: 371410
* AMDGPU/GlobalISel: Use known bits for selectionMatt Arsenault2019-09-093-8/+88
| | | | llvm-svn: 371409
* [clangd] Use pre-populated mappings for standard symbolsIlya Biryukov2019-09-097-76/+84
| | | | | | | | | | | | | | | | | | | | Summary: This takes ~5% of time when running clangd unit tests. To achieve this, move mapping of system includes out of CanonicalIncludes and into a separate class Reviewers: sammccall, hokein Reviewed By: sammccall Subscribers: MaskRay, jkorous, arphaman, kadircet, jfb, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D67172 llvm-svn: 371408
* AMDGPU/GlobalISel: Legalize wavefrontsize intrinsicMatt Arsenault2019-09-092-0/+24
| | | | llvm-svn: 371407
* AMDGPU/GlobalISel: Try generated matcher before add/sub codeMatt Arsenault2019-09-091-4/+4
| | | | | | This will allow optimization patterns which fold adds away to work. llvm-svn: 371406
* [ARM] Remove some spurious MVE reduction instructions.Simon Tatham2019-09-093-80/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The family of 'dual-accumulating' vector multiply-add instructions (VMLADAV, VMLALDAV and VRMLALDAVH) can all operate on both signed and unsigned integer types, and they all have an 'exchange' variant (with an X in the name) that modifies which pairs of vector lanes in the two inputs are multiplied together. But there's a clause in the spec that says that the X variants //don't// operate on unsigned integer types, only signed. You can have X, or unsigned, or neither, but not both. We didn't notice that clause when we implemented the MC support for these instructions, so LLVM believes that things like VMLADAVX.U8 do exist, contradicting the spec. Here I fix that by conditioning them out in Tablegen. In order to do that, I've reversed the nesting order of the Tablegen multiclasses for those instructions. Previously, the innermost multiclass generated the X and not-X variants, and the one outside that generated the A and not-A variants. Now X is done by the outer multiclass, which allows me to bypass that one when I only want the two not-X variants. Changing the multiclass nesting order also changes the names of the instruction ids unless I make a special effort not to. I decided that while I was changing them anyway I'd make them look nicer; so now the instructions have names like MVE_VMLADAVs32 or MVE_VMLADAVaxs32, instead of cumbersome _noacc_noexch suffixes. The corresponding multiply-subtract instructions are unaffected. Those don't accept unsigned types at all, either in the spec or in LLVM. Reviewers: ostannard, dmgreen Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67214 llvm-svn: 371405
* AMDGPU/GlobalISel: Remove dead patternsMatt Arsenault2019-09-091-5/+0
| | | | llvm-svn: 371404
* Merge note_ovl_builtin_candidate diagnostics; NFCSven van Haastregt2019-09-092-6/+3
| | | | | | | There is no difference between the unary and binary case, so merge them. llvm-svn: 371403
* [clangd] Add a new highlighting kind for typedefsIlya Biryukov2019-09-094-18/+48
| | | | | | | | | | | | | | | | | | | Summary: We still attempt to highlight them as underlying types, but fallback to the generic 'typedef' highlighting kind if the underlying type is too complicated. Reviewers: hokein Reviewed By: hokein Subscribers: nridge, MaskRay, jkorous, arphaman, kadircet, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D67290 llvm-svn: 371402
* [NFC][InstCombine] Fixup test i added in rL371352.Roman Lebedev2019-09-091-2/+2
| | | | llvm-svn: 371401
* compiler-rt: use fp_t instead of long double, for consistencyEd Maste2019-09-094-4/+4
| | | | | | | | | Most builtins accepting or returning long double use the fp_t typedef. Change the remaining few cases to do so. Differential Revision: https://reviews.llvm.org/D35034 llvm-svn: 371400
* [DFAPacketizer] Reapply: Track resources for packetized instructionsJames Molloy2019-09-095-60/+229
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reapply with fix to reduce resources required by the compiler - use unsigned[2] instead of std::pair. This causes clang and gcc to compile the generated file multiple times faster, and hopefully will reduce the resource requirements on Visual Studio also. This fix is a little ugly but it's clearly the same issue the previous author of DFAPacketizer faced (the previous tables use unsigned[2] rather uglily too). This patch allows the DFAPacketizer to be queried after a packet is formed to work out which resources were allocated to the packetized instructions. This is particularly important for targets that do their own bundle packing - it's not sufficient to know simply that instructions can share a packet; which slots are used is also required for encoding. This extends the emitter to emit a side-table containing resource usage diffs for each state transition. The packetizer maintains a set of all possible resource states in its current state. After packetization is complete, all remaining resource states are possible packetization strategies. The sidetable is only ~500K for Hexagon, but the extra tracking is disabled by default (most uses of the packetizer like MachinePipeliner don't care and don't need the extra maintained state). Differential Revision: https://reviews.llvm.org/D66936 llvm-svn: 371399
* [ELF] nmagic or omagic: don't allocate PT_PHDR or PF_R PT_LOAD for the ↵Fangrui Song2019-09-095-47/+52
| | | | | | | | | | | | | | | | | | | !hasPhdrsCommands case ``` part.phdrs = script->hasPhdrsCommands() ? script->createPhdrs() : createPhdrs(part); ``` createPhdrs() allocates a PT_PHDR and a PF_R PT_LOAD, which will be deleted later in LinkerScript::allocateHeaders, but leave a gap between the program headers and the first section. Don't allocate the segments to avoid the gap. PT_INTERP is likely not needed as well. Reviewed By: ruiu Differential Revision: https://reviews.llvm.org/D67324 llvm-svn: 371398
* [Inliner][NFC] Make test less brittle.Clement Courbet2019-09-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | Summary: This tests inlining size thresholds, but relies on the output of running the full O2 pipeline, making it brittle against changes in unrelated passes. Only run the inlining pass and set thresholds on the test RUN line instead. Found while investigating D60318. Reviewers: RKSimon, qcolombet Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67349 llvm-svn: 371397
* [clang-tidy] Fix bug in bugprone-use-after-move checkYitzhak Mandelbaum2019-09-092-6/+45
| | | | | | | | | | | | | | | | | | | | Summary: The bugprone-use-after-move check exhibits false positives for certain uses of the C++17 if/switch init statements. These false positives are caused by a bug in the ExprSequence calculations. This revision adds tests for the false positives and fixes the corresponding sequence calculation. Reviewers: gribozavr Subscribers: xazax.hun, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D67292 llvm-svn: 371396
* [ARM][MVE] VCTP instruction selectionSam Parker2019-09-092-0/+63
| | | | | | | | Add codegen support for vctp{8,16,32}. Differential Revision: https://reviews.llvm.org/D67344 llvm-svn: 371395
* [clang-doc] sys::fs::F_None -> OF_None. NFCFangrui Song2019-09-092-3/+3
| | | | | | F_None, F_Text and F_Append are kept for compatibility. llvm-svn: 371394
* Revert rL371198 from llvm/trunk: [DFAPacketizer] Track resources for ↵Simon Pilgrim2019-09-095-229/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | packetized instructions This patch allows the DFAPacketizer to be queried after a packet is formed to work out which resources were allocated to the packetized instructions. This is particularly important for targets that do their own bundle packing - it's not sufficient to know simply that instructions can share a packet; which slots are used is also required for encoding. This extends the emitter to emit a side-table containing resource usage diffs for each state transition. The packetizer maintains a set of all possible resource states in its current state. After packetization is complete, all remaining resource states are possible packetization strategies. The sidetable is only ~500K for Hexagon, but the extra tracking is disabled by default (most uses of the packetizer like MachinePipeliner don't care and don't need the extra maintained state). Differential Revision: https://reviews.llvm.org/D66936 ........ Reverted as this is causing "compiler out of heap space" errors on MSVC 2017/19 NDEBUG builds llvm-svn: 371393
* [clangd] Support multifile edits as output of TweaksKadir Cetinkaya2019-09-0915-68/+271
| | | | | | | | | | | | | | | | | | | | Summary: First patch for propogating multifile changes from tweak outputs to LSP WorkspaceEdits. Uses SM to convert tooling::Replacements to TextEdits. Errors out if there are any inconsistencies between the draft version and the version generated the edits. Reviewers: sammccall Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D66637 llvm-svn: 371392
* [clangd] Update clangd-vscode docs to be more user-focused.Sam McCall2019-09-099-56/+131
| | | | | | | | | | | | | | Summary: Relegate "updating the extension" docs to a separate file. Reviewers: hokein, kadircet Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D67092 llvm-svn: 371390
* [ELF][AArch64] Apply some NFC cleanups to AArch64ErrataFix.cppFangrui Song2019-09-091-10/+10
| | | | | | | | Reviewed By: ruiu Differential Revision: https://reviews.llvm.org/D67310 llvm-svn: 371389
* [AArch64][SVE] Implement abs and neg intrinsicsCullen Rhodes2019-09-094-6/+136
| | | | | | | | | | | | | | | | Summary: This patch implements two arithmetic intrinsics: * int_aarch64_sve_abs * int_aarch64_sve_neg testing the support for scalable vector types in intrinsics added in D65930. Reviewed By: greened Differential Revision: https://reviews.llvm.org/D65931 llvm-svn: 371388
* [ARM] Prevent generating NEON stack accesses under MVE.David Green2019-09-091-4/+8
| | | | | | | | | | | | We should not be generating Neon stack loads/stores even for these large registers. No test here because my understanding is we will only generate these QQPR regs for intrinsics and VLDn's. The tests will follow once those are available. Differential revision: https://reviews.llvm.org/D67169 llvm-svn: 371386
* GlobalISel: fix unused warnings in release builds.Tim Northover2019-09-091-0/+4
| | | | llvm-svn: 371385
* GlobalISel: add combiner to form indexed loads.Tim Northover2019-09-0912-20/+561
| | | | | | | | | | | Loosely based on DAGCombiner version, but this part is slightly simpler in GlobalIsel because all address calculation is performed by G_GEP. That makes the inc/dec distinction moot so there's just pre/post to think about. No targets can handle it yet so testing is via a special flag that overrides target hooks. llvm-svn: 371384
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