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llvm-svn: 125275
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llvm-svn: 125274
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llvm-svn: 125273
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llvm-svn: 125272
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gep to explicit addressing, we know that none of the intermediate
computation overflows.
This could use review: it seems that the shifts certainly wouldn't
overflow, but could the intermediate adds overflow if there is a
negative index?
Previously the testcase would instcombine to:
define i1 @test(i64 %i) {
%p1.idx.mask = and i64 %i, 4611686018427387903
%cmp = icmp eq i64 %p1.idx.mask, 1000
ret i1 %cmp
}
now we get:
define i1 @test(i64 %i) {
%cmp = icmp eq i64 %i, 1000
ret i1 %cmp
}
llvm-svn: 125271
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for NSW/NUW binops to follow the pattern of exact binops. This
allows someone to use Builder.CreateAdd(x, y, "tmp", MaybeNUW);
llvm-svn: 125270
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stack changes.
llvm-svn: 125269
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linkage into Decl.cpp. Disable this logic for extern "C" functions, because
the operative rule there is weaker. Fixes rdar://problem/8898466
llvm-svn: 125268
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exact/nsw/nuw shifts and have instcombine infer them when it can prove
that the relevant properties are true for a given shift without them.
Also, a variety of refactoring to use the new patternmatch logic thrown
in for good luck. I believe that this takes care of a bunch of related
code quality issues attached to PR8862.
llvm-svn: 125267
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optimizations to be much more aggressive in the face of
exact/nsw/nuw div and shifts. For example, these (which
are the same except the first is 'exact' sdiv:
define i1 @sdiv_icmp4_exact(i64 %X) nounwind {
%A = sdiv exact i64 %X, -5 ; X/-5 == 0 --> x == 0
%B = icmp eq i64 %A, 0
ret i1 %B
}
define i1 @sdiv_icmp4(i64 %X) nounwind {
%A = sdiv i64 %X, -5 ; X/-5 == 0 --> x == 0
%B = icmp eq i64 %A, 0
ret i1 %B
}
compile down to:
define i1 @sdiv_icmp4_exact(i64 %X) nounwind {
%1 = icmp eq i64 %X, 0
ret i1 %1
}
define i1 @sdiv_icmp4(i64 %X) nounwind {
%X.off = add i64 %X, 4
%1 = icmp ult i64 %X.off, 9
ret i1 %1
}
This happens when you do something like:
(ptr1-ptr2) == 42
where the pointers are pointers to non-unit types.
llvm-svn: 125266
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conversions". :)
llvm-svn: 125265
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and generally tidying things up. Only very trivial functionality changes
like now doing (-1 - A) -> (~A) for vectors too.
InstCombineAddSub.cpp | 296 +++++++++++++++++++++-----------------------------
1 file changed, 126 insertions(+), 170 deletions(-)
llvm-svn: 125264
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are shifting out since they do require them to be zeros. Similarly
for NUW/NSW bits of shl
llvm-svn: 125263
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llvm-svn: 125262
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managed by ExplodedNodes.
This reduces memory usage of the analyzer on sqlite by another 5%.
llvm-svn: 125260
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add a missing check when considering whether it's profitable to commute. rdar://8977508.
llvm-svn: 125259
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g_thumb_opcodes table,
and a helper method UnalignedSupport().
llvm-svn: 125258
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llvm-svn: 125257
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llvm-svn: 125256
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input reader.
Always make sure the input reader stack is not empty before
trying to get the top element from the stack.
llvm-svn: 125255
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Natural Loop Information
Loop Pass Manager
Canonicalize natural loops
Scalar Evolution Analysis
Loop Pass Manager
Induction Variable Users
Canonicalize natural loops
Induction Variable Users
Loop Strength Reduction
into this:
Scalar Evolution Analysis
Loop Pass Manager
Canonicalize natural loops
Induction Variable Users
Loop Strength Reduction
This fixes <rdar://problem/8869639>. I also filed PR9184 on doing this sort of
thing automatically, but it seems easier to just change the ordering of the
passes if this is the only case.
llvm-svn: 125254
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corresponding headers.
This is a hack because we really should only search in the 'include/clang/StaticAnalyzer' directory
if we are in 'lib/StaticAnalyzer'. My CMake knowledge is limited, so I appeal to anyone with
more expertise.
llvm-svn: 125252
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'include/clang/StaticAnalyzer/Core' and 'include/clang/StaticAnalyzer/Checkers'.
This layout matches lib/StaticAnalyzer, which corresponds to two StaticAnalyzer libraries.
llvm-svn: 125251
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llvm-svn: 125250
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this.
llvm-svn: 125249
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When matching operands for a candidate opcode match in the auto-generated
AsmMatcher, check each operand against the expected operand match class.
Previously, operands were classified independently of the opcode being
handled, which led to difficulties when operand match classes were
more complicated than simple subclass relationships.
llvm-svn: 125245
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of the CPSR during the course of executing an opcode, and modified SelectInstrSet()
to update this variable instead of the original m_inst_cpsr, which should be
the cached copy of the CPSR at the beginning of executing the opcode.
llvm-svn: 125244
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Loop splitting is better handled by the more generic global region splitting
based on the edge bundle graph.
llvm-svn: 125243
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table,
and a helper method ALUWritePC(Context&, uint32_t).
llvm-svn: 125241
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indirect forms, deals with empty DW_AT_comp_dir attributes, and fixups for
handling other signed integer types.
llvm-svn: 125240
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I have another way to achieve the same goal.
llvm-svn: 125239
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llvm-svn: 125238
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This fixes a bug where splitSingleBlocks() could split a live range after a
terminator instruction.
llvm-svn: 125237
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llvm-svn: 125236
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llvm-svn: 125235
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llvm-svn: 125232
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No functional changes intended.
llvm-svn: 125231
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llvm-svn: 125230
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warning when same parameter name used multiple times.
// rdar://8877730
llvm-svn: 125229
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name of a path, after resolving symbolic links and eliminating excess
path elements such as "foo/../" and "./".
This routine still needs a Windows implementation, but I don't have a
Windows machine available. Help? Please?
llvm-svn: 125228
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appropriate to
effect an interworking branch if the ArchVersion() is ARMv5T and above.
llvm-svn: 125227
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llvm-svn: 125226
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llvm-svn: 125225
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The tag is updated whenever the live interval union is changed, and it is tested
before using cached information.
llvm-svn: 125224
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llvm-svn: 125220
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llvm-svn: 125219
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llvm-svn: 125218
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llvm-svn: 125217
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llvm-svn: 125216
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Now, Syntax is only used as a tie-breaker if the Arch
matches. Previously, a request for x86_64 disassembler followed by the
i386 disassembler in a single process would return the cached x86_64
disassembler. Fixes <rdar://problem/8958982>
llvm-svn: 125215
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