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* Simplify code in mangler.Eli Friedman2013-07-011-6/+2
| | | | llvm-svn: 185384
* Debug Info: clean up usage of Verify.Manman Ren2013-07-012-17/+19
| | | | | | | No functionality change. It should suffice to check the type of a debug info metadata, instead of calling Verify. llvm-svn: 185383
* Recognize "decltype(nullptr)" as a valid DW_AT_name for ↵Greg Clayton2013-07-011-1/+2
| | | | | | DW_TAG_unspecified_type tags as meaning the C++11 null pointer type. llvm-svn: 185382
* Simplify linkage code for static local vars.Eli Friedman2013-07-014-56/+5
| | | | | | | | | The key insight here is that weak linkage for a static local variable should always mean linkonce_odr, because every file that needs it will generate a definition. We don't actually care about the precise linkage of the parent context. I feel a bit silly that I didn't realize this before. llvm-svn: 185381
* Index: test/CodeGen/PowerPC/reloc-align.llBill Schmidt2013-07-013-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | =================================================================== --- test/CodeGen/PowerPC/reloc-align.ll (revision 0) +++ test/CodeGen/PowerPC/reloc-align.ll (revision 0) @@ -0,0 +1,34 @@ +; RUN: llc -mcpu=pwr7 -O1 < %s | FileCheck %s + +; This test verifies that the peephole optimization of address accesses +; does not produce a load or store with a relocation that can't be +; satisfied for a given instruction encoding. Reduced from a test supplied +; by Hal Finkel. + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.S1 = type { [8 x i8] } + +@main.l_1554 = internal global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 -1, i8 -6, i8 57, i8 62, i8 -48, i8 0, i8 58, i8 80 }, align 1 + +; Function Attrs: nounwind readonly +define signext i32 @main() #0 { +entry: + %call = tail call fastcc signext i32 @func_90(%struct.S1* byval bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*)) +; CHECK-NOT: ld {{[0-9]+}}, main.l_1554@toc@l + ret i32 %call +} + +; Function Attrs: nounwind readonly +define internal fastcc signext i32 @func_90(%struct.S1* byval nocapture %p_91) #0 { +entry: + %0 = bitcast %struct.S1* %p_91 to i64* + %bf.load = load i64* %0, align 1 + %bf.shl = shl i64 %bf.load, 26 + %bf.ashr = ashr i64 %bf.shl, 54 + %bf.cast = trunc i64 %bf.ashr to i32 + ret i32 %bf.cast +} + +attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } Index: lib/Target/PowerPC/PPCAsmPrinter.cpp =================================================================== --- lib/Target/PowerPC/PPCAsmPrinter.cpp (revision 185327) +++ lib/Target/PowerPC/PPCAsmPrinter.cpp (working copy) @@ -679,7 +679,26 @@ void PPCAsmPrinter::EmitInstruction(const MachineI OutStreamer.EmitRawText(StringRef("\tmsync")); return; } + break; + case PPC::LD: + case PPC::STD: + case PPC::LWA: { + // Verify alignment is legal, so we don't create relocations + // that can't be supported. + // FIXME: This test is currently disabled for Darwin. The test + // suite shows a handful of test cases that fail this check for + // Darwin. Those need to be investigated before this sanity test + // can be enabled for those subtargets. + if (!Subtarget.isDarwin()) { + unsigned OpNum = (MI->getOpcode() == PPC::STD) ? 2 : 1; + const MachineOperand &MO = MI->getOperand(OpNum); + if (MO.isGlobal() && MO.getGlobal()->getAlignment() < 4) + llvm_unreachable("Global must be word-aligned for LD, STD, LWA!"); + } + // Now process the instruction normally. + break; } + } LowerPPCMachineInstrToMCInst(MI, TmpInst, *this); OutStreamer.EmitInstruction(TmpInst); Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp =================================================================== --- lib/Target/PowerPC/PPCISelDAGToDAG.cpp (revision 185327) +++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp (working copy) @@ -1530,6 +1530,14 @@ void PPCDAGToDAGISel::PostprocessISelDAG() { if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) { SDLoc dl(GA); const GlobalValue *GV = GA->getGlobal(); + // We can't perform this optimization for data whose alignment + // is insufficient for the instruction encoding. + if (GV->getAlignment() < 4 && + (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD || + StorageOpcode == PPC::LWA)) { + DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n"); + continue; + } ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags); } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(ImmOpnd)) { llvm-svn: 185380
* [ARMAsmParser] Sort the ARM register lists based on the encoding value, not theChad Rosier2013-07-013-36/+44
| | | | | | tablegen enum values. This should be the last fix due to fallout from r185094. llvm-svn: 185379
* Make PBQP require/preserve MachineLoopInfo - the spiller requires it.Lang Hames2013-07-011-0/+3
| | | | llvm-svn: 185378
* [docs] Amend confusing titleSean Silva2013-07-011-3/+3
| | | | | | | | | | "Writing an LLVM Compiler Backend" can be misinterpreted as meaning "backend" in the sense of "using LLVM as a backend for your compiler for your new language". This new name is less ambiguous. As a bonus, this brings the title in line with the file name. llvm-svn: 185377
* [mips] Reverse the order of source operands of shift and rotate instructions ↵Akira Hatanaka2013-07-012-8/+8
| | | | | | | | | | that have three register operands. No intended functionality changes. llvm-svn: 185376
* [PowerPC] Also add "msync" aliasUlrich Weigand2013-07-012-0/+3
| | | | | | | This adds an alias for "msync" (which is used on Book E systems instead of "sync"). llvm-svn: 185375
* Fix CMakeLists.txt.Eli Friedman2013-07-011-1/+1
| | | | | | Sorry about that. llvm-svn: 185374
* [mips] Increase the number of floating point control registers available to 32.Akira Hatanaka2013-07-015-20/+25
| | | | | | | Create a dedicated register class for floating point condition code registers and move FCC0 from register class CCR to the new register class. llvm-svn: 185373
* Fix mangling for block literals.Eli Friedman2013-07-0115-170/+304
| | | | | | | | | | | | | | | Blocks, like lambdas, can be written in contexts which are required to be treated as the same under ODR. Unlike lambdas, it isn't possible to actually take the address of a block, so the mangling of the block itself doesn't matter. However, objects like static variables inside a block do need to be mangled in a consistent way. There are basically three components here. One, block literals need a consistent numbering. Two, objects/types inside a block literal need to be mangled using it. Three, objects/types inside a block literal need to have their linkage computed correctly. llvm-svn: 185372
* [mips] Fix test case to check that mips64 instructions are generated.Akira Hatanaka2013-07-011-4/+4
| | | | llvm-svn: 185371
* Really fix the test. Sorry for the breakage...Anton Korobeynikov2013-07-011-1/+1
| | | | llvm-svn: 185369
* Fix the test which relies on uncommitted changeAnton Korobeynikov2013-07-011-1/+1
| | | | llvm-svn: 185368
* Fix the build after r185363. Use llvm::next instead of raw next.Cameron Zwarich2013-07-011-1/+1
| | | | llvm-svn: 185367
* Split symbol support for ELF and Linux.Michael Sartain2013-07-0138-494/+1452
| | | | llvm-svn: 185366
* Add jump tables handling for MSP430.Anton Korobeynikov2013-07-013-0/+65
| | | | | | Patch by Job Noorman! llvm-svn: 185364
* Fix PR16508.Cameron Zwarich2013-07-012-4/+36
| | | | | | | | | | | | When phis get lowered, destination copies are inserted using an iterator that is determined once for all phis in the block, which BuildMI interprets as a request to insert an instruction directly before the iterator. In the case of a cyclic phi, source copies may also be inserted directly before this iterator, which can cause source copies to be inserted before destination copies. The fix is to keep an iterator to the last phi and then advance it while lowering each phi in order to insert destination copies directly after the phis. llvm-svn: 185363
* Fix MSP430 builtin types.Anton Korobeynikov2013-07-013-13/+13
| | | | | | Patch by Job Noorman! llvm-svn: 185362
* Don't form PPC CTR loops for over-sized exit countsHal Finkel2013-07-012-0/+26
| | | | | | | | | | Although you can't generate this from C on PPC64, if you have a loop using a 64-bit counter on PPC32 then you can't form a CTR-based loop for it. This had been cauing the PPCCTRLoops pass to assert. Thanks to Joerg Sonnenberger for providing a test case! llvm-svn: 185361
* AArch64: correct CodeGen of MOVZ/MOVK combinations.Tim Northover2013-07-014-17/+36
| | | | | | | | | | | | According to the AArch64 ELF specification (4.6.8), it's the assembler's responsibility to make sure the shift amount is correct in relocated MOVZ/MOVK instructions. This wasn't being obeyed by either the MCJIT CodeGen or RuntimeDyldELF (which happened to work out well for JIT tests). This commit should make us compliant in this area. llvm-svn: 185360
* (1) Add ".test" to test/Other/lit.local.cfg, so llvm-cov.test is actually run.Matt Beaumont-Gay2013-07-014-3/+3
| | | | | | | | | (2) Rename llvm-cov test inputs so the string "llvm-cov" doesn't get substituted by lit within the input filenames on the RUN line. (3) XFAIL llvm-cov.test because it asserts: include/llvm/ADT/SmallVector.h:140: reference llvm::SmallVectorTemplateCommon<llvm::GCOVBlock *, void>::operator[](unsigned int) [T = llvm::GCOVBlock *]: Assertion `begin() + idx < end()' failed. llvm-svn: 185358
* Formatting cleanup.Jim Ingham2013-07-011-3/+10
| | | | llvm-svn: 185357
* Revert r185339 (ARM: relax the atomic release barrier to "dmb ishst")Tim Northover2013-07-013-95/+57
| | | | | | | | | Turns out I'd misread the architecture reference manual and thought that was a load/store-store barrier, when it's not. Thanks for pointing it out Eli! llvm-svn: 185356
* Debug Info: Scope of a DebugLoc should not be null.Manman Ren2013-07-011-6/+3
| | | | | | No functionality change. Remove handling for the null case. llvm-svn: 185354
* [PowerPC] Fix @got references to local symbolsUlrich Weigand2013-07-012-0/+80
| | | | | | | | | | | A @got reference must always result in a relocation, so that the linker has a chance to set up the GOT entry, even if the symbol happens to be local. Add a PPCELFObjectWriter::ExplicitRelSym routine that enforces a relocation to be emitted for GOT references. llvm-svn: 185353
* Implement n3656 - make_unique. Thanks to Howard for the review and suggestions.Marshall Clow2013-07-017-0/+191
| | | | llvm-svn: 185352
* [PowerPC] Add "wait" instructionUlrich Weigand2013-07-012-4/+15
| | | | | | This adds the "wait" instruction and its extended mnemonics. llvm-svn: 185350
* [PowerPC] Support "eieio" instructionUlrich Weigand2013-07-013-1/+11
| | | | | | | This adds support for the "eieio" instruction to the asm parser. llvm-svn: 185349
* Added c++ mode selector to head of SelectionDAGBuilder.h so editors open it ↵Michael Gottesman2013-07-011-1/+1
| | | | | | in c++ mode instead of c mode. llvm-svn: 185348
* [PowerPC] Add some existing instructions to ppc64-encoding-bookII.sUlrich Weigand2013-07-011-3/+8
| | | | | | | | | | The test case had a couple of FIXMEs where the instruction is in fact already supported by the back-end. In some other case, while the generic form of the instruction is not yet supported, a specialized form is. This adds tests for those already supported instructions / instruction forms. llvm-svn: 185347
* Fix incorrect token counting introduced by r185319.Daniel Jasper2013-07-012-1/+4
| | | | | | | | | | | | This lead to weird formatting. Before: DoSomethingWithVector({ {} /* No data */ }, { { 1, 2 } }); After: DoSomethingWithVector({ {} /* No data */ }, { { 1, 2 } }); llvm-svn: 185346
* [ASan] try to fix Windows buildAlexey Samsonov2013-07-011-2/+2
| | | | llvm-svn: 185345
* [PowerPC] Add variants of "sync" instructionUlrich Weigand2013-07-013-9/+19
| | | | | | | This adds support for the "sync $L" instruction with operand, and provides aliases for "lwsync" and "ptesync". llvm-svn: 185344
* Implement n3658 - Compile-time integer sequencesMarshall Clow2013-07-017-0/+331
| | | | llvm-svn: 185343
* [ASan] Properly disable strict init-order checking when pthread_create is calledAlexey Samsonov2013-07-013-7/+38
| | | | llvm-svn: 185342
* [msan] Intercept stpcpy.Evgeniy Stepanov2013-07-012-0/+22
| | | | llvm-svn: 185340
* ARM: relax the atomic release barrier to "dmb ishst"Tim Northover2013-07-013-57/+95
| | | | | | | | | | | I believe the full "dmb ish" barrier is not required to guarantee release semantics for atomic operations. The weaker "dmb ishst" prevents previous operations being reordered with a store executed afterwards, which is enough. A key point to note (fortunately already correct) is that this barrier alone is *insufficient* for sequential consistency, no matter how liberally placed. llvm-svn: 185339
* [sanitizer] Intercept getnameinfo.Evgeniy Stepanov2013-07-015-0/+46
| | | | llvm-svn: 185338
* Avoid column limit violation in block comments in certain cases.Alexander Kornienko2013-07-012-4/+27
| | | | | | | | | | | | | | | | | Summary: Add penalty when an excessively long line in a block comment can not be broken on a leading whitespace. Lack of this addition can lead to severe column width violations when they can be easily avoided. Reviewers: djasper Reviewed By: djasper CC: cfe-commits, klimek Differential Revision: http://llvm-reviews.chandlerc.com/D1071 llvm-svn: 185337
* [NVPTX] Add support for module-scope inline asmJustin Holewinski2013-07-012-0/+20
| | | | | | | Since we were explicitly not calling AsmPrinter::doInitialization, any module-scope inline asm was not being printed. llvm-svn: 185336
* [NVPTX] We dont use NVBuiltin anymoreJustin Holewinski2013-07-012-3/+0
| | | | llvm-svn: 185335
* [NVPTX] Cut down on physical register defsJustin Holewinski2013-07-013-28/+13
| | | | | | | | We are using virtual registers throughout now, but we still need to keep a few physical registers per class around to keep the infrastructure happy. llvm-svn: 185334
* [NVPTX] 64-bit ADDC/ADDE are not legalJustin Holewinski2013-07-012-0/+22
| | | | llvm-svn: 185333
* [NVPTX] Fix vector loads from parameters that span multiple loads, and fix ↵Justin Holewinski2013-07-013-156/+22
| | | | | | some typos llvm-svn: 185332
* [NVPTX] Handle signext/zeroext attributes properlyJustin Holewinski2013-07-012-19/+41
| | | | | | | | Fix a case where we were incorrectly sign-extending a value when we should have been zero-extending the value. Also change some SIGN_EXTEND to ANY_EXTEND because we really dont care and may have more opportunity to fold subexpressions llvm-svn: 185331
* [NVPTX] Add support for native SIGN_EXTEND_INREG where availableJustin Holewinski2013-07-013-4/+143
| | | | llvm-svn: 185330
* [NVPTX] Add isel patterns for [reg+offset] form of ldg/ldu.Justin Holewinski2013-07-013-112/+451
| | | | llvm-svn: 185329
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