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* Remove unnecessary indirection. No behavior change.Nico Weber2018-04-301-12/+6
| | | | llvm-svn: 331176
* [mips] Fix the predicates of jump and branch and link instructionsSimon Dardis2018-04-304-51/+69
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D46114 llvm-svn: 331175
* [LV] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC).Florian Hahn2018-04-301-8/+3
| | | | | | | | | | | | | | This patch updates some code responsible the skip debug info to use BasicBlock::instructionsWithoutDebug. I think this makes things slightly simpler and more direct. Reviewers: mkuper, rengolin, dcaballe, aprantl, vsk Reviewed By: rengolin Differential Revision: https://reviews.llvm.org/D46254 llvm-svn: 331174
* ObjectFileELF: Add support for arbitrarily named code sectionsPavel Labath2018-04-305-0/+73
| | | | | | | | | | | | | | | | | | | ObjectFileELF assumes that code section has ".text" name. There is an exception for kalimba toolchain that can use arbitrary names, but other toolchains also could use arbitrary names for code sections. For example, corert uses separate section for compiled managed code. As lldb doesn't recognize such section it leads to problem with breakpoints on arm, because debugger cannot determine instruction set (arm/thumb) and uses incorrect breakpoint opcode that breaks program execution. This change allows debugger to correctly handle such code sections. We assume that section is a code section if it has SHF_EXECINSTR flag set and has SHT_PROGBITS type. Patch by Konstantin Baladurin <k.baladurin@partner.samsung.com>. Differential Revision: https://reviews.llvm.org/D44998 llvm-svn: 331173
* Fixup r331049 (FileSpec auto-normalization)Pavel Labath2018-04-302-11/+5
| | | | | | | | | | | | | | | | | | A typo in the patch (using syntax instead of m_syntax) resulted in the normalization not working properly for windows filespecs when the syntax was passed as host-native. This did not affect the unit tests, as all of those pass an explicity syntax, but failed gloriously when running the full test suite. I also fix an expectation in an lldb-mi test, which was now failing because it was expecting a path to be echoed verbatim, but we were now normalizing it. As a drive-by, this also fixes the default-in-fully-covered-switch warning and removes an unused argument from the NeedsNormalization function. llvm-svn: 331172
* [bindings] Fix dibuilder go bindings after r331114.Benjamin Kramer2018-04-301-7/+7
| | | | llvm-svn: 331171
* [llvm-mca] Regenerate test Atom/resources-sse3.s. NFCAndrea Di Biagio2018-04-301-47/+41
| | | | | | Before this change, it wrongly specified -mcpu=slm instead of -mcpu=atom. llvm-svn: 331170
* [llvm-mca] Support for in-order CPU for -instruction-tables testing.Andrea Di Biagio2018-04-308-1/+3788
| | | | | | | | | Added Intel Atom tests to verify that the tool correctly generates instruction tables even if the CPU is in-order. Fixes PR37282. llvm-svn: 331169
* [clangd] Also use UTF-16 in index position.Haojian Wu2018-04-302-7/+12
| | | | | | | | | | Reviewers: sammccall Subscribers: klimek, ilya-biryukov, ioeric, MaskRay, jkorous, cfe-commits Differential Revision: https://reviews.llvm.org/D46258 llvm-svn: 331168
* [X86] Fix typo in skylake-avx512 model for PMAXSD/PMINSD instructionsSimon Pilgrim2018-04-301-20/+20
| | | | | | The PMAXSD/PMINSD instregexs had been written as PMAX(C?)SD - looks like this was a search+replace error when matching float MAXSD/MINSD commutative instructions. llvm-svn: 331167
* NFC - Typo fixes lib/VMCore -> lib/IRGabor Buella2018-04-302-2/+2
| | | | llvm-svn: 331166
* [mips] Fix microMIPS loads and stores.Simon Dardis2018-04-306-41/+1565
| | | | | | | | | | | Previously these instructions were unselectable and instead were generated through the instruction mapping tables. Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46055 llvm-svn: 331165
* [Targets] Implement getConstraintRegister for ARM and AArch64Mikhail Maltsev2018-04-305-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The getConstraintRegister method is used by semantic checking of inline assembly statements in order to diagnose conflicts between clobber list and input/output lists. Currently ARM and AArch64 don't override getConstraintRegister, so conflicts between registers assigned to variables in asm labels and clobber lists are not diagnosed. Such conflicts can cause assertion failures in the back end and even miscompilations. This patch implements getConstraintRegister for ARM and AArch64 targets. Since these targets don't have single-register constraints, the implementation is trivial and just returns the register specified in an asm label (if any). Reviewers: eli.friedman, javed.absar, thopre Reviewed By: thopre Subscribers: rengolin, eraman, rogfer01, myatsina, kristof.beyls, cfe-commits, chrib Differential Revision: https://reviews.llvm.org/D45965 llvm-svn: 331164
* tsan: disable trace switching after multithreaded forkDmitry Vyukov2018-04-302-0/+6
| | | | | | | | | | | | The problem is reported in: https://github.com/google/sanitizers/issues/945 We already disable as much as possible after multithreaded fork, trace switching is last place that can hang due to basic operations (memory accesses, function calls). Disable it too. llvm-svn: 331163
* [AArch64][SVE] Asm: Improve diagnostics for gather loads.Sander de Smalen2018-04-3013-55/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch extends the 'isSVEVectorRegWithShiftExtend' function to improve diagnostics for SVE's gather load (scalar + vector) addressing modes. Instead of always suggesting the 'unscaled' addressing mode, the use of DiagnosticPredicate enables a more specific error message in the context where the scaling is incorrect. For example: ld1h z0.d, p0/z, [x0, z0.d, lsl #2] ^ shift amount should be '1' Instead of suggesting the packed, unscaled addressing mode: expected 'z[0..31].d, (uxtw|sxtw)' the assembler now suggests using the proper scaling: expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D46124 llvm-svn: 331162
* [X86] Add a Requires<[In64BitMode]> to FARJMP64Craig Topper2018-04-303-2/+5
| | | | | | Otherwise we can try to assemble it in 32-bit mode and throw an assert in the encoder. llvm-svn: 331161
* [X86] Hide another instruction from the assembly matcher table to avoid a ↵Craig Topper2018-04-301-0/+1
| | | | | | duplicate entry. NFC llvm-svn: 331160
* [X86] Remove some InstAliases aren't needed because a MnemonicAlias makes ↵Craig Topper2018-04-301-3/+0
| | | | | | them unreachable. llvm-svn: 331159
* [X86] Remove some instructions from the Intel assembly matcher table as ↵Craig Topper2018-04-301-2/+2
| | | | | | | | | | there are equivalent mode aware InstAliases that conflict. The instructions have predicates of Not64BitMode, but there are identical strings in InstAliases that have Mode32Bit and Mode16Bit. But the ordering is uncontrolled and the less specific Not64BitMode was ordered first. This patch hides the Not64BitMode from the table so there is no conflict anymore. llvm-svn: 331158
* [X86] Use a MnemonicAlias instead of an InstAlias.Craig Topper2018-04-302-9/+8
| | | | llvm-svn: 331157
* Fix up after clang r331155.Richard Smith2018-04-306-12/+16
| | | | llvm-svn: 331156
* PR37189 Fix incorrect end source location and spelling for a split '>>' token.Richard Smith2018-04-3035-216/+379
| | | | | | | | | | | | | | | | | | When a '>>' token is split into two '>' tokens (in C++11 onwards), or (as an extension) when we do the same for other tokens starting with a '>', we can't just use a location pointing to the first '>' as the location of the split token, because that would result in our miscomputing the length and spelling for the token. As a consequence, for example, a refactoring replacing 'A<X>' with something else would sometimes replace one character too many, and similarly diagnostics highlighting a template-id source range would highlight one character too many. Fix this by creating an expansion range covering the first character of the '>>' token, whose spelling is '>'. For this to work, we generalize the expansion range of a macro FileID to be either a token range (the common case) or a character range (used in this new case). llvm-svn: 331155
* [X86] Remove support for accepting 'fnstsw %eax' and 'fnstsw %al'.Craig Topper2018-04-303-12/+1
| | | | | | I assume this was done because gas accepted it at one point, but current versions of gas don't. llvm-svn: 331154
* [X86] Mark some more InstAliases as 'att' syntax only.Craig Topper2018-04-301-6/+6
| | | | | | These aliases are used to default the memory forms of call and jmp to the size of the operating mode. This doesn't work for Intel syntax. We have a different hack in the AsmParser code itself to force a size on unsized memory operands. llvm-svn: 331153
* Rename DiagnosticClient to DiagnosticConsumer as per issue 5397.Fangrui Song2018-04-302-9/+9
| | | | llvm-svn: 331152
* Remove a dead #ifdef.Nico Weber2018-04-301-2/+0
| | | | | | | Unix/Threading.inc should never be included on _WIN32. See also https://reviews.llvm.org/D30526#1082292 llvm-svn: 331151
* Move _LIBCPP_ENABLE_CXX17_REMOVED_UNEXPECTED_FUNCTIONS macro to build systemNico Weber2018-04-293-7/+4
| | | | | | | | | | | | | | | _LIBCPP_ENABLE_CXX17_REMOVED_UNEXPECTED_FUNCTIONS is currently used to bring back std::unexpected, which is removed in C++17, but still needed for libc++abi for backward compatibility. This macro used to define in cxa_exception.cpp only, but actually needed for all sources that touches exceptions. So, a build-system-level macro is better fit to define this macro. https://reviews.llvm.org/D46056 Patch from Taiju Tsuiku <tzik@chromium.org>! llvm-svn: 331150
* [X86] Make 64-bit sysret/sysexit not ambiguous in Intel assembly syntax.Craig Topper2018-04-292-2/+11
| | | | | | This also makes it default to the 32-bit non REX.W version in 64-bit mode. This seems to be more consistent with gas. llvm-svn: 331149
* Support reading section ".gnu_debugaltlink"Jan Kratochvil2018-04-2914-5/+51
| | | | | | Differential revision: https://reviews.llvm.org/D40468 llvm-svn: 331148
* [X86] Remove unnecessary BT InstRW overrides.Simon Pilgrim2018-04-291-5/+1
| | | | llvm-svn: 331147
* [AArch64][AsmParser] NFC: Cleanup of addOperands functionsSander de Smalen2018-04-294-230/+81
| | | | | | | | | | | | | | | | Most of the add<operandname>Operands() functions are the same and can be replaced by using a single 'RenderMethod' in the AArch64InstrFormats.td file. Since many of the scaled immediates (with different scaling/bits) are the same, most of these can reuse the same AsmOperandClass. Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: samparker Differential Revision: https://reviews.llvm.org/D46122 llvm-svn: 331146
* [AArch64][SVE] Asm: Support for gather LD1/LDFF1 (vector + imm) load ↵Sander de Smalen2018-04-2932-4/+1020
| | | | | | | | | | | | instructions. Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46120 llvm-svn: 331145
* [llvm-mca][X86] Add BT resource tests to all modelsSimon Pilgrim2018-04-298-8/+1184
| | | | llvm-svn: 331144
* [X86] Merge more instregex single matches to reduce InstrRW compile time.Simon Pilgrim2018-04-296-393/+195
| | | | llvm-svn: 331143
* [X86] Remove unnecessary add/adc+sub/sbb InstRW overrides.Simon Pilgrim2018-04-291-9/+0
| | | | llvm-svn: 331142
* [XRay][profiler] Part 1: XRay Allocator and Array ImplementationsDean Michael Berris2018-04-296-16/+711
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change is part of the larger XRay Profiling Mode effort. Here we implement an arena allocator, for fixed sized buffers used in a segmented array implementation. This change adds the segmented array data structure, which relies on the allocator to provide and maintain the storage for the segmented array. Key features of the `Allocator` type: * It uses cache-aligned blocks, intended to host the actual data. These blocks are cache-line-size multiples of contiguous bytes. * The `Allocator` has a maximum memory budget, set at construction time. This allows us to cap the amount of data each specific `Allocator` instance is responsible for. * Upon destruction, the `Allocator` will clean up the storage it's used, handing it back to the internal allocator used in sanitizer_common. Key features of the `Array` type: * Each segmented array is always backed by an `Allocator`, which is either user-provided or uses a global allocator. * When an `Array` grows, it grows by appending a segment that's fixed-sized. The size of each segment is computed by the number of elements of type `T` that can fit into cache line multiples. * An `Array` does not return memory to the `Allocator`, but it can keep track of the current number of "live" objects it stores. * When an `Array` is destroyed, it will not return memory to the `Allocator`. Users should clean up the `Allocator` independently of the `Array`. * The `Array` type keeps a freelist of the chunks it's used before, so that trimming and growing will re-use previously allocated chunks. These basic data structures are used by the XRay Profiling Mode implementation to implement efficient and cache-aware storage for data that's typically read-and-write heavy for tracking latency information. We're relying on the cache line characteristics of the architecture to provide us good data isolation and cache friendliness, when we're performing operations like searching for elements and/or updating data hosted in these cache lines. Reviewers: echristo, pelikan, kpw Subscribers: mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D45756 llvm-svn: 331141
* [llvm-mca][X86] Add add/adc + sub/sbb resource tests to all modelsSimon Pilgrim2018-04-298-8/+3016
| | | | llvm-svn: 331140
* [NFC][LV][LoopUtil] Move LoopVectorizationLegality to its own fileHideki Saito2018-04-294-1456/+1557
| | | | | | | | | | | | | | | | | | | | | Summary: This is a follow up to D45420 (included here since it is still under review and this change is dependent on that) and D45072 (committed). Actual change for this patch is LoopVectorize* and cmakefile. All others are all from D45420. LoopVectorizationLegality is an analysis and thus really belongs to Analysis tree. It is modular enough and it is reusable enough ---- we can further improve those aspects once uses outside of LV picks up. Hopefully, this will make it easier for people familiar with vectorization theory, but not necessarily LV itself to contribute, by lowering the volume of code they should deal with. We probably should start adding some code in LV to check its own capability (i.e., vectorization is legal but LV is not ready to handle it) and then bail out. Reviewers: rengolin, fhahn, hfinkel, mkuper, aemerson, mssimpso, dcaballe, sguggill Reviewed By: rengolin, dcaballe Subscribers: egarcia, rogfer01, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D45552 llvm-svn: 331139
* [X86] Add suffixes to the LGDT/LIDT/SGDT/SIDT mnemonics in Intel syntax. Add ↵Craig Topper2018-04-293-12/+39
| | | | | | | | | | aliases based on 16/32-bit mode to choose the default. This allows the instruction selection to follow mode in Intel syntax. And allows a suffix to be used to change size. This matches gas behavior from what I could tell. llvm-svn: 331138
* Fix printing of reference-to-reference types.Richard Smith2018-04-292-8/+48
| | | | | | Previously we would sometimes print these as 'T &&&' or even 'T &&&&'. llvm-svn: 331137
* PR37275 packed attribute should not apply to base classesRichard Smith2018-04-294-14/+70
| | | | | | | | | | | | | Clang incorrectly applied the packed attribute to base classes. Per GCC's documentation and as can be observed from its behavior, packed only applies to members, not base classes. This change is conditioned behind -fclang-abi-compat so that an ABI break can be avoided by users if desired. Differential Revision: https://reviews.llvm.org/D46218 llvm-svn: 331136
* [X86] Remove SLDT64m instruction.Craig Topper2018-04-297-30/+11
| | | | | | | | It doesn't really exist. The instruction always writes 16-bits of memory. Putting a REX.w on it won't change anything. While I was touching the encoding tests to remove it, I added some other missing register form test cases. llvm-svn: 331135
* [X86] Remove unnecessary InstAliases. NFCICraig Topper2018-04-291-6/+0
| | | | | | These used to disambiguate MOV16ms/MOV16sm from other size instructions that no longer exist. llvm-svn: 331134
* Add -warn-backrefs (r329636) to lld's man pageEd Maste2018-04-291-1/+10
| | | | llvm-svn: 331133
* [LLVM-C] Eliminate an unused variable in a test.whitequark2018-04-291-3/+2
| | | | | | This was introduced in r331123 and broke -Werror bots. llvm-svn: 331132
* Update my email address and description.Rafael Espindola2018-04-291-2/+2
| | | | llvm-svn: 331131
* Remove keep/take/give from isl C++ bindingsTobias Grosser2018-04-291-816/+0
| | | | | | | | These functions have been legacy leftovers which we used before the official C++ bindings existed. As all uses of these legacy functions have been removed, this polly-specific extension can also be dropped. llvm-svn: 331130
* Remove another set or release() callsTobias Grosser2018-04-293-10/+10
| | | | llvm-svn: 331129
* [X86] Use getX86SubSuperRegister in addGR32orGR64Operands in the AsmParser ↵Craig Topper2018-04-291-24/+1
| | | | | | instead of duplicating its functionality. NFC llvm-svn: 331128
* s/LLVM_ON_WIN32/_WIN32/, llvmNico Weber2018-04-2946-99/+98
| | | | | | | | | | | | | | LLVM_ON_WIN32 is set exactly with MSVC and MinGW (but not Cygwin) in HandleLLVMOptions.cmake, which is where _WIN32 defined too. Just use the default macro instead of a reinvented one. See thread "Replacing LLVM_ON_WIN32 with just _WIN32" on llvm-dev and cfe-dev. No intended behavior change. This moves over all uses of the macro, but doesn't remove the definition of it in (llvm-)config.h yet. llvm-svn: 331127
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