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* [AMDGPU] Regenerate SDIV tests for an upcoming patchSimon Pilgrim2019-06-011-37/+2353
| | | | llvm-svn: 362303
* [MCA][Scheduler] Change how memory instructions are dispatched to the ↵Andrea Di Biagio2019-06-012-39/+47
| | | | | | pending set. NFCI llvm-svn: 362302
* [APInt] Add PR40897 test caseSimon Pilgrim2019-06-011-0/+3
| | | | | | In reality APInt::getBitsNeeded(INT_MIN, base) cases require one less bit than is returned llvm-svn: 362301
* [X86][AVX] Add tests for CONCAT(MOVDDUP(x),MOVDDUP(y))Simon Pilgrim2019-06-011-0/+41
| | | | llvm-svn: 362300
* [mips] Extend range of register indexes accepted by cfcmsa/ctcmsaSimon Atanasyan2019-06-013-13/+27
| | | | | | | | | | | | | | | | | The `cfcmsa` and `ctcmsa` instructions accept index of MSA control register. The MIPS64 SIMD Architecture define eight MSA control registers. But register index for `cfcmsa` and `ctcmsa` instructions might be any number in 0..31 range. If the index is greater then 7, `cfcmsa` writes zero to the destination registers and `ctcmsa` does nothing [1]. [1] MIPS Architecture for Programmers Volume IV-j: The MIPS64 SIMD Architecture Module https://www.mips.com/?do-download=the-mips64-simd-architecture-module Differential Revision: https://reviews.llvm.org/D62597 llvm-svn: 362299
* [AVR] Disable register coalescing to the PTRDISPREGS classDylan McKay2019-06-014-5/+27
| | | | | | | | | | | | | If we would allow register coalescing on PTRDISPREGS class then register allocator can lock Z register to some virtual register. Larger instructions requiring a memory acces then fail during the register allocation phase since there is no available register to hold a pointer if Y register was already taken for a stack frame. This patch prevents it by keeping Z register spillable. It does it by not allowing coalescer to lock it. Original discussion on https://github.com/avr-rust/rust/issues/128. llvm-svn: 362298
* [SLPVectorizer][X86] Add other tests described in PR28474Simon Pilgrim2019-06-011-0/+256
| | | | llvm-svn: 362297
* [SLPVectorizer][X86] This test was from PR28474Simon Pilgrim2019-06-011-1/+1
| | | | llvm-svn: 362296
* [NFC][Codegen] shift-amount-mod.ll: drop innermost operationRoman Lebedev2019-06-012-364/+232
| | | | | | | | | | | | | I have initially added it in for test to display both whether the binop w/ constant is sinked or hoisted. But as it can be seen from the 'sub (sub C, %x), %y' test, that actually conceals the issues it is supposed to test. At least two more patterns are unhandled: * 'add (sub C, %x), %y' - D62266 * 'sub (sub C, %x), %y' llvm-svn: 362295
* [ELF][test] Reorganize some AArch64 testsFangrui Song2019-06-0116-297/+175
| | | | | | | | | | | | | Delete aarch64-got.s because it is covered by aarch64-tls-iele.s Merge got-aarch64.s into aarch64-fpic-got.s by adding disassembly to the latter Create aarch64-gnu-ifunc-nonpreemptable to unify aarch64-gnu-ifunc3.s (position-dependent executable) and aarch64-gnu-ifunc-address-pie.s (PIE) Rename aarch64-got-reloc.s to aarch64-got-weak-undef.s Add --no-show-raw-insn to llvm-objdump -d RUN lines Add -pie test to arch64-tls-iele.s Delete aarch64-tls-pie.s: it is covered by arch64-tls-iele.s and aarch64-tls-le.s Rename aarch64-copy2.s to aarch64-nopic-plt.s: "copy2" gives false impression that the test is related to copy relocation llvm-svn: 362294
* msabi: Fix exponential mangling time for certain pathological inputsNico Weber2019-06-012-34/+100
| | | | | | | | | | | | | | | | | Template back references used to be recursively recomputed, add a memoization cache to cut down on this. Since there are now two different types of argument maps, rename the existing TypeBackReferences to FunArgBackReferences, and rename mangleArgumentType() to mangleFunctionArgumentType(). Fixes PR42091, the input there now takes 50ms instead of 7s to compile. No intended behavior change. Differential Revision: https://reviews.llvm.org/D62746 llvm-svn: 362293
* [IndVarSimplify] Fixup nowrap flags during LFTR (PR31181)Nikita Popov2019-06-012-6/+27
| | | | | | | | | | | | | | | | | | | | | | | | Fix for https://bugs.llvm.org/show_bug.cgi?id=31181 and partial fix for LFTR poison handling issues in general. When LFTR moves a condition from pre-inc to post-inc, it may now depend on value that is poison due to nowrap flags. To avoid this, we clear any nowrap flag that SCEV cannot prove for the post-inc addrec. Additionally, LFTR may switch to a different IV that is dynamically dead and as such may be arbitrarily poison. This patch will correct nowrap flags in some but not all cases where this happens. This is related to the adoption of IR nowrap flags for the pre-inc addrec. (See some of the switch_to_different_iv tests, where flags are not dropped or insufficiently dropped.) Finally, there are likely similar issues with the handling of GEP inbounds, but we don't have a test case for this yet. Differential Revision: https://reviews.llvm.org/D60935 llvm-svn: 362292
* [IndVarSimplify] Add additional PR33181 tests; NFCNikita Popov2019-06-011-4/+90
| | | | | | | Two more tests with a switch to a dynamically dead IV, with poison occuring on the first or second iteration. llvm-svn: 362291
* Extend the DWARFExpression address handling to support 16-bit addressesDylan McKay2019-06-013-5/+28
| | | | | | | | | | | | | | This allows the DWARFExpression class to handle addresses without crashing on targets with 16-bit pointers like AVR. This is required in order to generate assembly from clang via the '-S' flag. This fixes an error with the following message: clang: llvm/include/llvm/DebugInfo/DWARF/DWARFExpression.h:132: llvm::DWARFExpression::DWARFExpression(llvm::DataExtractor, uint16_t, uint8_t): Assertion `AddressSize == 8 || AddressSize == 4' failed. llvm-svn: 362290
* [llvm-objcopy] test commitAlex Brachet2019-06-011-1/+1
| | | | llvm-svn: 362289
* [X86] Add AVX512BF16 and AVX512VP2INTERSECT instructions to the loading ↵Craig Topper2019-06-013-0/+418
| | | | | | folding tables. llvm-svn: 362288
* [X86] Make the X86FoldTablesEmitter functional again. Fix the spacing in the ↵Craig Topper2019-06-012-28/+39
| | | | | | | | | output to make it easier to diff. Fix a few other formatting issues in the manual table. And remove some old FIXMEs. llvm-svn: 362287
* [RuntimeDyld] fix too-small-bitmask errorNick Desaulniers2019-06-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This was flagged in https://www.viva64.com/en/b/0629/ under "Snippet No. 33". It seems that this statement is doing the standard bitwise trick for adjusting a value to have a specific alignment. The issue is that getStubAlignment() returns an unsigned, while DataSize is declared a uint64_t. The right hand side of the expression is not extended to 64b before bitwise negation, resulting in the top half of the mask being 0s, which is not correct for realignment. Reviewers: lhames, MaskRay Reviewed By: MaskRay Subscribers: RKSimon, MaskRay, hiraditya, llvm-commits, srhines Tags: #llvm Differential Revision: https://reviews.llvm.org/D62227 llvm-svn: 362286
* Inline variable into assert to fix unused variable warning.Richard Trieu2019-06-011-3/+3
| | | | llvm-svn: 362285
* [LoopPred] Eliminate a redundant/confusing cover function [NFC]Philip Reames2019-06-011-19/+20
| | | | llvm-svn: 362284
* [COFF, ARM64] Fix location of ARM64 CodeView testTom Tan2019-06-012-1/+4
| | | | | | | | ARM64 CodeView test was incorrectly put under test/DebugInfo/COFF folder which runs for all all architectures. This fix moves it to a subfolder AArch64 with lit.local.cfg which specify it supports AArch64 only. llvm-svn: 362283
* [LoopPred] Handle a subset of NE comparison based latchesPhilip Reames2019-06-012-27/+47
| | | | | | | | | | | | | | | | | | | | | At the moment, LoopPredication completely bails out if it sees a latch of the form: %cmp = icmp ne %iv, %N br i1 %cmp, label %loop, label %exit OR %cmp = icmp ne %iv.next, %NPlus1 br i1 %cmp, label %loop, label %exit This is unfortunate since this is exactly the form that LFTR likes to produce. So, go ahead and recognize simple cases where we can. For pre-increment loops, we leverage the fact that LFTR likes canonical counters (i.e. those starting at zero) and a (presumed) range fact on RHS to discharge the check trivially. For post-increment forms, the key insight is in remembering that LFTR had to insert a (N+1) for the RHS. CVP can hopefully prove that add nsw/nuw (if there's appropriate range on N to start with). This leaves us both with the post-inc IV and the RHS involving an nsw/nuw add, and SCEV can discharge that with no problem. This does still need to be extended to handle non-one steps, or other harder patterns of variable (but range restricted) starting values. That'll come later. Differential Revision: https://reviews.llvm.org/D62748 llvm-svn: 362282
* [CodeGen] Fix hashing for MO_ExternalSymbol MachineOperands.Eli Friedman2019-06-012-1/+11
| | | | | | | | | | | | | | | | | We were hashing the string pointer, not the string, so two instructions could be identical (isIdenticalTo), but have different hash codes. This showed up as a very rare, non-deterministic assertion failure rehashing a DenseMap constructed by MachineOutliner. So there's no "real" testcase, just a unittest which checks that the hash function behaves correctly. I'm a little scared fixing this is going to cause a regression in outlining or MachineCSE, but hopefully we won't run into any issues. Differential Revision: https://reviews.llvm.org/D61975 llvm-svn: 362281
* [COFF, ARM64] Add CodeView register mappingTom Tan2019-05-3114-42/+638
| | | | | | | | | | | | | | | | CodeView has its own register map which is defined in cvconst.h. Missing this mapping before saving register to CodeView causes debugger to show incorrect value for all register based variables, like variables in register and local variables addressed by register (stack pointer + offset). This change added mapping between LLVM register and CodeView register so the correct register number will be stored to CodeView/PDB, it aso fixed the mapping from CodeView register number to register name based on current CPUType but print PDB to yaml still assumes X86 CPU and needs to be fixed. Differential Revision: https://reviews.llvm.org/D62608 llvm-svn: 362280
* Revise the google-objc-global-variable-declaration check to match the style ↵Stephane Moore2019-05-312-11/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | guide. Summary: Revise the google-objc-global-variable-declaration check to match the style guide. This commit updates the check as follows: (1) Do not emit fixes for extern global constants. (2) Allow the second character of prefixes for constants to be numeric (the new guideline is that global constants should generally be named with a prefix that begins with a capital letter followed by one or more capital letters or numbers). https://google.github.io/styleguide/objcguide.html#prefixes This is an amended re-submission of https://reviews.llvm.org/rG12e3726fadb0b2a4d8aeed0a2817b5159f9d029d. Contributed By: yaqiji Reviewers: Wizard, benhamilton, stephanemoore Reviewed By: benhamilton, stephanemoore Subscribers: mgorny, cfe-commits, yaqiji Tags: #clang Differential Revision: https://reviews.llvm.org/D62045 llvm-svn: 362279
* [PowerPC] check for INLINEASM_BR along w/ INLINEASMNick Desaulniers2019-05-312-1/+2
| | | | | | | | | | | | | | | | | | | | | Summary: It looks like since INLINEASM_BR was created off of INLINEASM (r353563), a few checks for INLINEASM needed to be updated to check for either case. pr/41999 Reviewers: hfinkel Reviewed By: hfinkel Subscribers: nemanjai, hiraditya, kbarton, jsji, llvm-commits, craig.topper, srhines Tags: #llvm Differential Revision: https://reviews.llvm.org/D62403 llvm-svn: 362278
* [codeview] Revert inline line table change of r362264Reid Kleckner2019-05-315-5/+9
| | | | | | | | | | | | Testing with debuggers shows that our previous behavior was correct. The reason I thought MSVC did things differently is that MSVC prefers to use the 0xB combined code offset and code length update opcode when inline sites are discontiguous. Keep the test changes, and update the llvm-pdbutil inline line table dumper to account for this new interpretation of the opcodes. llvm-svn: 362277
* [WebAssembly] Don't export __data_end and __heap_base by default.Sam Clegg2019-05-3123-268/+42
| | | | | | | | These can still be exported via --export if needed. Differential Revision: https://reviews.llvm.org/D62744 llvm-svn: 362276
* AMDGPU: Fix not adding ImplicitBufferPtr as a live-inMatt Arsenault2019-05-312-1/+18
| | | | | | Fixes missing test from r293000. llvm-svn: 362275
* [SimplifyLibCalls] Fold more fortified functions into non-fortified variantsErik Pilkington2019-05-318-17/+580
| | | | | | | | | | | | When the object size argument is -1, no checking can be done, so calling the _chk variant is unnecessary. We already did this for a bunch of these functions. rdar://50797197 Differential revision: https://reviews.llvm.org/D62358 llvm-svn: 362272
* NFC: Pull out a function to reduce some duplicationErik Pilkington2019-05-313-121/+82
| | | | | | Part of https://reviews.llvm.org/D62358 llvm-svn: 362271
* [Tests] Better represent the postinc form produced by LFTR in LoopPred testsPhilip Reames2019-05-311-8/+12
| | | | llvm-svn: 362270
* [SelectionDAG] Make the code in mutateStrictFPToFP less aware of how many ↵Craig Topper2019-05-311-55/+34
| | | | | | | | | | | | | operands each node has. NFCI Just copy all of the operands except the chain and call MorphNode on that. This removes the IsUnary and IsTernary flags. Also always get the result type from the result type of the original nodes. Previously we got it from the operand except for two nodes where that didn't work. llvm-svn: 362269
* [Commands] Stop hardcoding languages in CommandObjectTypeAlex Langford2019-05-311-14/+9
| | | | llvm-svn: 362268
* [Bugpoint] fix another use-after-move. NFCNick Desaulniers2019-05-311-1/+1
| | | | | | | | | | | | | | | | | | | | Summary: This was flagged in https://www.viva64.com/en/b/0629/ under "Snippet No. 7". These statements are order independent, short of the use-after-move. Reviewers: echristo, srhines, RKSimon Reviewed By: RKSimon Subscribers: dblaikie, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62114 llvm-svn: 362267
* Clarify when fix-it hints on warnings are appropriateAaron Puchert2019-05-311-0/+3
| | | | | | | | | | | | | | | | | | | | | Summary: This is not a change in the rules, it's meant as a clarification about warnings. Since the recovery from warnings is a no-op, the fix-it hints on warnings shouldn't change anything. Anything that doesn't just suppress the warning and changes the meaning of the code (even if it's for the better) should be on an additional note. Reviewers: rsmith, aaron.ballman Reviewed By: aaron.ballman Subscribers: cfe-commits, thakis Tags: #clang Differential Revision: https://reviews.llvm.org/D62470 llvm-svn: 362266
* [RegisterCoalescer] fix potential use of undef value. NFCNick Desaulniers2019-05-311-7/+11
| | | | | | | | | | | | | | | | | | | | | | | Summary: Fixes a warning produced from scan-build (llvm.org/reports/scan-build/), further warnings found by annotation isMoveInstr [[nodiscard]]. isMoveInstr potentially does not assign to its parameters, so if they were uninitialized, they will potentially stay uninitialized. It seems most call sites pass references to uninitialized values, then use them without checking the return value. Reviewers: wmi Reviewed By: wmi Subscribers: MatzeB, qcolombet, hiraditya, tpr, llvm-commits, srhines Tags: #llvm Differential Revision: https://reviews.llvm.org/D62109 llvm-svn: 362265
* [codeview] Fix inline line table accuracy for discontiguous segmentsReid Kleckner2019-05-315-51/+77
| | | | | | | | | | | | | | | | After improving the inline line table dumper in llvm-pdbutil and looking at MSVC's inline line tables, it is clear that setting the length of the inlined code region does not update the code offset. This means that the delta to the beginning of a new discontiguous inlined code region should be calculated relative to the last code offset, excluding the length. Implementing this is a one line fix for MC: simply don't update LastLabel. While I'm updating these test cases, switch them to use llvm-objdump -d and llvm-pdbutil. This allows us to show offsets of each instruction and correlate the line table offsets to the actual code. llvm-svn: 362264
* Reapply [CVP] Simplify non-overflowing saturating add/subNikita Popov2019-05-312-9/+32
| | | | | | | | | | | | | If we can determine that a saturating add/sub will not overflow based on range analysis, convert it into a simple binary operation. This is a sibling transform to the existing with.overflow handling. Reapplying this with an additional check that the saturating intrinsic has integer type, as LVI currently does not support vector types. Differential Revision: https://reviews.llvm.org/D62703 llvm-svn: 362263
* [CVP] Add vector saturating add test; NFCNikita Popov2019-05-311-0/+10
| | | | | | Extra test for the assertion failure from D62703. llvm-svn: 362262
* [CVP] Fix assertion failure on vector with.overflowNikita Popov2019-05-312-1/+13
| | | | | | | | Noticed on D62703. LVI only handles plain integers, not vectors of integers. This was previously not an issue, because vector support for with.overflow is only a relatively recent addition. llvm-svn: 362261
* [Tests] Add ne icmp tests w/preinc forms for LoopPredicationPhilip Reames2019-05-311-6/+80
| | | | | | Turns out this is substaintially easier to match then the post increment form, so let's start there. llvm-svn: 362260
* [Target] Remove ABI's dependence on ExpressionParserAlex Langford2019-05-311-5/+5
| | | | llvm-svn: 362259
* [ScopBuilder] Move verifyInvariantLoads function from ScopInfo. NFC.Michael Kruse2019-05-314-30/+30
| | | | | | | | | | | Refactor Scop and ScopBuilder class. Move verifyInvariantLoads from Scop class to ScopBuilder class. Patch by: Dominik Adamski <adamski.dominik@gmail.com> Differential Revision: https://reviews.llvm.org/D62628 llvm-svn: 362258
* [ScheduleOptimizer] Hoist extension nodes after schedule optimization.Michael Kruse2019-05-319-85/+724
| | | | | | | | | | | | | | | | | | | | | | Extension nodes make schedule trees are less flexible: Many operations, such as rescheduling, do not work on such schedule trees with extension. As such, some functionality such as determining parallel loops in isl's AST are disabled. Currently, only the pattern-matching generalized matrix-matrix multiplication optimization adds extension nodes (to add copy-in statements). This patch removes all extension nodes as the last step of the schedule optimization by hoisting the extension node's added domain up to the root domain node. All following passes can assume that schedule trees work without restrictions, including the parallelism test. Mark the outermost loop of the optimized matrix-matrix multiplication as parallel such that -polly-parallel is able to parallelize that loop. Differential Revision: https://reviews.llvm.org/D58202 llvm-svn: 362257
* [X86] Resync Host.cpp with compiler-rt's cpu_model.c to enable 0x55 to be ↵Craig Topper2019-05-311-5/+10
| | | | | | | | identified as cascadelake when avx512vnni is detected. Some other formatting changes. llvm-svn: 362256
* [NFC][InstCombine] Add unary FNeg tests to AMDGPU/amdgcn-intrinsics.llCameron McInally2019-05-311-0/+21
| | | | llvm-svn: 362255
* Revert "[CVP] Simplify non-overflowing saturating add/sub"Nikita Popov2019-05-312-32/+9
| | | | | | | | This reverts commit 1e692d1777ae34dcb93524b5798651a29defae09. Causes assertion failure in builtins-wasm.c clang test. llvm-svn: 362254
* [NFC][InstCombine] Add unary FNeg to cos-1.ll cos-2.ll cos-sin-intrinsic.llCameron McInally2019-05-313-0/+242
| | | | llvm-svn: 362253
* Add include for 'test_macros.h' to all the tests that were missing them. ↵Marshall Clow2019-05-313295-0/+5607
| | | | | | Thanks to Zoe for the (big, but simple) patch. NFC intended. llvm-svn: 362252
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