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* Rolled back r176719 because settings with fileSean Callanan2013-03-151-2/+11
| | | | | | | | names were broken. <rdar://problem/13422580> llvm-svn: 177139
* [analyzer] Refactor checks in IDC visitor for consistency and speedAnna Zaks2013-03-151-6/+6
| | | | llvm-svn: 177138
* [analyzer] Teach trackNullOrUndef to look through ternary operatorsAnna Zaks2013-03-152-3/+50
| | | | | | Allows the suppression visitors trigger more often. llvm-svn: 177137
* Turn anonymous type in anonymous union warning back on after cleaning upEric Christopher2013-03-155-16/+7
| | | | | | issues. llvm-svn: 177136
* Silence anonymous type in anonymous union warnings.Eric Christopher2013-03-156-197/+250
| | | | llvm-svn: 177135
* PR15290: 'this' is not permitted in the declaration of a friend function,Richard Smith2013-03-152-4/+23
| | | | | | | therefore references to members should not be transformed into implicit uses of 'this'. Patch by Ismail Pazarbasi! llvm-svn: 177134
* Silence anonymous type in anonymous union warnings.Eric Christopher2013-03-159-148/+173
| | | | llvm-svn: 177133
* Fix a virtual destructor warning.Eric Christopher2013-03-152-0/+3
| | | | | | Patch by Manuel Klimek! llvm-svn: 177132
* Add a triple to the test.Nadav Rotem2013-03-151-0/+3
| | | | llvm-svn: 177131
* Unaligned loads should use the VMOVUPS opcode.Nadav Rotem2013-03-143-2/+13
| | | | llvm-svn: 177130
* Remove some unused variables to clean the Clang -Werror buildDavid Blaikie2013-03-141-2/+0
| | | | | | (these were added in r177089) llvm-svn: 177129
* [mips] Set isAllocatable bit of unallocatable register classes to 0.Akira Hatanaka2013-03-141-8/+13
| | | | llvm-svn: 177128
* Diagnose about extern "C" functions returning c++ objectsFariborz Jahanian2013-03-142-2/+38
| | | | | | on first declaration only. // rdar://13364028 llvm-svn: 177127
* Don't try to typo-correct 'super' in an objc method.Argyrios Kyrtzidis2013-03-146-2/+45
| | | | | | | | | | | | | | | | | | | | | This created 2 issues: 1) Performance issue, since typo-correction with PCH/modules is rather expensive. 2) Correctness issue, since if it managed to "correct" 'super' then bogus compiler errors would be emitted, like this: 3.m:8:3: error: unknown type name 'super'; did you mean 'super1'? super.x = 0; ^~~~~ super1 t3.m:5:13: note: 'super1' declared here typedef int super1; ^ t3.m:8:8: error: expected identifier or '(' super.x = 0; ^ llvm-svn: 177126
* <rdar://problem/12537646>Greg Clayton2013-03-144-16/+50
| | | | | | lldb remembers not-found source file, setting target.source-map doesn't make it re-check for it. Now this is fixed. Each time the source path remappings get updated, the modification ID in the PathMappingList gets bumped and then we know the re-check for sources. llvm-svn: 177125
* Add a testcase for r177118.Adrian Prantl2013-03-141-1/+2
| | | | llvm-svn: 177124
* Fix r177112: Add ProcResGroup.Andrew Trick2013-03-141-1/+3
| | | | | | This is the other half of r177122 that I meant to commit at the same time. llvm-svn: 177123
* Prepare for adding InstrSchedModel annotations to X86 instructions.Jakob Stoklund Olesen2013-03-141-0/+26
| | | | | | | | | | | | The new InstrSchedModel is easier to use than the instruction itineraries. It will be used to model instruction latency and throughput in modern Intel microarchitectures like Sandy Bridge. InstrSchedModel should be able to coexist with instruction itinerary classes, but for cleanliness we should switch the Atom processor model to the new InstrSchedModel as well. llvm-svn: 177122
* [analyzer] Change the way in which IDC Visitor decides to kick in and make ↵Anna Zaks2013-03-143-33/+42
| | | | | | | | | | | | | sure it attaches in the given edge case In the test case below, the value V is not constrained to 0 in ErrorNode but it is in node N. So we used to fail to register the Suppression visitor. We also need to change the way we determine that the Visitor should kick in because the node N belongs to the ExplodedGraph and might not be on the BugReporter path that the visitor sees. Instead of trying to match the node, turn on the visitor when we see the last node in which the symbol is ‘0’. llvm-svn: 177121
* Add a new method which enables one to change register classes.Reed Kotler2013-03-142-0/+15
| | | | | | | | | | | | See the Mips16ISetLowering.cpp patch to see a use of this. For now now the extra code in Mips16ISetLowering.cpp is a nop but is used for test purposes. Mips32 registers are setup and then removed and then the Mips16 registers are setup. Normally you need to add register classes and then call computeRegisterProperties. llvm-svn: 177120
* Log the match substring as well in the case where we match the step-avoid ↵Jim Ingham2013-03-141-4/+12
| | | | | | regexp. llvm-svn: 177119
* Always declare the .block_descriptor parameter, not just the local copy.Adrian Prantl2013-03-141-9/+10
| | | | | | Un-breaks gdb's invoke-block behavior. llvm-svn: 177118
* Add some logging to track cases where “step-in” steps out due to the ↵Jim Ingham2013-03-141-4/+21
| | | | | | avoid-regexp and the step-in target. llvm-svn: 177117
* Recommit lldb realtime output for POSIX.Matt Kopec2013-03-143-29/+4
| | | | | | -Adds workaround for assertion in lldb for TestEvents.py llvm-svn: 177116
* LoopVectorizer: Insert some white space to make test case more readableArnold Schwaighofer2013-03-141-6/+10
| | | | | | Also remove some unneeded function attributes. llvm-svn: 177114
* [fast-isel] The X86FastISel::FastLowerArguments function doesn't properly handleChad Rosier2013-03-142-0/+13
| | | | | | | the win64 calling convention. rdar://13423768 llvm-svn: 177113
* MachineModel: Add a ProcResGroup class.Andrew Trick2013-03-143-12/+97
| | | | | | | | | | | | | | | | | This allows abitrary groups of processor resources. Using something in a subset automatically counts againts the superset. Currently, this only works if the superset is also a ProcResGroup as opposed to a SuperUnit. This allows SandyBridge to be expressed naturally, which will be checked in shortly. def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>; def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; def SBPort23 : ProcResGroup<[SBPort2, SBPort3]>; def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; llvm-svn: 177112
* Move estimateStackSize from ARM into MachineFrameInfoHal Finkel2013-03-144-108/+55
| | | | | | | | | | This is a generic function (derived from PEI); moving it into MachineFrameInfo eliminates a current redundancy between the ARM and AArch64 backends, and will allow it to be used by the PowerPC target code. No functionality change intended. llvm-svn: 177111
* [PR15513/<rdar://problem/13409707>] Template arguments in diagnostics aren't ↵Douglas Gregor2013-03-142-2/+12
| | | | | | always known at compile time. llvm-svn: 177110
* Make a README file with an introduction and basic directions for the ↵Enrico Granata2013-03-141-0/+264
| | | | | | lldb-perf infrastructure llvm-svn: 177109
* Provide the register scavenger to processFunctionBeforeFrameFinalizedHal Finkel2013-03-1410-12/+18
| | | | | | | | | | | | | Add the current PEI register scavenger as a parameter to the processFunctionBeforeFrameFinalized callback. This change is necessary in order to allow the PowerPC target code to set the register scavenger frame index after the save-area offset adjustments performed by processFunctionBeforeFrameFinalized. Only after these adjustments have been made is it possible to estimate the size of the stack frame. llvm-svn: 177108
* Use frame-index scavenging for PPC register spillingHal Finkel2013-03-142-26/+10
| | | | | | | | | | | | | | | Make requiresFrameIndexScavenging return true, and create virtual registers in the spilling code instead of using the register scavenger directly. This makes the target-level code simpler, and importantly, delays the scavenging until after callee-saved register processing (which will be important for later changes). Also cleans up trackLivenessAfterRegAlloc (makes it inline in the header with the other related functions). This makes it clear that it always returns true. No functionality change intended. llvm-svn: 177107
* Not all PPC functions with a frame pointer need a RS spill slotHal Finkel2013-03-142-11/+11
| | | | | | | | | | | | | We used to add a spill slot for the register scavenger whenever the function has a frame pointer. This is unnecessarily conservative: We may need the spill slot for dynamic stack allocations, and functions with dynamic stack allocations always have a FP, but we might also have a FP for other reasons (such as the user explicitly disabling frame-pointer elimination), and we don't necessarily need a spill slot for those functions. The structsinregs test needed adjustment because it disables FP elimination. llvm-svn: 177106
* ARM cost model: Increase cost of some vector selects we do terrible onArnold Schwaighofer2013-03-143-5/+249
| | | | | | | | | | | | | | | | | By terrible I mean we store/load from the stack. This matters on PAQp8 in _Z5trainPsS_ii (which is inlined into Mixer::update) where we decide to vectorize a loop with a VF of 8 resulting in a 25% degradation on a cortex-a8. LV: Found an estimated cost of 2 for VF 8 For instruction: icmp slt i32 LV: Found an estimated cost of 2 for VF 8 For instruction: select i1, i32, i32 The bug that tracks the CodeGen part is PR14868. radar://13403975 llvm-svn: 177105
* [mips] Fix filename in comment and delete unnecessary lines of code.Akira Hatanaka2013-03-141-5/+1
| | | | | | No functionality changes. llvm-svn: 177104
* Hexagon: Removed asserts regarding alignment and offset.Jyotsna Verma2013-03-142-5/+20
| | | | | | We are warning the user about the alignment, so we should not assert. llvm-svn: 177103
* Add missing asserts flag to test - it uses debug flagsArnold Schwaighofer2013-03-141-1/+1
| | | | llvm-svn: 177102
* Android uses cacheflush(long start, long end, long flags) for MIPS.Akira Hatanaka2013-03-141-0/+9
| | | | | | Patch by Stephen Hines. llvm-svn: 177101
* <rdar://problem/13228487>Enrico Granata2013-03-1411-24/+581
| | | | | | | A test case for the performance of some LLDB formatters Changes and improvements to the testing infrastructure itself llvm-svn: 177100
* Updated link to Marshall's instructionsMarshall Clow2013-03-141-1/+1
| | | | llvm-svn: 177099
* LoopVectorize: Invert case when we use a vector cmp value to query select costArnold Schwaighofer2013-03-142-1/+63
| | | | | | | We generate a select with a vectorized condition argument when the condition is NOT loop invariant. Not the other way around. llvm-svn: 177098
* Add back lines which were accidentally deleted in CMakeLists.txt.Akira Hatanaka2013-03-141-0/+2
| | | | llvm-svn: 177096
* [mips] Define function MipsSEDAGToDAGISel::selectAddESubE.Akira Hatanaka2013-03-142-31/+31
| | | | | | No intended functionality changes. llvm-svn: 177095
* Add a comment about overlapping PPC frame offsetsHal Finkel2013-03-141-0/+3
| | | | | | | | I don't think that it is otherwise clear how the overlapping offsets are processed into distinct spill slots. Comment that this is done in processFunctionBeforeFrameFinalized. llvm-svn: 177094
* Some forward-looking and optimistic documentation.Howard Hinnant2013-03-142-0/+157
| | | | llvm-svn: 177093
* [mips] Rename functions and variables to start with proper case.Akira Hatanaka2013-03-147-57/+57
| | | | llvm-svn: 177092
* <rdar://problem/13421412>Greg Clayton2013-03-1438-153/+138
| | | | | | Many "byte size" members and variables were using a mixture of uint32_t and size_t. Switching over to using uint64_t everywhere. llvm-svn: 177091
* Add header file MipsISelDAGToDAG.h.Akira Hatanaka2013-03-141-0/+93
| | | | llvm-svn: 177090
* [mips] Define two subclasses of MipsDAGToDAGISel. Mips16DAGToDAGISel is forAkira Hatanaka2013-03-146-648/+900
| | | | | | | | mips16 and MipsSEDAGToDAGISel is for mips32/64. No functionality changes. llvm-svn: 177089
* Perform factorization as a last resort of unsafe fadd/fsub simplification.Shuxin Yang2013-03-142-5/+196
| | | | | | | | | | | | | | | Rules include: 1)1 x*y +/- x*z => x*(y +/- z) (the order of operands dosen't matter) 2) y/x +/- z/x => (y +/- z)/x The transformation is disabled if the new add/sub expr "y +/- z" is a denormal/naz/inifinity. rdar://12911472 llvm-svn: 177088
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