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* AArch64: remove CRC feature from Cyclone.Tim Northover2016-02-242-1/+27
| | | | | | Turns out we don't actually support those instructions. llvm-svn: 261759
* AArch64: fix Cyclone CPU features list.Tim Northover2016-02-242-4/+7
| | | | | | It turns out we don't have CRC after all. Who knew? llvm-svn: 261758
* [ThinLTO] Add missing breaks when parsing summaries (NFC)Teresa Johnson2016-02-241-0/+2
| | | | | | | This wasn't causing a correctness issue, but was causing extra duplicate entries to be added to the SummaryMap. llvm-svn: 261757
* Objective-C: Add a size field to non-fragile category metadata.Manman Ren2016-02-242-2/+8
| | | | | | | | | | | This is mainly for extensibility. Note that fragile category metadata, metadata for classes and protocols all have a size field. Initial patch was provided by Greg Parker. rdar://problem/24804226 llvm-svn: 261756
* [CLANG] [AVX512] [BUILTIN] Adding PSHUF{L|H}W{128|256|512} builtin to clang .Michael Zuckerman2016-02-244-0/+158
| | | | | | Differential Revision: http://reviews.llvm.org/D17539 llvm-svn: 261755
* [SimplifyCFG] Use a more elegant solution than r261731David Majnemer2016-02-241-11/+9
| | | | | | | | | | | | | | | | The cleanupret instruction has an invariant that it's 'from' operand be a cleanuppad. This invariant was violated when we removed a dead block which removed a cleanuppad leaving behind a cleanupret with an undef 'from' operand. This was solved in r261731 by staving off the removal of the dead block to a later pass. However, it occured to me that we do not need to do this. Instead, we can simply avoid processing the cleanupret if it has an undef 'from' operand because we know that it will be removed soon. llvm-svn: 261754
* [X86][SSSE3] Added target shuffle combine tests for SSE3/SSSE3 specific ↵Simon Pilgrim2016-02-241-0/+67
| | | | | | | | shuffles. Allows us to test SSSE3 PSHUFB intrinsic. llvm-svn: 261753
* remove fixme comment that was fixed with r261750Sanjay Patel2016-02-241-1/+1
| | | | llvm-svn: 261752
* [WinEH] Make sure terminate handlers have funclet operandsDavid Majnemer2016-02-244-16/+22
| | | | | | | Calls to the terminate handler must be annotated within the exception region they are within. llvm-svn: 261751
* [InstCombine] enable optimization of casted vector xor instructionsSanjay Patel2016-02-242-21/+10
| | | | | | | | | | | | | | | | This is part of the payoff for the refactoring in: http://reviews.llvm.org/rL261649 http://reviews.llvm.org/rL261707 In addition to removing a pile of duplicated code, the xor case was missing the optimization for vector types because it checked "SrcTy->isIntegerTy()" rather than "SrcTy->isIntOrIntVectorTy()" like 'and' and 'or' were already doing. This solves part of: https://llvm.org/bugs/show_bug.cgi?id=26702 llvm-svn: 261750
* Create implicit plt entries for R_X86_64_32S.Rafael Espindola2016-02-243-2/+16
| | | | llvm-svn: 261749
* add test to show missing bitcasted vector xor foldSanjay Patel2016-02-241-0/+15
| | | | llvm-svn: 261748
* Mark R_AARCH64_PREL32 as relative.Rafael Espindola2016-02-242-1/+14
| | | | llvm-svn: 261747
* `MSP430InstrInfo::loadRegFromStackSlot` forgets to set register def.Anton Korobeynikov2016-02-242-2/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: For instance, compiling the below results in a panic: ``` llc: ../lib/CodeGen/InlineSpiller.cpp:1140: bool (anonymous namespace)::InlineSpiller::foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned int> >, llvm::MachineInstr *): Assertion `MO->isDead() && "Cannot fold physreg def"' failed. #0 0x00007f50fbcf353e llvm::sys::PrintStackTrace(llvm::raw_ostream&) /home/h/3rd/llvm/build/../lib/Support/Unix/Signals.inc:321:15 #1 0x00007f50fbcf3929 PrintStackTraceSignalHandler(void*) /home/h/3rd/llvm/build/../lib/Support/Unix/Signals.inc:380:1 #2 0x00007f50fbcf22a3 llvm::sys::RunSignalHandlers() /home/h/3rd/llvm/build/../lib/Support/Signals.cpp:45:5 #3 0x00007f50fbcf3bb4 SignalHandler(int) /home/h/3rd/llvm/build/../lib/Support/Unix/Signals.inc:210:1 #4 0x00007f50fa87a180 (/lib/x86_64-linux-gnu/libc.so.6+0x35180) #5 0x00007f50fa87a107 gsignal (/lib/x86_64-linux-gnu/libc.so.6+0x35107) #6 0x00007f50fa87b4e8 abort (/lib/x86_64-linux-gnu/libc.so.6+0x364e8) #7 0x00007f50fa873226 (/lib/x86_64-linux-gnu/libc.so.6+0x2e226) #8 0x00007f50fa8732d2 (/lib/x86_64-linux-gnu/libc.so.6+0x2e2d2) #9 0x00007f50fddd9287 (anonymous namespace)::InlineSpiller::foldMemoryOperand(llvm::ArrayRef<std::pair<llvm::MachineInstr*, unsigned int> >, llvm::MachineInstr*) /home/h/3rd/llvm/build/../lib/CodeGen/InlineSpiller.cpp:1141:21 #10 0x00007f50fddd9ee9 (anonymous namespace)::InlineSpiller::spillAroundUses(unsigned int) /home/h/3rd/llvm/build/../lib/CodeGen/InlineSpiller.cpp:1286:9 #11 0x00007f50fddd388b (anonymous namespace)::InlineSpiller::spillAll() /home/h/3rd/llvm/build/../lib/CodeGen/InlineSpiller.cpp:1338:21 #12 0x00007f50fddd221d (anonymous namespace)::InlineSpiller::spill(llvm::LiveRangeEdit&) /home/h/3rd/llvm/build/../lib/CodeGen/InlineSpiller.cpp:1391:3 #13 0x00007f50fdfd921b (anonymous namespace)::RAGreedy::selectOrSplitImpl(llvm::LiveInterval&, llvm::SmallVectorImpl<unsigned int>&, llvm::SmallSet<unsigned int, 16u, std::less<unsigned int> >&, unsigned int) /home/h/3rd/llvm/build/../lib/CodeGen/RegAllocGreedy.cpp:2555:5 #14 0x00007f50fdfd647b (anonymous namespace)::RAGreedy::selectOrSplit(llvm::LiveInterval&, llvm::SmallVectorImpl<unsigned int>&) /home/h/3rd/llvm/build/../lib/CodeGen/RegAllocGreedy.cpp:2221:12 #15 0x00007f50fdfc89f9 llvm::RegAllocBase::allocatePhysRegs() /home/h/3rd/llvm/build/../lib/CodeGen/RegAllocBase.cpp:110:14 #16 0x00007f50fdfd6337 (anonymous namespace)::RAGreedy::runOnMachineFunction(llvm::MachineFunction&) /home/h/3rd/llvm/build/../lib/CodeGen/RegAllocGreedy.cpp:2611:3 #17 0x00007f50fded33ee llvm::MachineFunctionPass::runOnFunction(llvm::Function&) /home/h/3rd/llvm/build/../lib/CodeGen/MachineFunctionPass.cpp:43:3 #18 0x00007f50fd6cdc6f llvm::FPPassManager::runOnFunction(llvm::Function&) /home/h/3rd/llvm/build/../lib/IR/LegacyPassManager.cpp:1550:23 #19 0x00007f50fd6cdf85 llvm::FPPassManager::runOnModule(llvm::Module&) /home/h/3rd/llvm/build/../lib/IR/LegacyPassManager.cpp:1571:16 #20 0x00007f50fd6ce71a (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) /home/h/3rd/llvm/build/../lib/IR/LegacyPassManager.cpp:1627:23 #21 0x00007f50fd6ce246 llvm::legacy::PassManagerImpl::run(llvm::Module&) /home/h/3rd/llvm/build/../lib/IR/LegacyPassManager.cpp:1730:16 #22 0x00007f50fd6cec31 llvm::legacy::PassManager::run(llvm::Module&) /home/h/3rd/llvm/build/../lib/IR/LegacyPassManager.cpp:1761:3 #23 0x0000000000415bdc compileModule(char**, llvm::LLVMContext&) /home/h/3rd/llvm/build/../tools/llc/llc.cpp:405:5 #24 0x0000000000414571 main /home/h/3rd/llvm/build/../tools/llc/llc.cpp:211:13 #25 0x00007f50fa866b45 __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x21b45) #26 0x0000000000414296 _start (/home/h/3rd/llvm/build/bin/llc+0x414296) Stack dump: 0. Program arguments: ./bin/llc -mtriple msp430 loadstore.ll 1. Running pass 'Function Pass Manager' on module 'loadstore.ll'. 2. Running pass 'Greedy Register Allocator' on function '@inc' ``` Original IR: ```llvm %struct.VeryLarge = type { i8, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } ; Function Attrs: norecurse nounwind define void @inc(%struct.VeryLarge* noalias nocapture sret %agg.result, %struct.VeryLarge* byval align 1 %s) #0 { entry: %p0 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 0 %0 = load i8, i8* %p0, align 1, !tbaa !1 %p1 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 1 %1 = load i32, i32* %p1, align 1, !tbaa !6 %p2 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 2 %2 = load i32, i32* %p2, align 1, !tbaa !7 %p3 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 3 %3 = load i32, i32* %p3, align 1, !tbaa !8 %p4 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 4 %4 = load i32, i32* %p4, align 1, !tbaa !9 %p5 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 5 %5 = load i32, i32* %p5, align 1, !tbaa !10 %p6 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 6 %6 = load i32, i32* %p6, align 1, !tbaa !11 %p7 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 7 %7 = load i32, i32* %p7, align 1, !tbaa !12 %p8 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 8 %8 = load i32, i32* %p8, align 1, !tbaa !13 %p9 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 9 %9 = load i32, i32* %p9, align 1, !tbaa !14 %p10 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 10 %10 = load i32, i32* %p10, align 1, !tbaa !15 %p11 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 11 %11 = load i32, i32* %p11, align 1, !tbaa !16 %p12 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 12 %12 = load i32, i32* %p12, align 1, !tbaa !17 %p13 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 13 %13 = load i32, i32* %p13, align 1, !tbaa !18 %p14 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 14 %14 = load i32, i32* %p14, align 1, !tbaa !19 %p15 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 15 %15 = load i32, i32* %p15, align 1, !tbaa !20 %p16 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 16 %16 = load i32, i32* %p16, align 1, !tbaa !21 %p17 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 17 %17 = load i32, i32* %p17, align 1, !tbaa !22 %p18 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 18 %18 = load i32, i32* %p18, align 1, !tbaa !23 %p19 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 19 %19 = load i32, i32* %p19, align 1, !tbaa !24 %p20 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 20 %20 = load i32, i32* %p20, align 1, !tbaa !25 %p21 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 21 %21 = load i32, i32* %p21, align 1, !tbaa !26 %p22 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 22 %22 = load i32, i32* %p22, align 1, !tbaa !27 %p23 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 23 %23 = load i32, i32* %p23, align 1, !tbaa !28 %p24 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 24 %24 = load i32, i32* %p24, align 1, !tbaa !29 %p25 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 25 %25 = load i32, i32* %p25, align 1, !tbaa !30 %p26 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 26 %26 = load i32, i32* %p26, align 1, !tbaa !31 %p27 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 27 %27 = load i32, i32* %p27, align 1, !tbaa !32 %p28 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 28 %28 = load i32, i32* %p28, align 1, !tbaa !33 %p29 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 29 %29 = load i32, i32* %p29, align 1, !tbaa !34 %p30 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 30 %30 = load i32, i32* %p30, align 1, !tbaa !35 %p31 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 31 %31 = load i32, i32* %p31, align 1, !tbaa !36 %p32 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 32 %32 = load i32, i32* %p32, align 1, !tbaa !37 %add = add i8 %0, 1 store i8 %add, i8* %p0, align 1, !tbaa !1 %add2 = add i32 %1, 2 store i32 %add2, i32* %p1, align 1, !tbaa !6 %add3 = add i32 %2, 3 store i32 %add3, i32* %p2, align 1, !tbaa !7 %add4 = add i32 %3, 4 store i32 %add4, i32* %p3, align 1, !tbaa !8 %add5 = add i32 %4, 5 store i32 %add5, i32* %p4, align 1, !tbaa !9 %add6 = add i32 %5, 6 store i32 %add6, i32* %p5, align 1, !tbaa !10 %add7 = add i32 %6, 7 store i32 %add7, i32* %p6, align 1, !tbaa !11 %add8 = add i32 %7, 8 store i32 %add8, i32* %p7, align 1, !tbaa !12 %add9 = add i32 %8, 9 store i32 %add9, i32* %p8, align 1, !tbaa !13 %add10 = add i32 %9, 10 store i32 %add10, i32* %p9, align 1, !tbaa !14 %add11 = add i32 %10, 11 store i32 %add11, i32* %p10, align 1, !tbaa !15 %add12 = add i32 %11, 12 store i32 %add12, i32* %p11, align 1, !tbaa !16 %add13 = add i32 %12, 13 store i32 %add13, i32* %p12, align 1, !tbaa !17 %add14 = add i32 %13, 14 store i32 %add14, i32* %p13, align 1, !tbaa !18 %add15 = add i32 %14, 15 store i32 %add15, i32* %p14, align 1, !tbaa !19 %add16 = add i32 %15, 16 store i32 %add16, i32* %p15, align 1, !tbaa !20 %add17 = add i32 %16, 17 store i32 %add17, i32* %p16, align 1, !tbaa !21 %add18 = add i32 %17, 18 store i32 %add18, i32* %p17, align 1, !tbaa !22 %add19 = add i32 %18, 19 store i32 %add19, i32* %p18, align 1, !tbaa !23 %add20 = add i32 %19, 20 store i32 %add20, i32* %p19, align 1, !tbaa !24 %add21 = add i32 %20, 21 store i32 %add21, i32* %p20, align 1, !tbaa !25 %add22 = add i32 %21, 22 store i32 %add22, i32* %p21, align 1, !tbaa !26 %add23 = add i32 %22, 23 store i32 %add23, i32* %p22, align 1, !tbaa !27 %add24 = add i32 %23, 24 store i32 %add24, i32* %p23, align 1, !tbaa !28 %add25 = add i32 %24, 25 store i32 %add25, i32* %p24, align 1, !tbaa !29 %add26 = add i32 %25, 26 store i32 %add26, i32* %p25, align 1, !tbaa !30 %add27 = add i32 %26, 27 store i32 %add27, i32* %p26, align 1, !tbaa !31 %add28 = add i32 %27, 28 store i32 %add28, i32* %p27, align 1, !tbaa !32 %add29 = add i32 %28, 29 store i32 %add29, i32* %p28, align 1, !tbaa !33 %add30 = add i32 %29, 30 store i32 %add30, i32* %p29, align 1, !tbaa !34 %add31 = add i32 %30, 31 store i32 %add31, i32* %p30, align 1, !tbaa !35 %add32 = add i32 %31, 32 store i32 %add32, i32* %p31, align 1, !tbaa !36 %add33 = add i32 %32, 33 store i32 %add33, i32* %p32, align 1, !tbaa !37 %33 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %agg.result, i32 0, i32 0 call void @llvm.memcpy.p0i8.p0i8.i32(i8* %33, i8* %p0, i32 129, i32 1, i1 false), !tbaa.struct !38 ret void } ; Function Attrs: argmemonly nounwind declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #1 attributes #0 = { norecurse nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind } !llvm.ident = !{!0} !0 = !{!"clang version 3.8.0 (git://github.com/llvm-mirror/clang 40ef2b7531472c41212c4719a9294aeb7bddebbc) (git://github.com/llvm-mirror/llvm c601eaf55606dfb9ad372b514b77aa00d1409be1)"} !1 = !{!2, !3, i64 0} !2 = !{!"", !3, i64 0, !5, i64 1, !5, i64 5, !5, i64 9, !5, i64 13, !5, i64 17, !5, i64 21, !5, i64 25, !5, i64 29, !5, i64 33, !5, i64 37, !5, i64 41, !5, i64 45, !5, i64 49, !5, i64 53, !5, i64 57, !5, i64 61, !5, i64 65, !5, i64 69, !5, i64 73, !5, i64 77, !5, i64 81, !5, i64 85, !5, i64 89, !5, i64 93, !5, i64 97, !5, i64 101, !5, i64 105, !5, i64 109, !5, i64 113, !5, i64 117, !5, i64 121, !5, i64 125} !3 = !{!"omnipotent char", !4, i64 0} !4 = !{!"Simple C/C++ TBAA"} !5 = !{!"int", !3, i64 0} !6 = !{!2, !5, i64 1} !7 = !{!2, !5, i64 5} !8 = !{!2, !5, i64 9} !9 = !{!2, !5, i64 13} !10 = !{!2, !5, i64 17} !11 = !{!2, !5, i64 21} !12 = !{!2, !5, i64 25} !13 = !{!2, !5, i64 29} !14 = !{!2, !5, i64 33} !15 = !{!2, !5, i64 37} !16 = !{!2, !5, i64 41} !17 = !{!2, !5, i64 45} !18 = !{!2, !5, i64 49} !19 = !{!2, !5, i64 53} !20 = !{!2, !5, i64 57} !21 = !{!2, !5, i64 61} !22 = !{!2, !5, i64 65} !23 = !{!2, !5, i64 69} !24 = !{!2, !5, i64 73} !25 = !{!2, !5, i64 77} !26 = !{!2, !5, i64 81} !27 = !{!2, !5, i64 85} !28 = !{!2, !5, i64 89} !29 = !{!2, !5, i64 93} !30 = !{!2, !5, i64 97} !31 = !{!2, !5, i64 101} !32 = !{!2, !5, i64 105} !33 = !{!2, !5, i64 109} !34 = !{!2, !5, i64 113} !35 = !{!2, !5, i64 117} !36 = !{!2, !5, i64 121} !37 = !{!2, !5, i64 125} !38 = !{i64 0, i64 1, !39, i64 1, i64 4, !40, i64 5, i64 4, !40, i64 9, i64 4, !40, i64 13, i64 4, !40, i64 17, i64 4, !40, i64 21, i64 4, !40, i64 25, i64 4, !40, i64 29, i64 4, !40, i64 33, i64 4, !40, i64 37, i64 4, !40, i64 41, i64 4, !40, i64 45, i64 4, !40, i64 49, i64 4, !40, i64 53, i64 4, !40, i64 57, i64 4, !40, i64 61, i64 4, !40, i64 65, i64 4, !40, i64 69, i64 4, !40, i64 73, i64 4, !40, i64 77, i64 4, !40, i64 81, i64 4, !40, i64 85, i64 4, !40, i64 89, i64 4, !40, i64 93, i64 4, !40, i64 97, i64 4, !40, i64 101, i64 4, !40, i64 105, i64 4, !40, i64 109, i64 4, !40, i64 113, i64 4, !40, i64 117, i64 4, !40, i64 121, i64 4, !40, i64 125, i64 4, !40} !39 = !{!3, !3, i64 0} !40 = !{!5, !5, i64 0} ``` Reviewers: asl Subscribers: qcolombet Differential Revision: http://reviews.llvm.org/D17441 llvm-svn: 261746
* [X86][SSE41] Combine vector blends with zeroSimon Pilgrim2016-02-247-26/+80
| | | | | | | | | Part 2 of 2 This patch add support for combining target shuffles into blends-with-zero. Differential Revision: http://reviews.llvm.org/D17483 llvm-svn: 261745
* [docs] Change non-c++ code blocks to 'text' format to fix a sphinx warning.Alexander Kornienko2016-02-241-5/+5
| | | | llvm-svn: 261744
* [X86][SSE41] Combine insertion of zero scalars into vector blends with zeroSimon Pilgrim2016-02-243-98/+189
| | | | | | | | | | Part 1 of 2 This patch attempts to replace the insertion of zero scalars with a vector blend with zero, avoiding the use of the integer insertion instructions (which are particularly slow on many targets). (Part 2 will add support for combining multiple blends-with-zero). Differential Revision: http://reviews.llvm.org/D17483 llvm-svn: 261743
* [AMDGPU] Assembler: Simplify handling of optional operandsNikolay Haustov2016-02-243-75/+79
| | | | | | | | | | | | | | | | | | Prepare to support DPP encodings. For DPP encodings, we want row_mask/bank_mask/bound_ctrl to be optional operands. However this means that when parsing instruction which has no mnemonic prefix, we cannot add both default values for VOP3 and for DPP optional operands to OperandVector - neither instructions would match. So add default values for optional operands to MCInst during conversion instead. Mark more operands as IsOptional = 1 in .td files. Do not add default values for optional operands to OperandVector in AMDGPUAsmParser. Add default values for optional operands during conversion using new helper addOptionalImmOperand. Change to cvtVOP3_2_mod to check instruction flag instead of presence of modifiers. In the future, cvtVOP3* functions can be combined into one. Separate cvtFlat and cvtFlatAtomic. Fix CNDMASK_B32 definition to have no modifiers. Review: http://reviews.llvm.org/D17445 Reviewers: tstellarAMD llvm-svn: 261742
* [Renderscript] Change expression strings to use portable format specifiers.Aidan Dodds2016-02-241-22/+26
| | | | | | Mips64 tests were failing on windows because the sscanf implementation differs between clang/gcc/msvc such that on windows %lx specifies a 32bits parameter and %llx is for 64bits. For us this meant that 64bit pointers were being truncated to 32bits on their way into a JIT'd expression. llvm-svn: 261741
* [MSAN] Fix memcmp_test on MIPSSagar Thakur2016-02-241-1/+4
| | | | | | | | | Summary: As per the test the 4th element of both arrays are not initialized and hence will contain garbage values. Memcmp returns the difference between the garbage values of the 4th element which will be different on every run of the test. And since the return value of memcmp is returned from main, we are getting random exit code every time. Reviewers: kcc, eugenis Subscribers: mohit.bhakkad, jaydeep, llvm-commits Differential: http://reviews.llvm.org/D17534 llvm-svn: 261739
* [clang-tidy] introduce modernize-deprecated-headers checkAlexander Kornienko2016-02-248-0/+512
| | | | | | | | | | | | | | | | | Summary: This patch introduces the modernize-deprecated-headers check, which is supposed to replace deprecated C library headers with the C++ STL-ones. For information see documentation; for exmaples see the test cases. Reviewers: Eugene.Zelenko, LegalizeAdulthood, alexfh Subscribers: cfe-commits Patch by Kirill Bobyrev! Differential Revision: http://reviews.llvm.org/D17484 llvm-svn: 261738
* [clang-tidy] Added a check for forward declaration in the potentially wrong ↵Alexander Kornienko2016-02-247-0/+420
| | | | | | | | | | | | | | | | | namespace Adds a new check "misc-forward-declaration-namespace". In check, A forward declaration is considerred in a potentially wrong namespace if there is any definition/declaration with the same name exists in a different namespace. Reviewers: akuegel, hokein, alexfh Patch by Eric Liu! Differential Revision: http://reviews.llvm.org/D17195 llvm-svn: 261737
* NFC. Move isDereferenceable to Loads.h/cppArtur Pilipenko2016-02-248-222/+228
| | | | | | | | | | This is a part of the refactoring to unify isSafeToLoadUnconditionally and isDereferenceablePointer functions. In subsequent change I'm going to eliminate isDerferenceableAndAlignedPointer from Loads API, leaving isSafeToLoadSpecualtively the only function to check is load instruction can be speculated. Reviewed By: hfinkel Differential Revision: http://reviews.llvm.org/D16180 llvm-svn: 261736
* NFC. Move getAlignment helper function from ValueTracking to Value class. Artur Pilipenko2016-02-243-42/+50
| | | | | | | | Reviewed By: reames, hfinkel Differential Revision: http://reviews.llvm.org/D16144 llvm-svn: 261735
* Fix test for homogeneity in case of aggregate consisting of containerized ↵Omair Javaid2016-02-241-13/+14
| | | | | | | | | | vector types Details can be found here: Differential revision: http://reviews.llvm.org/D17501 llvm-svn: 261734
* [X86][SSE] Fixed vector rotation test name typoSimon Pilgrim2016-02-241-5/+5
| | | | | | Rotation of 16i6 vector not 8i16 vector - copy+paste is not your friend llvm-svn: 261733
* [AMDGPU] fix amd_kernel_code_t bit field position as per spec (added missing ↵Nikolay Haustov2016-02-241-7/+15
| | | | | | | | | | | reserved fields) lit tests passed before and after because it doesn't test the binary representation of amd_kernel_code_t. Patch by: Valery Pykhtin (Valery.Pykhtin@amd.com) Reviewers: arsenm llvm-svn: 261732
* [SimplifyCFG] Do not blindly remove unreachable blocksDavid Majnemer2016-02-242-3/+51
| | | | | | | | | | | DeleteDeadBlock was called indiscriminately, leading to cleanuprets with undef cleanuppad references. Instead, try to drain the BB of most of it's instructions if it is unreachable. We can then remove the BB if it solely consists of a terminator (and maybe some phis). llvm-svn: 261731
* [CodeView] Describe variables live in x87 registersDavid Majnemer2016-02-242-0/+52
| | | | | | | We didn't have a mapping from LLVM's x87 floating point registers to CodeView's encoding. llvm-svn: 261730
* [ELF] - replaced std::function with raw pointers in LinkerScript.cppGeorge Rimar2016-02-241-20/+21
| | | | | | | | Change as was proposed by David Blaikie. Differential revision: http://reviews.llvm.org/D17499 llvm-svn: 261729
* tsan: disable ignore_lib4.cc test on powerpc64 and aarch64Dmitry Vyukov2016-02-241-0/+5
| | | | | | | | | | Fails on bots: http://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/1555/steps/ninja%20check%201/logs/FAIL%3A%20ThreadSanitizer-powerpc64%3A%3A%20ignore_lib4.cc http://lab.llvm.org:8011/builders/sanitizer-ppc64be-linux/builds/725/steps/ninja%20check-tsan/logs/stdio http://lab.llvm.org:8011/builders/clang-cmake-aarch64-full/builds/1468/steps/ninja%20check%202/logs/FAIL%3A%20ThreadSanitizer-aarch64%3A%3A%20ignore_lib4.cc http://lab.llvm.org:8011/builders/clang-native-aarch64-full/builds/2787/steps/ninja%20check%202/logs/FAIL%3A%20ThreadSanitizer-aarch64%3A%3A%20ignore_lib4.cc llvm-svn: 261728
* [X86][SSE] Don't get target shuffle operands prematurely. Simon Pilgrim2016-02-241-4/+7
| | | | | | PerformShuffleCombine should be usable by unary and binary target shuffles, but was attempting to get the first two operands whatever the instruction type. Since these are only used for VECTOR_SHUFFLE instructions for one particular combine I've moved them inside the relevant if statement. llvm-svn: 261727
* [ELF] - Teach input section wildcard patterns to recognize '?' meta character.George Rimar2016-02-243-17/+84
| | | | | | | | | | | `?' - matches any single character https://sourceware.org/binutils/docs/ld/Input-Section-Wildcards.html This is used in linker scripts. Differential revision: http://reviews.llvm.org/D17290 llvm-svn: 261726
* [LLVM][AVX512][PSHUFHW ][PSHUFLW ] Change imm8 to intMichael Zuckerman2016-02-244-42/+42
| | | | | | Differential Revision: http://reviews.llvm.org/D17538 llvm-svn: 261725
* AVX512: Add vpmovzxbw/d/q ,vpmovzxw/d/q ,vpmovzxbdq lowering patterns that ↵Igor Breger2016-02-242-0/+83
| | | | | | | | support 256bit inputs like AVX patterns ( that are disable in case HasVLX , see SS41I_pmovx_avx2_patterns). Differential Revision: http://reviews.llvm.org/D17504 llvm-svn: 261724
* [MSan] fix process_vm_readv test: Exit silently if syscall is not implemetedMohit K. Bhakkad2016-02-241-7/+15
| | | | | | | | | | Reviewers: eugenis Subscribers: jaydeep, sagar, llvm-commits Differential Revision: http://reviews.llvm.org/D17560 llvm-svn: 261723
* X86: Wrap a helper for an assert in #ifndef NDEBUGJustin Bogner2016-02-241-11/+7
| | | | | | | | | | | This function is used in exactly one place, and only in asserts builds. Move it a few lines up before the use and only define it when asserts are enabled. Fixes the release build under -Werror. Also remove the forward declaration and commentary that was basically identical to the code itself. llvm-svn: 261722
* [MSan] Mark dlerror.cc expected failure for MIPSMohit K. Bhakkad2016-02-241-1/+2
| | | | | | | | | | Reviewers: samsonov Subscribers: jaydeep, sagar, llvm-commits, aemerson Differential Revision: http://reviews.llvm.org/D17503 llvm-svn: 261721
* AMDGPU: Check cheaper condition before SignBitIsZeroMatt Arsenault2016-02-241-7/+6
| | | | | | | Don't do an expensive computeKnownBits call when we can do the cheap check for legal offsets first. llvm-svn: 261720
* [OpenCL] Add Sema checks for OpenCL 2.0 blockXiuli Pan2016-02-245-0/+85
| | | | | | | | | | | | | | Summary: Add Sema checks for opencl 2.0 new features: Block. This patch is partitioned from http://reviews.llvm.org/D16047 Reviewers: Anastasia Subscribers: pekka.jaaskelainen, cfe-commits Differential Revision: http://reviews.llvm.org/D17436 llvm-svn: 261719
* Fix TestCStrings for Linux with i386 inferiors.Chaoren Lin2016-02-241-48/+43
| | | | | | | | | | | | Summary: Temporarily revert part of r261704. Reviewers: spyffe Subscribers: lldb-commits Differential Revision: http://reviews.llvm.org/D17557 llvm-svn: 261718
* Default vaarg lowering should support indirect struct types.James Y Knight2016-02-245-22/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes PR11517 for SPARC. On most targets, clang lowers va_arg itself, eschewing the use of the llvm vaarg instruction. This is necessary (at least for now) as the type argument to the vaarg instruction cannot represent all the ABI information that is needed to support complex calling conventions. However, on targets with a simpler varrags ABIs, the LLVM instruction can work just fine, and clang can simply lower to it. Unfortunately, even on such targets, vaarg with a struct argument would fail, because the default lowering to vaarg was naive: it didn't take into account the ABI attribute computed by classifyArgumentType. In particular, for the DefaultABIInfo, structs are supposed to be passed indirectly and so llvm's vaarg instruction should be emitted with a pointer argument. Now, vaarg instruction emission is able to use computed ABIArgInfo for the provided argument type, which allows the default ABI support to work for structs too. I haven't touched the EmitVAArg implementation for PPC32_SVR4 or XCore, although I believe both are now redundant, and could be switched over to use the default implementation as well. Differential Revision: http://reviews.llvm.org/D16154 llvm-svn: 261717
* Fix Clang-tidy modernize-use-nullptr and modernize-use-default warnings in ↵Eugene Zelenko2016-02-243-326/+290
| | | | | | some files in source/Commands; other minor fixes. llvm-svn: 261716
* [tests] Portability fixup for r261713.Alexey Samsonov2016-02-241-2/+12
| | | | llvm-svn: 261715
* math: Fix ilogb(double) return typeAaron Watry2016-02-241-1/+1
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 261714
* [tests] Resolve old TODOs in ASan unit tests.Alexey Samsonov2016-02-242-15/+32
| | | | llvm-svn: 261713
* ELF: Remove InputSectionBase::getAlign and instead add Align member.Rui Ueyama2016-02-243-14/+11
| | | | | | | | | This is a preparation for ICF. If we merge two sections, we want to align the merged section at the largest alignment requirement. That means we want to update the alignment value, which was impossible before this patch because Header is a const value. llvm-svn: 261712
* ELF: Remove InputSectionBase::isLive and use Live member instead. NFC.Rui Ueyama2016-02-244-9/+13
| | | | | | This is also a preparation for ICF. llvm-svn: 261711
* ELF: Make some functions constant. NFC.Rui Ueyama2016-02-242-4/+4
| | | | | | This is a preparation for ICF. llvm-svn: 261710
* COFF: Temporarily remove flaky a test.Rui Ueyama2016-02-241-65/+0
| | | | | | | | This test is flaky for more than half a year or so on buildbots and has been causing confusion. Remove it while I'm investing the cause. llvm-svn: 261709
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