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* Reduce indentation.Anders Carlsson2010-06-271-14/+11
| | | | llvm-svn: 106980
* minor cleanup to SROA: when lowering type unsafe accesses toChris Lattner2010-06-271-1/+6
| | | | | | | | large integers, the first inserted value would always create an 'or X, 0'. Even though this is trivially zapped by instcombine, don't bother creating this pointless instruction. llvm-svn: 106979
* misc tidyingChris Lattner2010-06-272-5/+2
| | | | llvm-svn: 106978
* finally get around to doing a significant cleanup to irgen:Chris Lattner2010-06-2716-233/+164
| | | | | | | | have CGF create and make accessible standard int32,int64 and intptr types. This fixes a ton of 80 column violations introduced by LLVMContextification and cleans up stuff a lot. llvm-svn: 106977
* tidy up OrderGlobalInitsChris Lattner2010-06-272-14/+12
| | | | llvm-svn: 106976
* If coercing something from int or pointer type to int or pointer typeChris Lattner2010-06-272-2/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (potentially after unwrapping it from a struct) do it without going through memory. We now compile: struct DeclGroup { unsigned NumDecls; }; int foo(DeclGroup D) { return D.NumDecls; } into: %struct.DeclGroup = type { i32 } define i32 @_Z3foo9DeclGroup(i64) nounwind ssp noredzone { entry: %D = alloca %struct.DeclGroup, align 4 ; <%struct.DeclGroup*> [#uses=2] %coerce.dive = getelementptr %struct.DeclGroup* %D, i32 0, i32 0 ; <i32*> [#uses=1] %coerce.val.ii = trunc i64 %0 to i32 ; <i32> [#uses=1] store i32 %coerce.val.ii, i32* %coerce.dive %tmp = getelementptr inbounds %struct.DeclGroup* %D, i32 0, i32 0 ; <i32*> [#uses=1] %tmp1 = load i32* %tmp ; <i32> [#uses=1] ret i32 %tmp1 } instead of: %struct.DeclGroup = type { i32 } define i32 @_Z3foo9DeclGroup(i64) nounwind ssp noredzone { entry: %D = alloca %struct.DeclGroup, align 4 ; <%struct.DeclGroup*> [#uses=2] %tmp = alloca i64 ; <i64*> [#uses=2] %coerce.dive = getelementptr %struct.DeclGroup* %D, i32 0, i32 0 ; <i32*> [#uses=1] store i64 %0, i64* %tmp %1 = bitcast i64* %tmp to i32* ; <i32*> [#uses=1] %2 = load i32* %1, align 1 ; <i32> [#uses=1] store i32 %2, i32* %coerce.dive %tmp1 = getelementptr inbounds %struct.DeclGroup* %D, i32 0, i32 0 ; <i32*> [#uses=1] %tmp2 = load i32* %tmp1 ; <i32> [#uses=1] ret i32 %tmp2 } ... which is quite a bit less terrifying. llvm-svn: 106975
* Same patch as the previous on the store side. Before we compiled this:Chris Lattner2010-06-272-10/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | struct DeclGroup { unsigned NumDecls; }; int foo(DeclGroup D) { return D.NumDecls; } to: %struct.DeclGroup = type { i32 } define i32 @_Z3foo9DeclGroup(i64) nounwind ssp noredzone { entry: %D = alloca %struct.DeclGroup, align 4 ; <%struct.DeclGroup*> [#uses=2] %tmp = alloca i64 ; <i64*> [#uses=2] store i64 %0, i64* %tmp %1 = bitcast i64* %tmp to %struct.DeclGroup* ; <%struct.DeclGroup*> [#uses=1] %2 = load %struct.DeclGroup* %1, align 1 ; <%struct.DeclGroup> [#uses=1] store %struct.DeclGroup %2, %struct.DeclGroup* %D %tmp1 = getelementptr inbounds %struct.DeclGroup* %D, i32 0, i32 0 ; <i32*> [#uses=1] %tmp2 = load i32* %tmp1 ; <i32> [#uses=1] ret i32 %tmp2 } which caused fast isel bailouts due to the FCA load/store of %2. Now we generate this just blissful code: %struct.DeclGroup = type { i32 } define i32 @_Z3foo9DeclGroup(i64) nounwind ssp noredzone { entry: %D = alloca %struct.DeclGroup, align 4 ; <%struct.DeclGroup*> [#uses=2] %tmp = alloca i64 ; <i64*> [#uses=2] %coerce.dive = getelementptr %struct.DeclGroup* %D, i32 0, i32 0 ; <i32*> [#uses=1] store i64 %0, i64* %tmp %1 = bitcast i64* %tmp to i32* ; <i32*> [#uses=1] %2 = load i32* %1, align 1 ; <i32> [#uses=1] store i32 %2, i32* %coerce.dive %tmp1 = getelementptr inbounds %struct.DeclGroup* %D, i32 0, i32 0 ; <i32*> [#uses=1] %tmp2 = load i32* %tmp1 ; <i32> [#uses=1] ret i32 %tmp2 } This avoids fastisel bailing out and is groundwork for future patch. This reduces bailouts on CGStmt.ll to 911 from 935. llvm-svn: 106974
* improve CreateCoercedLoad a bit to generate slightly less awfulChris Lattner2010-06-271-1/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IR when handling X86-64 by-value struct stuff. For example, we use to compile this: struct DeclGroup { unsigned NumDecls; }; int foo(DeclGroup D); void bar(DeclGroup *D) { foo(*D); } into: define void @_Z3barP9DeclGroup(%struct.DeclGroup* %D) ssp nounwind { entry: %D.addr = alloca %struct.DeclGroup*, align 8 ; <%struct.DeclGroup**> [#uses=2] %agg.tmp = alloca %struct.DeclGroup, align 4 ; <%struct.DeclGroup*> [#uses=2] %tmp3 = alloca i64 ; <i64*> [#uses=2] store %struct.DeclGroup* %D, %struct.DeclGroup** %D.addr %tmp = load %struct.DeclGroup** %D.addr ; <%struct.DeclGroup*> [#uses=1] %tmp1 = bitcast %struct.DeclGroup* %agg.tmp to i8* ; <i8*> [#uses=1] %tmp2 = bitcast %struct.DeclGroup* %tmp to i8* ; <i8*> [#uses=1] call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp1, i8* %tmp2, i64 4, i32 4, i1 false) %0 = bitcast i64* %tmp3 to %struct.DeclGroup* ; <%struct.DeclGroup*> [#uses=1] %1 = load %struct.DeclGroup* %agg.tmp ; <%struct.DeclGroup> [#uses=1] store %struct.DeclGroup %1, %struct.DeclGroup* %0, align 1 %2 = load i64* %tmp3 ; <i64> [#uses=1] call void @_Z3foo9DeclGroup(i64 %2) ret void } which would cause fastisel to bail out due to the first class aggregate load %1. With this patch we now compile it into the (still awful): define void @_Z3barP9DeclGroup(%struct.DeclGroup* %D) nounwind ssp noredzone { entry: %D.addr = alloca %struct.DeclGroup*, align 8 ; <%struct.DeclGroup**> [#uses=2] %agg.tmp = alloca %struct.DeclGroup, align 4 ; <%struct.DeclGroup*> [#uses=2] %tmp3 = alloca i64 ; <i64*> [#uses=2] store %struct.DeclGroup* %D, %struct.DeclGroup** %D.addr %tmp = load %struct.DeclGroup** %D.addr ; <%struct.DeclGroup*> [#uses=1] %tmp1 = bitcast %struct.DeclGroup* %agg.tmp to i8* ; <i8*> [#uses=1] %tmp2 = bitcast %struct.DeclGroup* %tmp to i8* ; <i8*> [#uses=1] call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp1, i8* %tmp2, i64 4, i32 4, i1 false) %coerce.dive = getelementptr %struct.DeclGroup* %agg.tmp, i32 0, i32 0 ; <i32*> [#uses=1] %0 = bitcast i64* %tmp3 to i32* ; <i32*> [#uses=1] %1 = load i32* %coerce.dive ; <i32> [#uses=1] store i32 %1, i32* %0, align 1 %2 = load i64* %tmp3 ; <i64> [#uses=1] %call = call i32 @_Z3foo9DeclGroup(i64 %2) noredzone ; <i32> [#uses=0] ret void } which doesn't bail out. On CGStmt.ll, this reduces fastisel bail outs from 958 to 935, and is the precursor of better things to come. llvm-svn: 106973
* Implicitly compare symbolic expressions to zero when they're being used as ↵Jordy Rose2010-06-272-3/+25
| | | | | | constraints. Part of PR7491. llvm-svn: 106972
* merge two tests.Chris Lattner2010-06-272-4/+6
| | | | llvm-svn: 106971
* Change IR generation for return (in the simple case) to avoid doing sillyChris Lattner2010-06-278-103/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | load/store nonsense in the epilog. For example, for: int foo(int X) { int A[100]; return A[X]; } we used to generate: %arrayidx = getelementptr inbounds [100 x i32]* %A, i32 0, i64 %idxprom ; <i32*> [#uses=1] %tmp1 = load i32* %arrayidx ; <i32> [#uses=1] store i32 %tmp1, i32* %retval %0 = load i32* %retval ; <i32> [#uses=1] ret i32 %0 } which codegen'd to this code: _foo: ## @foo ## BB#0: ## %entry subq $408, %rsp ## imm = 0x198 movl %edi, 400(%rsp) movl 400(%rsp), %edi movslq %edi, %rax movl (%rsp,%rax,4), %edi movl %edi, 404(%rsp) movl 404(%rsp), %eax addq $408, %rsp ## imm = 0x198 ret Now we generate: %arrayidx = getelementptr inbounds [100 x i32]* %A, i32 0, i64 %idxprom ; <i32*> [#uses=1] %tmp1 = load i32* %arrayidx ; <i32> [#uses=1] ret i32 %tmp1 } and: _foo: ## @foo ## BB#0: ## %entry subq $408, %rsp ## imm = 0x198 movl %edi, 404(%rsp) movl 404(%rsp), %edi movslq %edi, %rax movl (%rsp,%rax,4), %eax addq $408, %rsp ## imm = 0x198 ret This actually does matter, cutting out 2000 lines of IR from CGStmt.ll for example. Another interesting effect is that altivec.h functions which are dead now get dce'd by the inliner. Hence all the changes to builtins-ppc-altivec.c to ensure the calls aren't dead. llvm-svn: 106970
* add some named accessors for StoreInstChris Lattner2010-06-261-0/+3
| | | | llvm-svn: 106969
* fit in 80 colsChris Lattner2010-06-261-2/+2
| | | | llvm-svn: 106968
* reduce indentationChris Lattner2010-06-261-34/+35
| | | | llvm-svn: 106967
* Implement rdar://7530813 - collapse multiple GEP instructions in IRgenChris Lattner2010-06-265-20/+53
| | | | | | | | | | | | | | | | | | | | This avoids generating two gep's for common array operations. Before we would generate something like: %tmp = load i32* %X.addr ; <i32> [#uses=1] %arraydecay = getelementptr inbounds [100 x i32]* %A, i32 0, i32 0 ; <i32*> [#uses=1] %arrayidx = getelementptr inbounds i32* %arraydecay, i32 %tmp ; <i32*> [#uses=1] %tmp1 = load i32* %arrayidx ; <i32> [#uses=1] Now we generate: %tmp = load i32* %X.addr ; <i32> [#uses=1] %arrayidx = getelementptr inbounds [100 x i32]* %A, i32 0, i32 %tmp ; <i32*> [#uses=1] %tmp1 = load i32* %arrayidx ; <i32> [#uses=1] Less IR is better at -O0. llvm-svn: 106966
* Allow '__extension__' to be analyzed in a lvalue context.Ted Kremenek2010-06-261-2/+6
| | | | llvm-svn: 106964
* minor cleanup: don't emit the base of an array subscript until after Chris Lattner2010-06-261-8/+7
| | | | | | | we're done diddling around with the index stuff. Use a cheaper type comparison. llvm-svn: 106963
* fix inc/dec to honor -fwrapv and -ftrapv, implementing PR7426.Chris Lattner2010-06-262-9/+37
| | | | llvm-svn: 106962
* move scalar inc/dec codegen into ScalarExprEmitter instead Chris Lattner2010-06-262-97/+111
| | | | | | of being in CGF. No functionality change. llvm-svn: 106961
* this test is failing nondeterministically and blaming me, just disableChris Lattner2010-06-261-1/+2
| | | | | | it for now. llvm-svn: 106960
* Fix test weirdness.Benjamin Kramer2010-06-261-1/+1
| | | | llvm-svn: 106959
* use more efficient type comparison predicates.Chris Lattner2010-06-264-6/+6
| | | | llvm-svn: 106958
* Fix unary minus to trap on overflow with -ftrapv, refactoring binopChris Lattner2010-06-262-32/+35
| | | | | | code so we can use it from VisitUnaryMinus. llvm-svn: 106957
* Implement support for -fwrapv, rdar://7221421Chris Lattner2010-06-2613-73/+125
| | | | | | | | | | | | As part of this, pull together trapv handling into the same enum. This also add support for NSW multiplies. This also makes PCH disagreement on overflow behavior silent, since it really doesn't matter except for warnings and codegen (no macros get defined etc). llvm-svn: 106956
* implement rdar://7432000 - signed negate should codegen as NSW.Chris Lattner2010-06-264-10/+28
| | | | | | While I'm in there, adjust pointer to member adjustments as well. llvm-svn: 106955
* Fix some tests that didn't test anything.Benjamin Kramer2010-06-265-7/+7
| | | | llvm-svn: 106954
* Partial specialization test should not depend on the order of specialization ↵Kenneth Uildriks2010-06-261-8/+8
| | | | | | operations or the names assigned to the specialized functions llvm-svn: 106953
* When splitting a VAARG, remember its alignment.Rafael Espindola2010-06-266-11/+51
| | | | | | This produces terrible but correct code. llvm-svn: 106952
* Revert my if-conversion cleanup since it caused a bunch of nightly testBob Wilson2010-06-262-38/+34
| | | | | | | | | | regressions. --- Reverse-merging r106939 into '.': U test/CodeGen/Thumb2/thumb2-ifcvt3.ll U lib/CodeGen/IfConversion.cpp llvm-svn: 106951
* Implement support for #pragma message, patch by Michael Spencer!Chris Lattner2010-06-265-2/+113
| | | | llvm-svn: 106950
* Change EmitReferenceBindingToExpr to take a decl instead of a boolean.Anders Carlsson2010-06-268-11/+15
| | | | llvm-svn: 106949
* Add function for mangling reference temporaries.Anders Carlsson2010-06-262-0/+11
| | | | llvm-svn: 106948
* Fix PR7328: when turning a tail recursion into a loop, need to preserveDuncan Sands2010-06-262-6/+23
| | | | | | | | the returned value after the tail call if it differs from other return values. The optimal thing to do would be to introduce a phi node for the return value, but for the moment just fix the miscompile. llvm-svn: 106947
* use ArgOperand APIGabor Greif2010-06-261-5/+5
| | | | llvm-svn: 106946
* use ArgOperand APIGabor Greif2010-06-261-24/+24
| | | | llvm-svn: 106945
* use ArgOperand APIGabor Greif2010-06-262-8/+8
| | | | llvm-svn: 106944
* VNInfos don't need to be destructed anymore.Benjamin Kramer2010-06-263-9/+9
| | | | llvm-svn: 106943
* resort to ArgOperand APIGabor Greif2010-06-261-9/+8
| | | | llvm-svn: 106942
* Remove bogus test.Eli Friedman2010-06-261-22/+0
| | | | llvm-svn: 106941
* Followup to r106770: actually generate SXTB and SXTH for sign-extensions.Eli Friedman2010-06-261-5/+2
| | | | llvm-svn: 106940
* Clean up some problems with extra CFG edges being introduced duringBob Wilson2010-06-262-34/+38
| | | | | | | | | | | | | | | if-conversion. The RemoveExtraEdges function doesn't work for blocks that end with unanalyzable branches, so in those cases, the "extra" edges must be explicitly removed. The CopyAndPredicateBlock and MergeBlocks methods can also avoid copying successor edges due to branches that have already been removed. The latter case is especially helpful when MergeBlocks is called for handling "diamond" if-conversions, where otherwise you can end up with some weird intermediate states in the CFG. Unfortunately I've been unable to find cases where this cleanup actually makes a significant difference in the code. There is one test where we manage to remove an empty block at the end of a function. Radar 6911268. llvm-svn: 106939
* Add support for encoding NEON VMOV (from scalar to core register) instructions.Bob Wilson2010-06-261-0/+33
| | | | llvm-svn: 106938
* Mangle pointer and (lvalue) reference types in the Microsoft C++ Mangler.Charles Davis2010-06-262-47/+96
| | | | | | | Also, fix mangling of throw specs. Turns out MSVC totally ignores throw specs when mangling names. llvm-svn: 106937
* It's now possible to run code placement pass for ARM.Evan Cheng2010-06-261-4/+8
| | | | llvm-svn: 106935
* When creating X86 MUL8 and DIV8 instructions, make sure we don't produceJakob Stoklund Olesen2010-06-262-37/+80
| | | | | | | | | | | CopyFromReg nodes for aliasing registers (AX and AL). This confuses the fast register allocator. Instead of CopyFromReg(AL), use ExtractSubReg(CopyFromReg(AX), sub_8bit). This fixes PR7312. llvm-svn: 106934
* Remove cruft that I didn't intend to commit.Daniel Dunbar2010-06-261-5/+0
| | | | llvm-svn: 106932
* No need to add the test script containing directory to sys.path more than once.Johnny Chen2010-06-261-1/+2
| | | | llvm-svn: 106929
* Renumber NEON instruction formats to be consecutive.Bob Wilson2010-06-263-26/+24
| | | | llvm-svn: 106927
* Add a missing dependency to try to fix a buildbot failure.Bob Wilson2010-06-261-1/+1
| | | | | | | | | It complained with: llvm[5]: Building Clang arm_neon.h.inc with tblgen cp: cannot create regular file `/build/buildbot-llvm/clang-x86_64-linux-selfhost-rel/llvm.obj.2/Release/lib/clang/2.0/include/arm_neon.h': No such file or directory llvm-svn: 106922
* Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm toBob Wilson2010-06-253-27/+27
| | | | | | "N..." instead of "NEON..." for consistency with the other NEON format names. llvm-svn: 106921
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