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* use range-based for loop; NFCISanjay Patel2015-11-161-2/+2
| | | | llvm-svn: 253256
* Correctly handle type mismatches in the __weak copy/move-initializationJohn McCall2015-11-163-2/+66
| | | | | | | | peephole I added in r250916. rdar://23559789 llvm-svn: 253255
* Add isInteger() to APFloat.Stephen Canon2015-11-163-1/+27
| | | | | | | | Useful utility function; this wasn't too hard to do before, but also wasn't obviously discoverable. Make it explicit. Reviewed offline by Michael Gottesman. llvm-svn: 253254
* [PR25538]: Fix a failure caused by r253126.Michael Zolotukhin2015-11-161-2/+2
| | | | | | | | | | | | | | | | In r253126 we stopped to recompute LCSSA after loop unrolling in all cases, except the unrolling is full and at least one of the loop exits is outside the parent loop. In other cases the transformation should not break LCSSA, but it turned out, that we also call SimplifyLoop on the parent loop, which might break LCSSA by itself. This fix just triggers LCSSA recomputation in this case as well. I'm committing it without a test case for now, but I'll try to invent one. It's a bit tricky because in an isolated test LoopSimplify would be scheduled before LoopUnroll, and thus will change the test and hide the problem. llvm-svn: 253253
* [WebAssembly] Fix function return type printingDerek Schuff2015-11-164-29/+53
| | | | | | | | | | | Summary: Previously return type information for a function was derived from return dag nodes. But this didn't work for dags with != return node. So instead compute it directly from the LLVM function as is done for imports. Differential Revision: http://reviews.llvm.org/D14593 llvm-svn: 253251
* [WebAssembly] Reverse the order of operands for br_ifDerek Schuff2015-11-163-17/+17
| | | | | | | | | | | | Summary: This is to match the new version in the spec Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff Differential Revision: http://reviews.llvm.org/D14519 llvm-svn: 253249
* [IR] Manage TheNoneToken with a std::unique_ptrDavid Majnemer2015-11-163-4/+3
| | | | | | Hopefully, this will make the sanitizer build bots happy. llvm-svn: 253248
* Find available scratch register to use in function prologue and epilogue as ↵Kit Barton2015-11-166-35/+457
| | | | | | | part of shrink wrapping. Phabricator: http://reviews.llvm.org/D13955 llvm-svn: 253247
* Add a new clang-tidy checker that flags throw expressions whose thrown type ↵Aaron Ballman2015-11-167-0/+210
| | | | | | | | is not nothrow copy constructible. While the compiler is free to elide copy constructor calls in some cases, it is under no obligation to do so, which makes the code a portability concern as well as a security concern. This checker corresponds to the CERT secure coding rule: https://www.securecoding.cert.org/confluence/display/cplusplus/ERR60-CPP.+Exception+objects+must+be+nothrow+copy+constructible llvm-svn: 253246
* [WinEH] Don't let UnwindHelp alias the return addressReid Kleckner2015-11-163-6/+56
| | | | | | | | | | | On top of that, don't bother allocating and initializing UnwindHelp if we don't have any funclets. Currently we always use RBP as our frame pointer when funclets are present, so this change makes it impossible to come here without any fixed stack objects. Fixes PR25533. llvm-svn: 253245
* Use the subtarget reference that we already haveReid Kleckner2015-11-161-2/+1
| | | | llvm-svn: 253244
* When producing error messages for always_inline functions with theEric Christopher2015-11-162-2/+14
| | | | | | | | | | target attribute, don't include "negative" subtarget features in the list of required features. Builtins are positive by default so don't need this change, but we pull the default list of features from the command line and so need to make sure that we only include features that are turned on for code generation in our error. llvm-svn: 253242
* Add intermediate subtract instructions to reassociation worklist.Owen Anderson2015-11-169-26/+87
| | | | | | | | | | We sometimes create intermediate subtract instructions during reassociation. Adding these to the worklist to revisit exposes many additional reassociation opportunities. Patch by Aditya Nandakumar. llvm-svn: 253240
* [ELF2] Remove target specific code from GotPltSection.Igor Kudrin2015-11-163-9/+17
| | | | | | | | | | | The content of reserved entries of the .got.plt section is target specific. In particular, on x86_64 the zero entry holds the address of the .dynamic section, but on AArch64 the same info is stored in the zero entry of the .got section. Differential revision: http://reviews.llvm.org/D14703 llvm-svn: 253239
* [LoopStrengthReduce] Don't increment iterator past the end of the BBDavid Majnemer2015-11-162-1/+52
| | | | | | | | | | | We tried to move the insertion point beyond instructions like landingpad and cleanuppad. However, we *also* tried to move past catchpad. This is problematic because catchpad is also a terminator. This fixes PR25541. llvm-svn: 253238
* [mips] Disable code generation through FastISel for MIPS32R6.Vasileios Kalintiris2015-11-162-3/+30
| | | | | | | | | | Reviewers: dsanders Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14708 llvm-svn: 253225
* [SimplifyLibCalls] Generalize a comment. This doesn't apply only to sqrt.Davide Italiano2015-11-161-2/+2
| | | | llvm-svn: 253224
* LWG#2156 loosened the requirements on unordered containers 'rehash' calls. ↵Marshall Clow2015-11-165-1/+49
| | | | | | Add tests to make sure we meet these requirements. Since we met the stricter ones, no code change needed to meet the looser ones. llvm-svn: 253223
* [ARM] Prevent use of a value pointed by end() iterator when placing a jump tablePetr Pavlu2015-11-161-0/+2
| | | | | | | | | | | | | | Function ARMConstantIslands::doInitialJumpTablePlacement() iterates over all basic blocks in a machine function. It calls `MI = MBB.getLastNonDebugInstr()` to get the last instruction in each block and then uses MI->getOpcode() to decide what to do. If getLastNonDebugInstr() returns MBB.end() (for example, when the block does not contain any instructions) then calling getOpcode() on this value is incorrect. Avoid this problem by checking the result of getLastNonDebugInstr(). Differential Revision: http://reviews.llvm.org/D14694 llvm-svn: 253222
* [ARM,AArch64] Store source location of asm constant pool entriesOliver Stannard2015-11-1610-18/+34
| | | | | | | | | | Storing the source location of the expression that created a constant pool entry allows us to emit better error messages if we later discover that the expression cannot be represented by a relocation. Differential Revision: http://reviews.llvm.org/D14646 llvm-svn: 253220
* [ARM,AArch64] Store source location for values in assembly filesOliver Stannard2015-11-166-4/+14
| | | | | | | | | | | The MCValue class can store a SMLoc to allow better error messages to be emitted if an error is detected after parsing. The ARM and AArch64 assembly parsers were not setting this, so error messages did not have source information. Differential Revision: http://reviews.llvm.org/D14645 llvm-svn: 253219
* [WebAssembly] Prototype passes for register coloring and register stackifying.Dan Gohman2015-11-165-0/+341
| | | | | | These passes are not yet enabled by default. llvm-svn: 253217
* tsan: replace macro check with constant checkDmitry Vyukov2015-11-161-7/+7
| | | | | | As per comments in 252892 commit. llvm-svn: 253216
* Implement P0013R1: Logical Operator Type Traits. Make a hidden ↵Marshall Clow2015-11-165-143/+370
| | | | | | implementation (__and_, __or_, and __not_) so that we can use them elsewhere in non-C++17 code - for example, in the LFTS llvm-svn: 253215
* [mips] Do not add arch name in the compiler-rt's components.Vasileios Kalintiris2015-11-162-3/+2
| | | | | | | Instead, use the constant "mips" since the libraries are already placed under the multilib's OS suffix. llvm-svn: 253214
* [Myriad]: pass the 'std=' option to moviCompileDouglas Katzman2015-11-162-1/+5
| | | | llvm-svn: 253213
* Mark P0013 as 'in progress'Marshall Clow2015-11-161-1/+1
| | | | llvm-svn: 253212
* [ARM,AArch64] Fix __rev16l and __rev16ll intrinsicsOliver Stannard2015-11-162-16/+46
| | | | | | | | | | | | | | | | | | | | These two intrinsics are defined in arm_acle.h. __rev16l needs to rotate by 16 bits, bit it was actually rotating by 2 bits. For AArch64, where long is 64 bits, this would still be wrong. __rev16ll was incorrect, it reversed the bytes in each 32-bit word, rather than each 16-bit halfword. The correct implementation is to apply __rev16 to the top and bottom words of the 64-bit value. For AArch32 targets, these get compiled down to the hardware rev16 instruction at -O1 and above. For AArch64 targets, the 64-bit ones get compiled to two 32-bit rev16 instructions, because there is not currently a pattern for the 64-bit rev16 instruction. Differential Revision: http://reviews.llvm.org/D14609 llvm-svn: 253211
* [mips][ias] Remove spurious ';' from inline assembly test.Daniel Sanders2015-11-161-4/+4
| | | | | | | IAS will not emit it. NFC at the moment but will prevent a test failure once IAS is enabled. llvm-svn: 253210
* [mips][ias] Accept $31 or $ra in hf16call32.ll. IAS prints the latter.Daniel Sanders2015-11-161-14/+14
| | | | | | NFC at the moment, but it will prevent a test failure once IAS is enabled. llvm-svn: 253209
* [mips][ias] Allow whitespace after commas in inlineasm*.ll tests.Daniel Sanders2015-11-164-59/+59
| | | | | | | IAS always prints whitespace after a comma. NFC at the moment but this will prevent failures when IAS is enabled. llvm-svn: 253208
* Handle ARMv6KZ namingArtyom Skrobov2015-11-162-5/+8
| | | | | | | | | | | | Summary: Update for clang tests for D14568 Reviewers: rengolin, joerg, bogden Subscribers: aemerson, rengolin, cfe-commits Differential Revision: http://reviews.llvm.org/D14570 llvm-svn: 253207
* Handle ARMv6KZ namingArtyom Skrobov2015-11-169-58/+18
| | | | | | | | | | | | | | | | | | | | | | | Summary: * ARMv6KZ is the "canonical" name, given in the ARMARM * ARMv6Z is an "official abbreviation" for it, mentioned in the ARMARM * ARMv6ZK is a popular misspelling, which we should support as an alias. The patch corrects the handling of the names. Functional changes: * ARMv6Z no longer treated as an architecture in its own right * ARMv6ZK renamed to ARMv6KZ, accepting ARMv6ZK as an alias * arm1176jz-s and arm1176jzf-s recognized as ARMv6ZK, instead of ARMv6K * default ARMv6K CPU changed to arm1176j-s Reviewers: rengolin, logan, compnerd Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D14568 llvm-svn: 253206
* [compiler-rt] [tsan] Enable intercept setjmp/longjmp for AArch64Adhemerval Zanella2015-11-169-11/+227
| | | | | | | | | | | | | | | This patch adds assembly routines to enable setjmp/longjmp for aarch64 on linux. It fixes: * test/tsan/longjmp2.cc * test/tsan/longjmp3.cc * test/tsan/longjmp4.cc * test/tsan/signal_longjmp.cc I also checked with perlbench from specpu2006 (it fails to run with missing setjmp/longjmp intrumentation). llvm-svn: 253205
* [asan] Restored asynch signal test.Yury Gribov2015-11-161-0/+104
| | | | llvm-svn: 253204
* [clang-tidy] Test commit (playing with git-svn)Alexander Kornienko2015-11-162-4/+3
| | | | llvm-svn: 253203
* clang-format: Enable #include sorting by default.Daniel Jasper2015-11-169-17/+46
| | | | | | | | | This has seen quite some usage and I am not aware of any issues. Also add a style option to enable/disable include sorting. The existing command line flag can from now on be used to override whatever is set in the style. llvm-svn: 253202
* NFC refactorings in lib/Support/TargetParser.cppArtyom Skrobov2015-11-161-16/+16
| | | | | | | | | | | | | | | | Summary: * declare FPUNames, ARCHNames, ARCHExtNames, HWDivNames, CPUNames as static const * implement getDefaultExtensions with a StringSwitch, in the same way getDefaultFPU is implemented Reviewers: rengolin Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14648 llvm-svn: 253201
* [OPENMP] Fixed tests for gcc build.Alexey Bataev2015-11-162-2/+3
| | | | llvm-svn: 253200
* [ARM] Pass in the architecture to TargetParser to cope with API changeBradley Smith2015-11-161-2/+3
| | | | | | | | The TargetParser API to get the default FPU and default extensions has changed so that it can fall back to the architecture in case of a generic CPU. llvm-svn: 253199
* [ARM] Allow TargetParser to accurately target architecturesBradley Smith2015-11-163-38/+48
| | | | | | | | | | | | Instead of defaulting to an empty string, we want to default to the CPU 'generic' in the case of no valid default CPU being found, (as long as the architecture is actually valid). In order to do this we add a default FPU for each architecture, as well as falling back to architecture defaults for extensions and FPU in the case of a generic CPU is specified. llvm-svn: 253198
* Revert "Add a "not_in()" function you can apply to the list type arguments ↵Pavel Labath2015-11-162-21/+4
| | | | | | | | to expectedFailureAll to reverse" This reverts commit r253106. llvm-svn: 253197
* [ARM] Introduce subtarget features per ARM architecture.Bradley Smith2015-11-166-362/+412
| | | | | | | This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
* Properly check if a CMPZ node is in fact comparing against zeroJames Molloy2015-11-162-0/+17
| | | | | | | | This was left implicit and never ever checked, which means we could have a CMPZ against some non-zero value and we were carrying on with BFI conversion regardless. Caught by Oliver Stannard using csmith; regression test added. llvm-svn: 253195
* Don't generate discriminators for calls to debug intrinsicsPavel Labath2015-11-162-17/+49
| | | | | | | | | | | | | | Summary: This fails a check in Verifier.cpp, which checks for location matches between the declared variable and the !dbg attachments. Reviewers: dnovillo, dblaikie, danielcdh Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14657 llvm-svn: 253194
* [AArch64] ldr= pseudo-instruction silently ignored if register invalidOliver Stannard2015-11-162-1/+19
| | | | | | | | | | | | | The AArch64 assembler was silently ignoring instructions like this: ldr foo, =bar AArch64AsmParser::parseOperand was returning true as the parse failed, but was not calling AArch64AsmParser::Error to report this to the user, so the instruction was ignored without printing an error message. Differential Revision: http://reviews.llvm.org/D14651 llvm-svn: 253193
* [GlobalOpt] Address post-commit review comments on r253168James Molloy2015-11-161-3/+17
| | | | | | | | Address Duncan Exon Smith's comments on D14148, which was added after the patch had been LGTM'd and committed: * clang-format one area where whitespace diffs occurred. * Add a threshold to limit the store/load dominance checks as they are quadratic. llvm-svn: 253192
* Update for the gnu flavor being renamed to old-gnu.Rafael Espindola2015-11-164-10/+10
| | | | llvm-svn: 253191
* [CGDebugInfo] Set the size and align for reference typesKeno Fischer2015-11-162-7/+8
| | | | | | | | | | In r253186, I changed the DIBuilder API to now take size and align for reference types as well. This was done in preparation for upcoming changes to the Verifier that will validate that sizes match between DI types and IR values that are declared as having those types. This updates clang to actually pass the information through. llvm-svn: 253190
* Move helper classes into anonymous namespaces. NFC.Benjamin Kramer2015-11-162-0/+6
| | | | llvm-svn: 253189
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