| Commit message (Collapse) | Author | Age | Files | Lines |
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Removed ifdeffed out functions and added the implementation of
WriteRegister for x86_64 architecture.
Signed-off-by: Johnny Chen <johnny.chen@apple.com>
llvm-svn: 131696
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Host.cpp was missing Error.h and the implementation of
LaunchProcess. Once againg I have added a "fake" implementation
waiting for a real one.
Fixed the call GetAddressRange to reflect the new interface in
DynamicLoaderLinuxDYLD.cpp.
Added string.h to ARM_DWARF_Registers.cpp that is needed for ::memset.
Signed-off-by: Johnny Chen <johnny.chen@apple.com>
llvm-svn: 131695
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llvm-svn: 131694
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llvm-svn: 131693
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template case.
llvm-svn: 131692
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llvm-svn: 131691
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llvm-svn: 131689
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foo:
bar = foo
.quad bar
Avoid producing it. Fixes PR9951.
llvm-svn: 131687
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llvm-svn: 131686
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llvm-svn: 131685
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Seriously, I have no idea how you guys managed to build LLDB before.
llvm-svn: 131684
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* Remove unnecessary arguments now that ForceExpAbs is a method.
* Use ForceExpAbs in EmitAbsValue.
llvm-svn: 131683
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Fixes rdar://9218925
Fixes PR9601
llvm-svn: 131682
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llvm-svn: 131681
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while stopped on a breakpoint.
llvm-svn: 131680
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llvm-svn: 131679
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the root if there is only one such node. This leaves only 2 verifier failures in
the entire test suite when running "make check".
llvm-svn: 131677
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arguments in registers).
llvm-svn: 131676
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text section.
Assume the following bit of annotated assembly:
.section .data.rel.ro,"aw",%progbits
.align 2
.LAlpha:
.long startval(GOTOFF)
.text
.align 2
.type main,%function
.align 4
main: ;;; assume "main" starts at offset 0x20
0x0 push {r11, lr}
0x4 movw r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8 movt r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc ... blah
.LBeta:
0x10 add r0, pc, r0
0x14 ... blah
.LGamma:
0x18 add r1, pc, r1
Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions
00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha
And the encoded instructions in the .o file for main: must be
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec i.e. -20
28: e34f0ff0 movt r0, #65520 ; 0xfff0 i.e. -16
However, llc (prior to this commit) generates the following sequence
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec - i.e. -20
28: e34f0fff movt r0, #65535 ; 0xffff - i.e. -1
What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.
This change agrees with what GNU as does, and makes the PIC code run.
MC/ARM/elf-movt.s covers this case.
llvm-svn: 131674
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llvm-svn: 131673
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llvm-svn: 131672
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llvm-svn: 131671
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llvm-svn: 131670
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Fixes PR9934.
We really need to start tblgening the relocation info :-(
llvm-svn: 131669
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llvm-svn: 131668
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bugs. C++11 only.
llvm-svn: 131667
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I had to change the API slightly to avoid overloading issues.
llvm-svn: 131666
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llvm-svn: 131665
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llvm-svn: 131664
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llvm-svn: 131663
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llvm-svn: 131662
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llvm-svn: 131661
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llvm-svn: 131660
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llvm-svn: 131659
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StoppointLocation.h.
Added a new lldb_private::Address function:
addr_t
Address::GetOpcodeLoadAddress (Target *target) const;
This will strip any special bits from an address to make sure it is suitable
for use in addressing an opcode. Often ARM addresses have an extra bit zero
that can be set to indicate ARM vs Thumb addresses (gotten from return address
registers, or symbol addresses that may be marked up specially). We need to
strip these bits off prior to setting breakpoints, so we can centralized the
place to do this inside the Address class.
llvm-svn: 131658
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Stankovic.
llvm-svn: 131657
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llvm-svn: 131656
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Introduce -fatal-assembler-warnings for the obvious purpose
llvm-svn: 131655
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llvm-svn: 131654
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llvm-svn: 131653
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ours compatible with GAS.
In retrospect, I should have emailed binutils about this earlier. Thanks to
Kai Tietz for pointing out that GAS already had SEH directives.
llvm-svn: 131652
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llvm-svn: 131651
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llvm-svn: 131650
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llvm-svn: 131649
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llvm-svn: 131648
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llvm-svn: 131647
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llvm-svn: 131646
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llvm-svn: 131645
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llvm-svn: 131644
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llvm-svn: 131642
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