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* [lldb, windows] Update two more locations that use LaunchThread to the new ↵Stella Stamenova2019-07-092-16/+20
| | | | | | function signature llvm-svn: 365526
* [AMDGPU] gfx908 targetStanislav Mekhanoshin2019-07-0917-7/+148
| | | | | | Differential Revision: https://reviews.llvm.org/D64429 llvm-svn: 365525
* [Object][XCOFF] Add support for 64-bit file header and section header dumping.Sean Fertile2019-07-0914-187/+633
| | | | | | | | | | | Adds a readobj dumper for 32-bit and 64-bit section header tables, and extend support for the file-header dumping to include 64-bit object files. Also refactors the binary file parsing to be done in a helper function in an attempt to cleanup error handeling. Differential Revision: https://reviews.llvm.org/D63843 llvm-svn: 365524
* [InstCombine] add tests for trunc(load); NFCSanjay Patel2019-07-091-0/+73
| | | | | | | | I'm not sure if transforming any of these is valid as a target-independent fold, but we might as well have a few tests here to confirm or deny our position. llvm-svn: 365523
* [clangd] Show documentation in hover, and fetch docs from index if needed.Sam McCall2019-07-096-44/+113
| | | | | | | | | | | | | | | | | | | Summary: I assume showing docs is going to be part of structured hover rendering, but it's unclear whether that's going to make clangd 9 so this is low-hanging fruit. (Also fixes a bug uncovered in FormattedString's plain text output: need blank lines when text follows codeblocks) Reviewers: kadircet Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64296 llvm-svn: 365522
* AMDGPU: Fix test failing since r365512Matt Arsenault2019-07-091-1/+1
| | | | llvm-svn: 365521
* Revert "[HardwareLoops] NFC - move hardware loop checking code to ↵Jinsong Ji2019-07-093-46/+35
| | | | | | | | isHardwareLoopProfitable()" This reverts commit d95557306585404893d610784edb3e32f1bfce18. llvm-svn: 365520
* Add lit.local.cfg to llvm-objdump testsSteven Wu2019-07-092-1/+2
| | | | | | | Add configuration file to llvm-objdump tests to treat files with .yaml extension as tests. llvm-svn: 365519
* [ObjC] Add a warning for implicit conversions of a constant non-boolean ↵Erik Pilkington2019-07-095-2/+114
| | | | | | | | | | value to BOOL rdar://51954400 Differential revision: https://reviews.llvm.org/D63912 llvm-svn: 365518
* Remove a comment that has been obsolete since r327679Nico Weber2019-07-091-3/+0
| | | | llvm-svn: 365517
* [unittest] Add bogus register info.Michael Liao2019-07-091-0/+52
| | | | | | | | | | | | Reviewers: dstenb Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64421 llvm-svn: 365516
* Rename llvm/test/tools/llvm-pdbdump to llvm/test/tools/llvm-pdbutilNico Weber2019-07-0943-0/+0
| | | | | | | llvm-pdbdump was renamed to llvm-pdbutil long ago. This updates the test to be where you'd expect them to be. llvm-svn: 365515
* Make pdbdump-objfilename test work againNico Weber2019-07-093-14/+13
| | | | | | | | | | | | - The test had extension .yaml, which lit doesn't execute in this directory. Rename to .test to make it run, and move the yaml bits into a dedicated file, like with all other tests in this dir. - llvm-pdbdump got renamed to llvm-pdbutil long ago, update test. - -dbi-module-info got renamed in r305032, update test for this too. llvm-svn: 365514
* [TSan] Improve handling of stack pointer mangling in {set,long}jmp, pt.8Julian Lettner2019-07-092-10/+51
| | | | | | | | | | | | Refine longjmp key management. For Linux, re-implement key retrieval in C (instead of assembly). Removal of `InitializeGuardPtr` and a final round of cleanups will be done in the next commit. Reviewed By: dvyukov Differential Revision: https://reviews.llvm.org/D64092 llvm-svn: 365513
* [AMDGPU] Created a sub-register class for the return address operand in the ↵Christudasan Devadasan2019-07-0914-114/+119
| | | | | | | | | | | | | | return instruction. Function return instruction lowering, currently uses the fixed register pair s[30:31] for holding the return address. It can be any SGPR pair other than the CSRs. Created an SGPR pair sub-register class exclusive of the CSRs, and used this regclass while lowering the return instruction. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D63924 llvm-svn: 365512
* [RISCV] Fix ICE in isDesirableToCommuteWithShiftSam Elliott2019-07-092-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: There was an error being thrown from isDesirableToCommuteWithShift in some tests. This was tracked down to the method being called before legalisation, with an extended value type, not a machine value type. In the case I diagnosed, the error was only hit with an instruction sequence involving `i24`s in the add and shift. `i24` is not a Machine ValueType, it is instead an Extended ValueType which was causing the issue. I have added a test to cover this case, and fixed the error in the callback. Reviewers: asb, luismarques Reviewed By: asb Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64425 llvm-svn: 365511
* [AArch64][GlobalISel] Optimize conditional branches followed by ↵Amara Emerson2019-07-097-9/+160
| | | | | | | | | | | | | | unconditional branches If we have an icmp->brcond->br sequence where the brcond just branches to the next block jumping over the br, while the br takes the false edge, then we can modify the conditional branch to jump to the br's target while inverting the condition of the incoming icmp. This means we can eliminate the br as an unconditional branch to the fallthrough block. Differential Revision: https://reviews.llvm.org/D64354 llvm-svn: 365510
* Revert Revert Devirtualize destructor of final class.Hiroshi Yamauchi2019-07-092-3/+50
| | | | | | | | | Revert r364359 and recommit r364100. r364100 was reverted as r364359 due to an internal test failure, but it was a false alarm. llvm-svn: 365509
* [mips] Show error in case of using FP64 mode on pre MIPS32R2 CPUSimon Atanasyan2019-07-092-2/+7
| | | | llvm-svn: 365508
* [mips] Explicitly select `mips32r2` CPU for test cases require 64-bit FPU. NFCSimon Atanasyan2019-07-0980-170/+203
| | | | | | | Support for 64-bit coprocessors on a 32-bit architecture was added in `MIPS32 R2`. llvm-svn: 365507
* [NFC] Fixed testsDavid Bolvansky2019-07-091-69/+133
| | | | llvm-svn: 365506
* [libunwind] Fix Unwind-EHABI.cpp:getByte on big-endian targetsMikhail Maltsev2019-07-091-0/+4
| | | | | | | | | | | | | | | | | | | | Summary: The function getByte is dependent on endianness and the current behavior is incorrect on big-endian targets. This patch fixes the issue. Reviewers: phosek, ostannard, dmgreen, christof, chill Reviewed By: ostannard, chill Subscribers: chill, christof, libcxx-commits Tags: #libc Differential Revision: https://reviews.llvm.org/D64402 llvm-svn: 365505
* [DAGCombine] LoadedSlice - keep getOffsetFromBase() uint64_t offset. NFCI.Simon Pilgrim2019-07-091-1/+1
| | | | | | Keep the uint64_t type from getOffsetFromBase() to stop truncation/extension overflow warnings in MSVC in alignment math. llvm-svn: 365504
* [BPF] Support for compile once and run everywhereYonghong Song2019-07-0939-224/+3016
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduction ============ This patch added intial support for bpf program compile once and run everywhere (CO-RE). The main motivation is for bpf program which depends on kernel headers which may vary between different kernel versions. The initial discussion can be found at https://lwn.net/Articles/773198/. Currently, bpf program accesses kernel internal data structure through bpf_probe_read() helper. The idea is to capture the kernel data structure to be accessed through bpf_probe_read() and relocate them on different kernel versions. On each host, right before bpf program load, the bpfloader will look at the types of the native linux through vmlinux BTF, calculates proper access offset and patch the instruction. To accommodate this, three intrinsic functions preserve_{array,union,struct}_access_index are introduced which in clang will preserve the base pointer, struct/union/array access_index and struct/union debuginfo type information. Later, bpf IR pass can reconstruct the whole gep access chains without looking at gep itself. This patch did the following: . An IR pass is added to convert preserve_*_access_index to global variable who name encodes the getelementptr access pattern. The global variable has metadata attached to describe the corresponding struct/union debuginfo type. . An SimplifyPatchable MachineInstruction pass is added to remove unnecessary loads. . The BTF output pass is enhanced to generate relocation records located in .BTF.ext section. Typical CO-RE also needs support of global variables which can be assigned to different values to different hosts. For example, kernel version can be used to guard different versions of codes. This patch added the support for patchable externals as well. Example ======= The following is an example. struct pt_regs { long arg1; long arg2; }; struct sk_buff { int i; struct net_device *dev; }; #define _(x) (__builtin_preserve_access_index(x)) static int (*bpf_probe_read)(void *dst, int size, const void *unsafe_ptr) = (void *) 4; extern __attribute__((section(".BPF.patchable_externs"))) unsigned __kernel_version; int bpf_prog(struct pt_regs *ctx) { struct net_device *dev = 0; // ctx->arg* does not need bpf_probe_read if (__kernel_version >= 41608) bpf_probe_read(&dev, sizeof(dev), _(&((struct sk_buff *)ctx->arg1)->dev)); else bpf_probe_read(&dev, sizeof(dev), _(&((struct sk_buff *)ctx->arg2)->dev)); return dev != 0; } In the above, we want to translate the third argument of bpf_probe_read() as relocations. -bash-4.4$ clang -target bpf -O2 -g -S trace.c The compiler will generate two new subsections in .BTF.ext, OffsetReloc and ExternReloc. OffsetReloc is to record the structure member offset operations, and ExternalReloc is to record the external globals where only u8, u16, u32 and u64 are supported. BPFOffsetReloc Size struct SecLOffsetReloc for ELF section #1 A number of struct BPFOffsetReloc for ELF section #1 struct SecOffsetReloc for ELF section #2 A number of struct BPFOffsetReloc for ELF section #2 ... BPFExternReloc Size struct SecExternReloc for ELF section #1 A number of struct BPFExternReloc for ELF section #1 struct SecExternReloc for ELF section #2 A number of struct BPFExternReloc for ELF section #2 struct BPFOffsetReloc { uint32_t InsnOffset; ///< Byte offset in this section uint32_t TypeID; ///< TypeID for the relocation uint32_t OffsetNameOff; ///< The string to traverse types }; struct BPFExternReloc { uint32_t InsnOffset; ///< Byte offset in this section uint32_t ExternNameOff; ///< The string for external variable }; Note that only externs with attribute section ".BPF.patchable_externs" are considered for Extern Reloc which will be patched by bpf loader right before the load. For the above test case, two offset records and one extern record will be generated: OffsetReloc records: .long .Ltmp12 # Insn Offset .long 7 # TypeId .long 242 # Type Decode String .long .Ltmp18 # Insn Offset .long 7 # TypeId .long 242 # Type Decode String ExternReloc record: .long .Ltmp5 # Insn Offset .long 165 # External Variable In string table: .ascii "0:1" # string offset=242 .ascii "__kernel_version" # string offset=165 The default member offset can be calculated as the 2nd member offset (0 representing the 1st member) of struct "sk_buff". The asm code: .Ltmp5: .Ltmp6: r2 = 0 r3 = 41608 .Ltmp7: .Ltmp8: .loc 1 18 9 is_stmt 0 # t.c:18:9 .Ltmp9: if r3 > r2 goto LBB0_2 .Ltmp10: .Ltmp11: .loc 1 0 9 # t.c:0:9 .Ltmp12: r2 = 8 .Ltmp13: .loc 1 19 66 is_stmt 1 # t.c:19:66 .Ltmp14: .Ltmp15: r3 = *(u64 *)(r1 + 0) goto LBB0_3 .Ltmp16: .Ltmp17: LBB0_2: .loc 1 0 66 is_stmt 0 # t.c:0:66 .Ltmp18: r2 = 8 .loc 1 21 66 is_stmt 1 # t.c:21:66 .Ltmp19: r3 = *(u64 *)(r1 + 8) .Ltmp20: .Ltmp21: LBB0_3: .loc 1 0 66 is_stmt 0 # t.c:0:66 r3 += r2 r1 = r10 .Ltmp22: .Ltmp23: .Ltmp24: r1 += -8 r2 = 8 call 4 For instruction .Ltmp12 and .Ltmp18, "r2 = 8", the number 8 is the structure offset based on the current BTF. Loader needs to adjust it if it changes on the host. For instruction .Ltmp5, "r2 = 0", the external variable got a default value 0, loader needs to supply an appropriate value for the particular host. Compiling to generate object code and disassemble: 0000000000000000 bpf_prog: 0: b7 02 00 00 00 00 00 00 r2 = 0 1: 7b 2a f8 ff 00 00 00 00 *(u64 *)(r10 - 8) = r2 2: b7 02 00 00 00 00 00 00 r2 = 0 3: b7 03 00 00 88 a2 00 00 r3 = 41608 4: 2d 23 03 00 00 00 00 00 if r3 > r2 goto +3 <LBB0_2> 5: b7 02 00 00 08 00 00 00 r2 = 8 6: 79 13 00 00 00 00 00 00 r3 = *(u64 *)(r1 + 0) 7: 05 00 02 00 00 00 00 00 goto +2 <LBB0_3> 0000000000000040 LBB0_2: 8: b7 02 00 00 08 00 00 00 r2 = 8 9: 79 13 08 00 00 00 00 00 r3 = *(u64 *)(r1 + 8) 0000000000000050 LBB0_3: 10: 0f 23 00 00 00 00 00 00 r3 += r2 11: bf a1 00 00 00 00 00 00 r1 = r10 12: 07 01 00 00 f8 ff ff ff r1 += -8 13: b7 02 00 00 08 00 00 00 r2 = 8 14: 85 00 00 00 04 00 00 00 call 4 Instructions #2, #5 and #8 need relocation resoutions from the loader. Signed-off-by: Yonghong Song <yhs@fb.com> Differential Revision: https://reviews.llvm.org/D61524 llvm-svn: 365503
* [ADT] Remove MSVC-only "no two-phase name lookup" typename path.Simon Pilgrim2019-07-091-9/+0
| | | | | | Now that we've dropped VS2015 support (D64326) we can use the regular codepath as VS2017+ correctly handles it llvm-svn: 365502
* [NFC] Added tests for D64285David Bolvansky2019-07-091-0/+240
| | | | llvm-svn: 365501
* [OpenCL][Sema] Improve address space support for blocksMarco Antognini2019-07-091-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch ensures that the following code is compiled identically with -cl-std=CL2.0 and -fblocks -cl-std=c++. kernel void test(void) { void (^const block_A)(void) = ^{ return; }; } A new test is not added because cl20-device-side-enqueue.cl will cover this once blocks are further improved for C++ for OpenCL. The changes to Sema::PerformImplicitConversion are based on the parts of Sema::CheckAssignmentConstraints on block pointer conversions. Reviewers: rjmccall, Anastasia Subscribers: yaxunl, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D64083 llvm-svn: 365500
* [OpenCL][Sema] Fix builtin rewritingMarco Antognini2019-07-095-5/+8
| | | | | | | | | | | This patch ensures built-in functions are rewritten using the proper parent declaration. Existing tests are modified to run in C++ mode to ensure the functionality works also with C++ for OpenCL while not increasing the testing runtime. llvm-svn: 365499
* Ignore trailing NullStmts in StmtExprs for GCC compatibility.Aaron Ballman2019-07-099-44/+124
| | | | | | | | Ignore trailing NullStmts in compound expressions when determining the result type and value. This is to match the GCC behavior which ignores semicolons at the end of compound expressions. Patch by Dominic Ferreira. llvm-svn: 365498
* [HardwareLoops] NFC - move hardware loop checking code to ↵Chen Zheng2019-07-093-35/+46
| | | | | | | | isHardwareLoopProfitable() Differential Revision: https://reviews.llvm.org/D64197 llvm-svn: 365497
* [ARM] Add test for MVE and no floats. NFCDavid Green2019-07-091-0/+139
| | | | | | | Adds a simple test that MVE with no floating point will be promoted correctly to software float calls. llvm-svn: 365496
* [InferFunctionAttrs] add more tests for derefenceable; NFCSanjay Patel2019-07-091-9/+51
| | | | llvm-svn: 365495
* [MIPS GlobalISel] Register bank select for G_PHI. Select i64 phiPetar Avramovic2019-07-096-27/+564
| | | | | | | | | | | | | | | Select gprb or fprb when def/use register operand of G_PHI is used/defined by either: copy to/from physical register or instruction with only one mapping available for that use/def operand. Integer s64 phi is handled with narrowScalar when mapping is applied, produced artifacts are combined away. Manually set gprb to all register operands of instructions created during narrowScalar. Differential Revision: https://reviews.llvm.org/D64351 llvm-svn: 365494
* AMDGPU/GlobalISel: Prepare some tests for store selectionMatt Arsenault2019-07-0917-124/+92
| | | | | | | | | | | Mostsly these would fail due to trying to use SI with a flat operation. Implementing global loads with MUBUF is more work than flat, so these won't be handled in the initial load selection. Others fail because store of s64 won't initially work, as the current set of patterns expect everything to be turned into v2i32. llvm-svn: 365493
* [MIPS GlobalISel] Regbanks for G_SELECT. Select i64, f32 and f64 selectPetar Avramovic2019-07-096-30/+449
| | | | | | | | | | | | | | | | | | Select gprb or fprb when def/use register operand of G_SELECT is used/defined by either: copy to/from physical register or instruction with only one mapping available for that use/def operand. Integer s64 select is handled with narrowScalar when mapping is applied, produced artifacts are combined away. Manually set gprb to all register operands of instructions created during narrowScalar. For selection of floating point s32 or s64 select it is enough to set fprb of appropriate size and selectImpl will do the rest. Differential Revision: https://reviews.llvm.org/D64350 llvm-svn: 365492
* AMDGPU/GlobalISel: Fix testMatt Arsenault2019-07-091-4/+1
| | | | llvm-svn: 365491
* [libclang] Fix hang in release / assertion in debug when evaluating ↵Emilio Cobos Alvarez2019-07-092-0/+13
| | | | | | | | | | | | | value-dependent types. Expression evaluator doesn't work in value-dependent types, so ensure that the precondition it asserts holds. This fixes https://bugs.llvm.org/show_bug.cgi?id=42532 Differential Revision: https://reviews.llvm.org/D64409 llvm-svn: 365490
* [docs][llvm-dwarfdump] Fix wordingJames Henderson2019-07-091-1/+1
| | | | llvm-svn: 365489
* AMDGPU/GlobalISel: Legalize more concat_vectorsMatt Arsenault2019-07-093-27/+115
| | | | llvm-svn: 365488
* AMDGPU/GlobalISel: Improve regbankselect for icmp s16Matt Arsenault2019-07-093-30/+376
| | | | | | Account for 64-bit scalar eq/ne when available. llvm-svn: 365487
* AMDGPU/GlobalISel: Make s16 G_ICMP legalMatt Arsenault2019-07-092-153/+482
| | | | llvm-svn: 365486
* [OPENMP]Fix the float point semantics handling on the device.Alexey Bataev2019-07-093-9/+17
| | | | | | | | | | The device should use the same float point representation as the host. Previous patch fixed the handling of the sizes of the float point types, but did not fixed the fp semantics. This patch makes target device to use the host fp semantics. this is required for the correct data transfer between host and device and correct codegen. llvm-svn: 365485
* AMDGPU/GlobalISel: Select G_SUBMatt Arsenault2019-07-093-7/+76
| | | | llvm-svn: 365484
* AMDGPU/GlobalISel: Select G_UNMERGE_VALUESMatt Arsenault2019-07-093-0/+278
| | | | llvm-svn: 365483
* AMDGPU/GlobalISel: Select G_MERGE_VALUESMatt Arsenault2019-07-096-18/+1380
| | | | llvm-svn: 365482
* gn build: Merge r365453Nico Weber2019-07-091-0/+1
| | | | llvm-svn: 365481
* [ItaniumMangle] Refactor long double/__float128 mangling and fix the mangled ↵Fangrui Song2019-07-096-35/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | code In gcc PowerPC, long double has 3 mangling schemes: -mlong-double-64: `e` -mlong-double-128 -mabi=ibmlongdouble: `g` -mlong-double-128 -mabi=ieeelongdouble: `u9__ieee128` (gcc <= 8.1: `U10__float128`) The current useFloat128ManglingForLongDouble() bisection is not suitable when we support -mlong-double-128 in clang (D64277). Replace useFloat128ManglingForLongDouble() with getLongDoubleMangling() and getFloat128Mangling() to allow 3 mangling schemes. I also deleted the `getTriple().isOSBinFormatELF()` check (the Darwin support has gone: https://reviews.llvm.org/D50988). For x86, change the mangled code of __float128 from `U10__float128` to `g`. `U10__float128` was wrongly copied from PowerPC. The test will be added to `test/CodeGen/x86-long-double.cpp` in D64277. Reviewed By: erichkeane Differential Revision: https://reviews.llvm.org/D64276 llvm-svn: 365480
* [Syntax] Move roles into a separate enumIlya Biryukov2019-07-096-36/+39
| | | | | | To align with reviewer's suggestions. llvm-svn: 365479
* lld-link: Stop accepting /natvis and /fastfail in .drectve sectionsNico Weber2019-07-091-2/+2
| | | | | | | | link.exe doesn't accept them either. Differential Revision: https://reviews.llvm.org/D64352 llvm-svn: 365478
* [CodeGen] AccelTable - remove non-constexpr (MSVC) Atom defsSimon Pilgrim2019-07-092-44/+0
| | | | | | Now that we've dropped VS2015 support (D64326) we can enable the constexpr variables on MSVC builds as VS2017+ correctly handles them llvm-svn: 365477
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