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* IndVarSimplify: do not recompute an IV value outside of the loop if :Arnaud A. de Grandmaison2013-03-192-0/+108
| | | | | | | - it is trivially known to be used inside the loop in a way that can not be optimized away - there is no use outside of the loop which can take advantage of the computation hoisting llvm-svn: 177432
* Add missing mayLoad flag to LHAUX8 and LWAUX.Ulrich Weigand2013-03-191-1/+2
| | | | | | | | | All pre-increment load patterns need to set the mayLoad flag (since they don't provide a DAG pattern). This was missing for LHAUX8 and LWAUX, which is added by this patch. llvm-svn: 177431
* Rewrite LHAU8 pattern to use standard memory operand.Ulrich Weigand2013-03-191-4/+4
| | | | | | | | | | | | As opposed to to pre-increment store patterns, the pre-increment load patterns were already using standard memory operands, with the sole exception of LHAU8. As there's no real reason why LHAU8 should be different here, this patch simply rewrites the pattern to also use a memri operand, just like all the other patterns. llvm-svn: 177430
* Rewrite pre-increment store patterns to use standard memory operands.Ulrich Weigand2013-03-193-151/+291
| | | | | | | | | | | | | | | | | | | | | | Currently, pre-increment store patterns are written to use two separate operands to represent address base and displacement: stwu $rS, $ptroff($ptrreg) This causes problems when implementing the assembler parser, so this commit changes the patterns to use standard (complex) memory operands like in all other memory access instruction patterns: stwu $rS, $dst To still match those instructions against the appropriate pre_store SelectionDAG nodes, the patch uses the new feature that allows a Pat to match multiple DAG operands against a single (complex) instruction operand. Approved by Hal Finkel. llvm-svn: 177429
* Extend TableGen instruction selection matcher to improve handlingUlrich Weigand2013-03-193-11/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of complex instruction operands (e.g. address modes). Currently, if a Pat pattern creates an instruction that has a complex operand (i.e. one that consists of multiple sub-operands at the MI level), this operand must match a ComplexPattern DAG pattern with the correct number of output operands. This commit extends TableGen to alternatively allow match a complex operands against multiple separate operands at the DAG level. This allows using Pat patterns to match pre-increment nodes like pre_store (which must have separate operands at the DAG level) onto an instruction pattern that uses a multi-operand memory operand, like the following example on PowerPC (will be committed as a follow-on patch): def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst), "stwu $rS, $dst", LdStStoreUpd, []>, RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff), (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>; Here, the pair of "ptroff" and "ptrreg" operands is matched onto the complex operand "dst" of class "memri" in the "STWU" instruction. Approved by Jakob Stoklund Olesen. llvm-svn: 177428
* Fix sub-operand size mismatch in tocentry operands.Ulrich Weigand2013-03-191-1/+1
| | | | | | | | | | | The tocentry operand class refers to 64-bit values (it is only used in 64-bit, where iPTR is a 64-bit type), but its sole suboperand is designated as 32-bit type. This causes a mismatch to be detected at compile-time with the TableGen patch I'll check in shortly. To fix this, this commit changes the suboperand to a 64-bit type as well. llvm-svn: 177427
* Remove an invalid and unnecessary Pat pattern from the X86 backend:Ulrich Weigand2013-03-191-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))), (MOV64rm tglobaltlsaddr :$dst)>; This pattern is invalid because the MOV64rm instruction expects a source operand of type "i64mem", which is a subclass of X86MemOperand and thus actually consists of five MI operands, but the Pat provides only a single MI operand ("tglobaltlsaddr" matches an SDnode of type ISD::TargetGlobalTLSAddress and provides a single output). Thus, if the pattern were ever matched, subsequent uses of the MOV64rm instruction pattern would access uninitialized memory. In addition, with the TableGen patch I'm about to check in, this would actually be reported as a build-time error. Fortunately, the pattern does in fact never match, for at least two independent reasons. First, the code generator actually never generates a pattern of the form (load (X86Wrapper (tglobaltlsaddr))). For most combinations of TLS and code models, (tglobaltlsaddr) represents just an offset that needs to be added to some base register, so it is never directly dereferenced. The only exception is the initial-exec model, where (tglobaltlsaddr) refers to the (pc-relative) address of a GOT slot, which *is* in fact directly dereferenced: but in that case, the X86WrapperRIP node is used, not X86Wrapper, so the Pat doesn't match. Second, even if some patterns along those lines *were* ever generated, we should not need an extra Pat pattern to match it. Instead, the original MOV64rm instruction pattern ought to match directly, since it uses an "addr" operand, which is implemented via the SelectAddr C++ routine; this routine is supposed to accept the full range of input DAGs that may be implemented by a single mov instruction, including those cases involving ISD::TargetGlobalTLSAddress (and actually does so e.g. in the initial-exec case as above). To avoid build breaks (due to the above-mentioned error) after the TableGen patch is checked in, I'm removing this Pat here. llvm-svn: 177426
* Update Sketch test case to capture this and use accessors for debugger, ↵Greg Clayton2013-03-192-36/+64
| | | | | | target, process and thread. llvm-svn: 177425
* Fix "control reaches end of non-void function" compiling lld on gcc.Andy Gibbs2013-03-191-1/+2
| | | | llvm-svn: 177424
* Prepare to make r0 an allocatable register on PPCHal Finkel2013-03-197-112/+209
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the PPC r0 register is unconditionally reserved. There are two reasons for this: 1. r0 is treated specially (as the constant 0) by certain instructions, and so cannot be used with those instructions as a regular register. 2. r0 is used as a temporary register in the CR-register spilling process (where, under some circumstances, we require two GPRs). This change addresses the first reason by introducing a restricted register class (without r0) for use by those instructions that treat r0 specially. These register classes have a new pseudo-register, ZERO, which represents the r0-as-0 use. This has the side benefit of making the existing target code simpler (and easier to understand), and will make it clear to the register allocator that uses of r0 as 0 don't conflict will real uses of the r0 register. Once the CR spilling code is improved, we'll be able to allocate r0. Adding these extra register classes, for some reason unclear to me, causes requests to the target to copy 32-bit registers to 64-bit registers. The resulting code seems correct (and causes no test-suite failures), and the new test case covers this new kind of asymmetric copy. As r0 is still reserved, no functionality change intended. llvm-svn: 177423
* Don't replace macro usage if macro body has NULLEdwin Vane2013-03-193-31/+120
| | | | | | | | | | | | | | | | | | | In case of macro body expansion, check to see if the macro is named NULL and don't replace inside the macro body. This fixes the case when NULL appears inside the macro body and the transform replaces the usage of the macro with nullptr. This is an easy fix for the problem for now and we should analyze the macro body to see if it expands to only NullToPointer in the future for a more robust solution that takes care of user defined macros that behaves like NULL. Other changes: - Moved complex macro tests to macros.cpp - Added new test cases. - Added checks to make sure that the macro bodies are not modified by the tool. Fixes: PR15396 Author: Tareq A Siraj <tareq.a.siraj@intel.com> llvm-svn: 177422
* Optimize sext <4 x i8> and <4 x i16> to <4 x i64>.Nadav Rotem2013-03-194-6/+42
| | | | | | Patch by Ahmad, Muhammad T <muhammad.t.ahmad@intel.com> llvm-svn: 177421
* Fix indentation for case: // comment.Daniel Jasper2013-03-192-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | Before: switch (x) { case 1: // Do amazing stuff { g(); f(); } } After: switch (x) { case 1: // Do amazing stuff { g(); f(); } } llvm-svn: 177420
* Relax test to allow for attributes on other architectures. Caught by ↵Adrian Prantl2013-03-191-2/+2
| | | | | | powerpc64-unknown-linux-gnu buildbot. llvm-svn: 177419
* Annotate X86InstrExtension.td with SchedRW lists.Jakob Stoklund Olesen2013-03-191-26/+39
| | | | llvm-svn: 177418
* Annotate a lot of X86InstrInfo.td with SchedRW lists.Jakob Stoklund Olesen2013-03-191-26/+60
| | | | llvm-svn: 177417
* Fixed incorrect python that was trying to validate that we got a valid ↵Greg Clayton2013-03-1915-26/+26
| | | | | | | | lldb.SBThread object by checking to see if it is equal to "None". This test is incorrect as functions that return lldb.SBThread objects never return None, they just return lldb.SBThread objects that contain invalid opaque classes. llvm-svn: 177416
* Split long lines in multi-line comments.Alexander Kornienko2013-03-192-57/+275
| | | | | | | | | | | | | | Summary: This is implementation for /* */ comments only. Reviewers: djasper, klimek Reviewed By: djasper CC: cfe-commits Differential Revision: http://llvm-reviews.chandlerc.com/D547 llvm-svn: 177415
* Update test for r177413.Chad Rosier2013-03-191-2/+2
| | | | llvm-svn: 177414
* [ms-inline asm] Move the size directive asm rewrite into the target specificChad Rosier2013-03-193-61/+37
| | | | | | | logic as a QOI cleanup. rdar://13445327 llvm-svn: 177413
* Update documentation of llvm-link to reflect recent cleanups.Eli Bendersky2013-03-191-22/+4
| | | | llvm-svn: 177411
* Remove stale commentEli Bendersky2013-03-191-3/+0
| | | | llvm-svn: 177410
* Fix for r177390: map values are pointers, use DeleteContainerSeconds() ↵Alexey Samsonov2013-03-191-1/+2
| | | | | | instead of .clear() llvm-svn: 177409
* cindex.py: Handle NULL pointers when parsing translation unitsTobias Grosser2013-03-192-2/+19
| | | | | | | | | | | | | The code inside cindex.py was comparing NULL pointer returned by clang_parseTranslationUnit and clang_createTranslationUnit with None. However, as illustrated by the two tests I've added, those conditions were ineffective which resulted in assert triggering later on. Instead, a pointer is now treated as a boolean value, a NULL pointer being False. Contributed-by: Xavier Deguillard <deguilx@gmail.com> llvm-svn: 177408
* [asan] s/ASAN_POSIX/SANITIZER_POSIX/Evgeniy Stepanov2013-03-191-1/+1
| | | | llvm-svn: 177407
* The Linker interface has some dead code after the cleanup in r172749Eli Bendersky2013-03-193-62/+3
| | | | | | | (and possibly others). The attached patch removes it, and tries to update comments accordingly. llvm-svn: 177406
* Cleanup PPC64 unaligned i64 load/storeHal Finkel2013-03-192-4/+3
| | | | | | | | | Remove an accidentally-added instruction definition and add a comment in the test case. This is in response to a post-commit review by Bill Schmidt. No functionality change intended. llvm-svn: 177404
* [docs] Remove incorrect information about lit.Sean Silva2013-03-191-10/+1
| | | | | | Lit does support redirects in the 2>&1 style. llvm-svn: 177403
* Don't try to set attributes in alias, they have none.Rafael Espindola2013-03-192-1/+15
| | | | llvm-svn: 177402
* [sanitizer] More renamed macros.Evgeniy Stepanov2013-03-1914-19/+19
| | | | llvm-svn: 177401
* [sanitizer] Replace more platform checks with SANITIZER_ constants.Evgeniy Stepanov2013-03-1937-87/+144
| | | | llvm-svn: 177400
* Revert r177329.Rafael Espindola2013-03-191-2/+1
| | | | | | | | | If this should not happen, we should have an assert. If it should happen, we should have a test and remove the comment. In no case should we have this self inconsistent code. llvm-svn: 177399
* Go back to using the integrated assembler on windows ever when passedRafael Espindola2013-03-192-2/+6
| | | | | | -no-integrated-as. It is the only assembler we have there. llvm-svn: 177398
* [sanitizer] Move ASan platform macros to sanitizer_common and rename them ↵Evgeniy Stepanov2013-03-199-46/+46
| | | | | | appropriately. llvm-svn: 177397
* Don't use --sysroot to linux SDK when building libprofile - SDK on Linux ↵Alexey Samsonov2013-03-191-2/+1
| | | | | | seems to be incomplete. llvm-svn: 177396
* tsan: fix buildDmitry Vyukov2013-03-191-0/+2
| | | | llvm-svn: 177395
* tsan: flush dead thread info earlier (when another thread is finished rather ↵Dmitry Vyukov2013-03-194-26/+42
| | | | | | than new thread is created) llvm-svn: 177394
* tsan: instruct malloc() to consume less memoryDmitry Vyukov2013-03-191-0/+5
| | | | llvm-svn: 177393
* Add virtual destructors to fix -Wnon-virtual-dtor warningsAlexey Samsonov2013-03-192-0/+6
| | | | llvm-svn: 177392
* [ASan] Make -fsanitize=address always imply -fsanitize=init-orderAlexey Samsonov2013-03-193-12/+10
| | | | llvm-svn: 177391
* llvm-symbolizer: flush internal caches functionalityDmitry Vyukov2013-03-192-0/+5
| | | | llvm-svn: 177390
* tsan: symbolizer "flush caches" supportDmitry Vyukov2013-03-192-0/+8
| | | | llvm-svn: 177389
* tsan: symbolizer "flush caches" functinalityDmitry Vyukov2013-03-192-0/+24
| | | | llvm-svn: 177388
* tsan: fix memory leakDmitry Vyukov2013-03-191-0/+1
| | | | llvm-svn: 177387
* The testing to ensure a vector of zeros of type floating point isn't ↵David Tweed2013-03-191-6/+3
| | | | | | misclassified as negative zero can be simplified, as pointed out by Duncan Sands. llvm-svn: 177386
* Enable -Wnon-virtual-dtor build warningAlexey Samsonov2013-03-191-0/+2
| | | | llvm-svn: 177385
* [sanitizer] Avoid use of uintptr_t.Evgeniy Stepanov2013-03-191-1/+1
| | | | llvm-svn: 177384
* [sanitizer] Don't adjust the size of the user-allocated stack.Evgeniy Stepanov2013-03-195-24/+65
| | | | | | Moved this code to sanitizer_common. llvm-svn: 177383
* Support CMake build of profile runtime library on LinuxAlexey Samsonov2013-03-193-5/+21
| | | | llvm-svn: 177382
* tsan: do not allocate sync vars on relaxed atomic operationsDmitry Vyukov2013-03-191-18/+26
| | | | | | helps to reduce memory consumption if an atomic is used only with relaxed ops (stats) llvm-svn: 177381
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