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* [Codestyle][x32] Cosmetic codestyle fix.Zinovy Nis2014-07-101-6/+6
| | | | llvm-svn: 212728
* Support the built-in type-trait support in gcc 4.7 and later. Thanks to ↵Marshall Clow2014-07-101-46/+42
| | | | | | Albert Wong for the patch. llvm-svn: 212727
* [mips] Added FPXX modeless calling convention.Zoran Jovanovic2014-07-107-1/+100
| | | | | | Differential Revision: http://reviews.llvm.org/D4293 llvm-svn: 212726
* [x32] Adding X32 target support to driver, including ↵Zinovy Nis2014-07-1021-28/+153
| | | | | | | | | | TargetInfo,DescriptionString, flags, paths lookup, etc. Cover changes with new tests. The author of the patch is Pavel Chupin (@pavel.v.chupin). The changes enable "hello world" on x32 target (x86_64-*-linux-gnux32). s/isX32/IsX32/ also fixed. Differential Revision: http://reviews.llvm.org/D4180 llvm-svn: 212725
* Add support for BIONIC C library (Android). Patch from Dan AlbertMarshall Clow2014-07-105-12/+217
| | | | llvm-svn: 212724
* Fix warning in test - missing exception specifier for overload of operator newMarshall Clow2014-07-101-1/+1
| | | | llvm-svn: 212723
* [AArch64] Add logical alias instructions to MC AsmParserArnaud A. de Grandmaison2014-07-105-17/+124
| | | | | | | | | | | | | | | | This patch teaches the AsmParser to accept some logical+immediate instructions and convert them as shown: bic Rd, Rn, #imm -> and Rd, Rn, #~imm bics Rd, Rn, #imm -> ands Rd, Rn, #~imm orn Rd, Rn, #imm -> orr Rd, Rn, #~imm eon Rd, Rn, #imm -> eor Rd, Rn, #~imm Those instructions are an alternate syntax available to assembly coders, and are needed in order to support code already compiling with some other assemblers. For example, the bic construct is used by the linux kernel. llvm-svn: 212722
* Reapply typo fix.Bruce Mitchener2014-07-101-1/+1
| | | | | | This was lost in the re-merging of command validation changes. llvm-svn: 212721
* Feeding isSafeToSpeculativelyExecute its DataLayout pointerHal Finkel2014-07-107-36/+52
| | | | | | | | | | | | | | isSafeToSpeculativelyExecute can optionally take a DataLayout pointer. In the past, this was mainly used to make better decisions regarding divisions known not to trap, and so was not all that important for users concerned with "cheap" instructions. However, now it also helps look through bitcasts for dereferencable loads, and will also be important if/when we add a dereferencable pointer attribute. This is some initial work to feed a DataLayout pointer through to callers of isSafeToSpeculativelyExecute, generally where one was already available. llvm-svn: 212720
* [mips][mips64r6] Add support for mips-img-linux-gnu GCC toolchainsDaniel Sanders2014-07-1057-13/+225
| | | | | | | | | | | | | | Summary: * Support the multilib layout used by the mips-img-linux-gnu * Recognize mips{,64}{,el}-img-linux-gnu as being aliases of mips-img-linux-gnu * Use the correct dynamic linker for mips-img-linux-gnu * Make mips32r6/mips64r6 the default CPU for mips-img-linux-gnu Subscribers: mpf Differential Revision: http://reviews.llvm.org/D4436 llvm-svn: 212719
* AArch64: correctly fast-isel i8 & i16 multipliesTim Northover2014-07-102-0/+41
| | | | | | | | We were asking for a register for type i8 or i16 which caused an assert. rdar://problem/17620015 llvm-svn: 212718
* [mips] Add support for -modd-spreg/-mno-odd-spregDaniel Sanders2014-07-1016-98/+462
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When -mno-odd-spreg is in effect, 32-bit floating point values are not permitted in odd FPU registers. The option also prohibits 32-bit and 64-bit floating point comparison results from being written to odd registers. This option has three purposes: * It allows support for certain MIPS implementations such as loongson-3a that do not allow the use of odd registers for single precision arithmetic. * When using -mfpxx, -mno-odd-spreg is the default and this allows us to statically check that code is compliant with the O32 FPXX ABI since mtc1/mfc1 instructions to/from odd registers are guaranteed not to appear for any reason. Once this has been established, the user can then re-enable -modd-spreg to regain the use of all 32 single-precision registers. * When using -mfp64 and -mno-odd-spreg together, an O32 extension named O32 FP64A is used as the ABI. This is intended to provide almost all functionality of an FR=1 processor but can also be executed on a FR=0 core with the assistance of a hardware compatibility mode which emulates FR=0 behaviour on an FR=1 processor. * Added '.module oddspreg' and '.module nooddspreg' each of which update the .MIPS.abiflags section appropriately * Moved setFpABI() call inside emitDirectiveModuleFP() so that the caller doesn't have to remember to do it. * MipsABIFlags now calculates the flags1 and flags2 member on demand rather than trying to maintain them in the same format they will be emitted in. There is one portion of the -mfp64 and -mno-odd-spreg combination that is not implemented yet. Moves to/from odd-numbered double-precision registers must not use mtc1. I will fix this in a follow-up. Differential Revision: http://reviews.llvm.org/D4383 llvm-svn: 212717
* [x32] Add AsmBackend for X32 which uses ELF32 with x86_64 (the author is ↵Zinovy Nis2014-07-101-0/+14
| | | | | | | | | | Pavel Chupin). This is minimal change for backend required to have "hello world" compiled and working on x32 target (x86_64-linux-gnux32). More patches for x32 will follow. Differential Revision: http://reviews.llvm.org/D4181 llvm-svn: 212716
* [msan] Fix performance issue in fast_memset.Evgeniy Stepanov2014-07-101-5/+6
| | | | | | Fast path was never triggered when called from __msan_poison. llvm-svn: 212715
* [x86,SDAG] Introduce any- and sign-extend-vector-inreg nodes analogousChandler Carruth2014-07-109-9/+165
| | | | | | | | | | | | | | | | | | | | to the zero-extend-vector-inreg node introduced previously for the same purpose: manage the type legalization of widened extend operations, especially to support the experimental widening mode for x86. I'm adding both because sign-extend is expanded in terms of any-extend with shifts to propagate the sign bit. This removes the last fundamental scalarization from vec_cast2.ll (a test case that hit many really bad edge cases for widening legalization), although the trunc tests in that file still appear scalarized because the the shuffle legalization is scalarizing. Funny thing, I've been working on that. Some initial experiments with this and SSE2 scenarios is showing moderately good behavior already for sign extension. Still some work to do on the shuffle combining on X86 before we're generating optimal sequences, but avoiding scalarization is a huge step forward. llvm-svn: 212714
* [mach-o]: support -Z option to skip standard library pathsTim Northover2014-07-103-2/+28
| | | | llvm-svn: 212713
* [mach-o]: support user-specified (-L) library search pathsTim Northover2014-07-105-5/+45
| | | | llvm-svn: 212712
* [SystemZ] Use SystemZCallingConv.td to define callee-saved registersRichard Sandiford2014-07-105-16/+23
| | | | | | Just a clean-up. No behavioral change intended. llvm-svn: 212711
* SpecialCaseList.h: Fix -Wdocumentation with \code.NAKAMURA Takumi2014-07-101-0/+2
| | | | llvm-svn: 212710
* llvm/test/CodeGen/X86/shift-parts.ll: FileCheck-ize. (from r212640)NAKAMURA Takumi2014-07-101-1/+3
| | | | llvm-svn: 212709
* Revert r212640, "Add trunc (select c, a, b) -> select c (trunc a), (trunc b) ↵NAKAMURA Takumi2014-07-103-54/+3
| | | | | | | | combine." This caused miscompilation on, at least, x86-64. SExt(i1 cond) confused other optimizations. llvm-svn: 212708
* [SystemZ] Tweak instruction format classificationsRichard Sandiford2014-07-102-53/+43
| | | | | | | | | | There's no real need to have Shift as a separate format type from Binary. The comments for other format types were too specific and in some cases no longer accurate. Just a clean-up, no behavioral change intended. llvm-svn: 212707
* [mach-o]: support -syslibroot and -l optionsTim Northover2014-07-1012-4/+288
| | | | | | | | | | | | | | | | | | | | | | | | | | These behave slightly idiosyncratically in the best of cases, and have additional hacks layered on top of that for compatibility with badly behaved build systems (via ld64). For -lXYZ: + If XYZ is actually XY.o then search all library paths for XY.o + Otherwise search all library paths, first for libXYZ.dylib, then libXYZ.a + By default the library paths are /usr/lib and /usr/local/lib in that order. For -syslibroot: + -syslibroot options apply to absolute paths in the search order. + All -syslibroot prefixes that exist are added to the search path *instead* of the original. + If no -syslibroot prefixed path exists, the original is kept. + Hacks^WExceptions: + If only 1 -syslibroot is given and doesn't contain /usr/lib or /usr/local/lib, that path is dropped entirely. (rdar://problem/6438270). + If the last -syslibroot is "/", all of them are ignored entirely. (rdar://problem/5829579). At least, that's my best interpretation of what ld64 does in buildSearchPaths. llvm-svn: 212706
* [x86] Add another combine that is particularly useful for the new vectorChandler Carruth2014-07-102-3/+52
| | | | | | | | | | shuffle lowering: match shuffle patterns equivalent to an unpcklwd or unpckhwd instruction. This allows us to use generic lowering code for v8i16 shuffles and match the unpack pattern late. llvm-svn: 212705
* [msan] Switch chained origins hash to murmur2.Evgeniy Stepanov2014-07-101-1/+24
| | | | llvm-svn: 212704
* [SystemZ] Add MC support for LEDBRA, LEXBRA and LDXBRARichard Sandiford2014-07-105-0/+172
| | | | | | | These instructions aren't used for codegen since the original L*DB instructions are suitable for fround. llvm-svn: 212703
* [SystemZ] Avoid using i8 constants for immediate fieldsRichard Sandiford2014-07-105-58/+54
| | | | | | | | | | | | Immediate fields that have no natural MVT type tended to use i8 if the field was small enough. This was a bit confusing since i8 isn't a legal type for the target. Fields for short immediates in a 32-bit or 64-bit operation use i32 or i64 instead, so it would be better to do the same for all fields. No behavioral change intended. llvm-svn: 212702
* [SystemZ] Fix FPR dwarf numberingRichard Sandiford2014-07-102-14/+62
| | | | | | | | The dwarf FPR numbers are supposed to have the order F0, F2, F4, F6, F1, F3, F5, F7, F8, etc., which matches the pairing of registers for long doubles. E.g. a long double stored in F0 is paired with F2. llvm-svn: 212701
* [mips] Add support for -modd-spreg/-mno-odd-spregDaniel Sanders2014-07-103-0/+18
| | | | | | Differential Revision: http://reviews.llvm.org/D4432 llvm-svn: 212700
* [ASan/Win] Don't hardcode ASan runtime version in ASan dll thunkTimur Iskhodzhanov2014-07-105-18/+46
| | | | | | Reviewed at http://reviews.llvm.org/D4459 llvm-svn: 212699
* Get the inferior binary's name via the command line argument insteadJason Molenda2014-07-101-2/+24
| | | | | | of hardcoding it. llvm-svn: 212698
* Make it possible for ints/floats to return different values from ↵Daniel Sanders2014-07-1015-137/+254
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | getBooleanContents() Summary: On MIPS32r6/MIPS64r6, floating point comparisons return 0 or -1 but integer comparisons return 0 or 1. Updated the various uses of getBooleanContents. Two simplifications had to be disabled when float and int boolean contents differ: - ScalarizeVecRes_VSELECT except when the kind of boolean contents is trivially discoverable (i.e. when the condition of the VSELECT is a SETCC node). - visitVSELECT (select C, 0, 1) -> (xor C, 1). Come to think of it, this one could test for the common case of 'C' being a SETCC too. Preserved existing behaviour for all other targets and updated the affected MIPS32r6/MIPS64r6 tests. This also fixes the pi benchmark where the 'low' variable was counting in the wrong direction because it thought it could simply add the result of the comparison. Reviewers: hfinkel Reviewed By: hfinkel Subscribers: hfinkel, jholewinski, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D4389 llvm-svn: 212697
* MachO: add dummy armv6m architecture directory so clang_macho_embedded ↵Tim Northover2014-07-102-1/+21
| | | | | | | | | | | | | | | | | | | builds things. Without some mention of armv6m in a subdirectory of builtins, the make code doesn't even know that armv6m exists and is something it should be looking for in the platform-specific Makefiles. This means that none of the functions listed actually get built and we end up with an almost entirely empty libclang_rt.a for armv6m. Unfortunately, the assembly code in the usual arm directory has no hope of running on armv6m, which only supports Thumb-1 (not even ARM mode), so adding it there won't work. Realistically, we probably *will* want to put any optimised versions in a separate directory, so creating it now is harmless. rdar://problem/17613576 llvm-svn: 212696
* [x86] Expand the target DAG combining for PSHUFD nodes to be able toChandler Carruth2014-07-102-5/+35
| | | | | | | | | | combine into half-shuffles through unpack instructions that expand the half to a whole vector without messing with the dword lanes. This fixes some redundant instructions in splat-like lowerings for v16i8, which are now getting to be *really* nice. llvm-svn: 212695
* Fix test name.Jason Molenda2014-07-101-1/+1
| | | | llvm-svn: 212694
* Make sanitizers' interceptors non-weak on FreeBSDViktor Kutuzov2014-07-101-0/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D4418 llvm-svn: 212693
* [x86] Tweak the v16i8 single input special case lowering for shufflesChandler Carruth2014-07-102-45/+51
| | | | | | | | | | | | | | | | | | | that splat i8s into i16s. Previously, we would try much too hard to arrange a sequence of i8s in one half of the input such that we could unpack them into i16s and shuffle those into place. This isn't always going to be a cheaper i8 shuffle than our other strategies. The case where it is always going to be cheaper is when we can arrange all the necessary inputs into one half using just i16 shuffles. It happens that viewing the problem this way also makes it much easier to produce an efficient set of shuffles to move the inputs into one half and then unpack them. With this, our splat code gets one step closer to being not terrible with the new experimental lowering strategy. It also exposes two combines missing which I will add next. llvm-svn: 212692
* Only use fast stack unwinding for sanitizers failure reports on FreeBSDViktor Kutuzov2014-07-101-1/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D4420 llvm-svn: 212691
* Fix getting environment variables for sanitizers needs on FreeBSDViktor Kutuzov2014-07-101-8/+16
| | | | | | Differential Revision: http://reviews.llvm.org/D4229 llvm-svn: 212690
* Add clang headers that fix machine-dependent definitions on FreeBSD 9.2Viktor Kutuzov2014-07-103-0/+218
| | | | | | Differential Revision: http://reviews.llvm.org/D3908 llvm-svn: 212689
* A test case for not asserting in isDereferenceablePointer upon unsized typesHal Finkel2014-07-101-0/+41
| | | | | | This is the test case for r212687. llvm-svn: 212688
* Fix isDereferenceablePointer not to try to take the size of an unsized type.Hal Finkel2014-07-101-1/+2
| | | | | | I'll add a test-case shortly. llvm-svn: 212687
* Allow isDereferenceablePointer to look through some bitcastsHal Finkel2014-07-108-21/+202
| | | | | | | | | | | | | | | | isDereferenceablePointer should not give up upon encountering any bitcast. If we're casting from a pointer to a larger type to a pointer to a small type, we can continue by examining the bitcast's operand. This missing capability was noted in a comment in the function. In order for this to work, isDereferenceablePointer now takes an optional DataLayout pointer (essentially all callers already had such a pointer available). Most code uses isDereferenceablePointer though isSafeToSpeculativelyExecute (which already took an optional DataLayout pointer), and to enable the LICM test case, LICM needs to actually provide its DL pointer to isSafeToSpeculativelyExecute (which it was not doing previously). llvm-svn: 212686
* Fix a type mismatch in NativeProcessLinux that shows up in 32-bit builds.Todd Fiala2014-07-101-1/+1
| | | | | | http://llvm.org/bugs/show_bug.cgi?id=20255 llvm-svn: 212685
* MC: modernise for loopSaleem Abdulrasool2014-07-101-13/+9
| | | | | | Convert a for loop to range bsaed form. NFC. llvm-svn: 212684
* MC: add and use an accessor for WinCFISaleem Abdulrasool2014-07-102-14/+18
| | | | | | | | | | This adds a utility method to access the WinCFI information in bulk and uses that to iterate rather than requesting the count and individually iterating them. This is in preparation for restructuring WinCFI handling to enable more clear sharing across architectures to enable unwind information emission for Windows on ARM. llvm-svn: 212683
* Remove move assignment operator to appease older GCCs.Peter Collingbourne2014-07-101-5/+0
| | | | llvm-svn: 212682
* Fixes for broken Debian build - g++ 4.7 support.Todd Fiala2014-07-103-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | These fix the broken debian lldb build, which is using g++ 4.7.2. TypeFormat changes: 1. stopped using the C++11 "dtor = default;" construct. The generated default destructor in the two derived classes wanted them to have a different throws() semantic that was causing 4.7 to fail to generate it. I switched these to empty destructors defined in the .cpp file. 2. Switched the m_types map from an ordered map to an unordered_map. g++ 4.7's c++ library supports the C++11 emplace() used by TypeFormat but the same c++ library's map impl does not. Since TypeFormat didn't look like it depended on ordering in the map, I just switched it to a std::unordered_map. NativeProcessLinux - g++ 4.7 chokes on lexing the "<::" in static_cast<::pid_t>(wpid). g++ 4.8+ and clang are fine with it. I just put a space in between the "<" and the "::" and that cleared it up. llvm-svn: 212681
* [x86] Initial improvements to the new shuffle lowering for v16i8Chandler Carruth2014-07-102-27/+57
| | | | | | | | | | | | | shuffles specifically for cases where a small subset of the elements in the input vector are actually used. This is specifically targetted at improving the shuffles generated for trunc operations, but also helps out splat-like operations. There is still some really low-hanging fruit here that I want to address but this is a huge step in the right direction. llvm-svn: 212680
* Explicitly define move constructor and move assignment operator to appease MSVC.Peter Collingbourne2014-07-101-0/+9
| | | | llvm-svn: 212679
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