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* [llvm-mca] Add the ability to customize the instruction selection strategy ↵Andrea Di Biagio2018-08-212-34/+64
| | | | | | | | | | | | | | | | | | | | | | in the Scheduler. The constructor of Scheduler now accepts a SchedulerStrategy object, which is used internally by method Scheduler::select() to drive the instruction selection process. The goal of this patch is to enable the definition of custom selection strategies while reusing the same algorithms implemented by class Scheduler. The motivation is that, on some targets, the default strategy may not well approximate the selection logic in the hardware schedulers. This patch also adds the ability to pass a ResourceManager object to the constructor of Scheduler. This gives a bit more flexibility to the design, and potentially it allows to expose processor resources to SchedulerStrategy objects. Differential Revision: https://reviews.llvm.org/D51051 llvm-svn: 340314
* [X86][SSE] Add non-uniform udiv test that is mostly divide by 1.Simon Pilgrim2018-08-211-0/+178
| | | | | | The test demonstrates over-complicated codegen for a udiv that only has one divisor that doesn't equal 1. This should have allowed the codegen to be a lot simpler (uniform shifts etc.) but only the SSE2 manages to make use of this...... llvm-svn: 340313
* [AST] Remove notion of volatile from alias sets [NFCI]Philip Reames2018-08-214-38/+12
| | | | | | | | | | Volatility is not an aliasing property. We used to model volatile as if it had extremely conservative aliasing implications, but that hasn't been true for several years now. So, it doesn't make sense to be in AliasSet. It also turns out the code is entirely a noop. Outside of the AST code to update it, there was only one user: load store promotion in LICM. L/S promotion doesn't need the check since it walks all the users of the address anyway. It already checks each load or store via !isUnordered which causes us to bail for volatile accesses. (Look at the lines immediately following the two remove asserts.) There is the possibility of some small compile time impact here, but the only case which will get noticeably slower is a loop with a large number of loads and stores to the same address where only the last one we inspect is volatile. This is sufficiently rare it's not worth optimizing for.. llvm-svn: 340312
* Address Aaron Ballman's post-commit review comments from r340306, NFCErik Pilkington2018-08-212-4/+9
| | | | llvm-svn: 340311
* Update DBG_VALUE register operand during LiveInterval operationsYury Delendik2018-08-212-11/+121
| | | | | | | | | | | | | | | | | | | Summary: Handling of DBG_VALUE in ConnectedVNInfoEqClasses::Distribute() was fixed in PR16110. However DBG_VALUE register operands are not getting updated. This patch properly resolves the value location. Reviewers: MatzeB, vsk Reviewed By: MatzeB Subscribers: kparzysz, thegameg, vsk, MatzeB, dschuff, sbc100, jgravelle-google, aheejin, sunfish, llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D48994 llvm-svn: 340310
* Revert "Revert rr340111 "[GISel]: Add Legalization/lowering code for bit ↵Aditya Nandakumar2018-08-217-1/+518
| | | | | | | | | | | | | | | counting operations"" This reverts commit d1341152d91398e9a882ba2ee924147ea2f9b589. This patch originally made use of Nested MachineIRBuilder buildInstr calls, and since order of argument processing is not well defined, the instructions were built slightly in a different order (still correct). I've removed the nested buildInstr calls to have a defined order now. Patch was tested by Mikael. llvm-svn: 340309
* SafeStack: Use correct unsafe stack sizesVlad Tsyrklevich2018-08-212-1/+56
| | | | | | | | | | | | | | | | | Summary: When deallocating thread stacks, we use one thread's unsafe stack size to deallocate another thread's unsafe stack; however, the two sizes may differ. Record an unsafe stack's size in the thread stack linked list. Reviewers: pcc, eugenis Reviewed By: eugenis Subscribers: delcypher, llvm-commits, #sanitizers, kcc Differential Revision: https://reviews.llvm.org/D51016 llvm-svn: 340308
* [X86][SSE] Lower vXi8 general shifts to SSE shifts directly. NFCI.Simon Pilgrim2018-08-211-26/+17
| | | | | | Most of these shifts are extended to vXi16 so we don't gain anything from forcing another round of generic shift lowering - we know these extended cases are legal constant splat shifts. llvm-svn: 340307
* Add a new flag and attributes to control static destructor registrationErik Pilkington2018-08-2118-1/+197
| | | | | | | | | | | | | | | | | | | | This commit adds the flag -fno-c++-static-destructors and the attributes [[clang::no_destroy]] and [[clang::always_destroy]]. no_destroy specifies that a specific static or thread duration variable shouldn't have it's destructor registered, and is the default in -fno-c++-static-destructors mode. always_destroy is the opposite, and is the default in -fc++-static-destructors mode. A variable whose destructor is disabled (either because of -fno-c++-static-destructors or [[clang::no_destroy]]) doesn't count as a use of the destructor, so we don't do any access checking or mark it referenced. We also don't emit -Wexit-time-destructors for these variables. rdar://21734598 Differential revision: https://reviews.llvm.org/D50994 llvm-svn: 340306
* llvm-readobj: Simplify. NFCI.Peter Collingbourne2018-08-211-1/+1
| | | | llvm-svn: 340305
* [ASTImporter] Add test for CXXNoexceptExprRaphael Isemann2018-08-212-0/+9
| | | | | | | | | | | | Reviewers: a.sidorin, a_sidorin Reviewed By: a_sidorin Subscribers: a_sidorin, hiraditya, martong, cfe-commits Differential Revision: https://reviews.llvm.org/D50737 llvm-svn: 340304
* [BypassSlowDivision] Teach bypass slow division not to interfere with div by ↵Craig Topper2018-08-212-68/+35
| | | | | | | | | | | | | | constant where constants have been constant hoisted, but not moved from their basic block DAGCombiner doesn't pay attention to whether constants are opaque before doing the div by constant optimization. So BypassSlowDivision shouldn't introduce control flow that would make DAGCombiner unable to see an opaque constant. This can occur when a div and rem of the same constant are used in the same basic block. it will be hoisted, but not leave the block. Longer term we probably need to look into the X86 immediate cost model used by constant hoisting and maybe not mark div/rem immediates for hoisting at all. This fixes the case from PR38649. Differential Revision: https://reviews.llvm.org/D51000 llvm-svn: 340303
* [X86][SSE] Lower v8i16 general shifts to SSE shifts directly. NFCI.Simon Pilgrim2018-08-211-9/+9
| | | | | | We don't gain anything from forcing another round of generic shift lowering - we know these are legal constant splat shifts. llvm-svn: 340302
* [Parser] Support alternative operator token keyword args in Objective-C++Erik Pilkington2018-08-212-0/+54
| | | | | | | | rdar://30741878 Differential revision: https://reviews.llvm.org/D50527 llvm-svn: 340301
* [X86][SSE] Lower directly to SSE shifts in the BLEND(SHIFT, SHIFT) combine. ↵Simon Pilgrim2018-08-211-9/+13
| | | | | | | | NFCI. We don't gain anything from forcing another round of generic shift lowering - we know these are legal constant splat shifts. llvm-svn: 340300
* [ASTImporter] Add test for CXXForRangeStmtRaphael Isemann2018-08-212-0/+64
| | | | | | | | | | | | Reviewers: a.sidorin, martong Reviewed By: martong Subscribers: rnkovacs, martong, cfe-commits Differential Revision: https://reviews.llvm.org/D51001 llvm-svn: 340297
* Try to fix bot build failureMatt Arsenault2018-08-211-1/+1
| | | | llvm-svn: 340296
* [AMDGPU] Support idot2 pattern.Farhana Aleen2018-08-213-0/+1873
| | | | | | | | | | | | | | | | Summary: Transform add (mul ((i32)S0.x, (i32)S1.x), add( mul ((i32)S0.y, (i32)S1.y), (i32)S3) => i/udot2((v2i16)S0, (v2i16)S1, (i32)S3) Author: FarhanaAleen Reviewed By: arsenm Subscribers: llvm-commits, AMDGPU Differential Revision: https://reviews.llvm.org/D50024 llvm-svn: 340295
* lldbtest.py: Unconditionally set the clang module cache path.Adrian Prantl2018-08-212-13/+11
| | | | | | This should fix the errors observable on the new lldb-cmake bot. llvm-svn: 340293
* AMDGPU: Move target code into TargetParserMatt Arsenault2018-08-212-193/+77
| | | | llvm-svn: 340292
* AMDGPU: Partially move target handling code from clang to TargetParserMatt Arsenault2018-08-212-0/+227
| | | | | | | | | | | | | | | | | | | | A future change in clang necessitates access of this information from the driver, so move this into a common place. Try to mimic something resembling the API the other targets are using here. One thing I'm uncertain about is how to split amdgcn and r600 handling. Here I've mostly duplicated the functions for each, while keeping the same enums. I think this is a bit awkward for the features which don't matter for amdgcn. It's also a bit messy that this isn't a complete set of subtarget features. This is just the minimum set needed for the driver code. For example building the list of subtarget feature names is still in clang. llvm-svn: 340291
* [X86][SSE] Add helper function to convert to/between the SSE vector shift ↵Simon Pilgrim2018-08-211-36/+33
| | | | | | | | opcodes. NFCI. Also remove some more getOpcode calls from LowerShift when we already have Opc. llvm-svn: 340290
* [clang][NFC] Fix typo in the name of a noteLouis Dionne2018-08-212-2/+2
| | | | | | | | | | | | | | Summary: r306722 introduced a new note called note_silence_unligned_allocation_unavailable where I believe what was meant is note_silence_aligned_allocation_unavailable. Reviewers: ahatanak Subscribers: dexonsmith, cfe-commits Differential Revision: https://reviews.llvm.org/D51043 llvm-svn: 340288
* [aarch64][mc] Don't lookup symbols when there is no symbol lookup callbackDaniel Sanders2018-08-211-0/+2
| | | | | | | | | | | | | | Summary: When run under llvm-mc-disassemble-fuzzer, there is no symbol lookup callback so tryAddingSymbolicOperand() must fail gracefully instead of crashing Reviewers: aemerson, javed.absar Reviewed By: aemerson Subscribers: lhames, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D51005 llvm-svn: 340287
* Makefile.rules: Use an absolute path to the module cache directory.Adrian Prantl2018-08-211-1/+2
| | | | | | This change is NFC, but it makes it more obvious in log files what happened. llvm-svn: 340286
* [InstCombine] Add new tests for icmp ugt/ult (add nuw X, C2), CNicola Zaghen2018-08-211-0/+43
| | | | | | Differential Revision: https://reviews.llvm.org/D51040 llvm-svn: 340284
* [X86] Add SSE2 and XOP udiv combine testsSimon Pilgrim2018-08-211-155/+515
| | | | llvm-svn: 340282
* [PPC64] Add TLS initial exec to local exec relaxationZaara Syeda2018-08-215-3/+277
| | | | | | | | | This patch adds the target call back relaxTlsIeToLe to support TLS relaxation from initial exec to local exec model. Differential Revision: https://reviews.llvm.org/D48091 llvm-svn: 340281
* [analyzer] Correctly marked a virtual function 'override'Kristof Umann2018-08-211-1/+1
| | | | llvm-svn: 340280
* [InstSimplify] use isKnownNeverNaN to fold more fcmp ord/unoSanjay Patel2018-08-213-260/+33
| | | | | | | | | | | Remove duplicate tests from InstCombine that were added with D50582. I left negative tests there to verify that nothing in InstCombine tries to go overboard. If isKnownNeverNaN is improved to handle the FP binops or other cases, we should have coverage under InstSimplify, so we could remove more duplicate tests from InstCombine at that time. llvm-svn: 340279
* [LV] Vectorize loops where non-phi instructions used outside loopAnna Thomas2018-08-213-7/+183
| | | | | | | | | | | | | | | | | | | Summary: Follow up change to rL339703, where we now vectorize loops with non-phi instructions used outside the loop. Note that the cyclic dependency identification occurs when identifying reduction/induction vars. We also need to identify that we do not allow users where the PSCEV information within and outside the loop are different. This was the fix added in rL307837 for PR33706. Reviewers: Ayal, mkuper, fhahn Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D50778 llvm-svn: 340278
* [ASTImporter] Adding some friend function related unittests.Balazs Keri2018-08-211-0/+205
| | | | | | | | | | | | Reviewers: a.sidorin, a_sidorin Reviewed By: a_sidorin Subscribers: a_sidorin, martong, cfe-commits Differential Revision: https://reviews.llvm.org/D49798 llvm-svn: 340277
* [InstSimplify] add tests for FP uno/ord with nnan; NFCSanjay Patel2018-08-211-0/+424
| | | | | | | | | This is a slight modification of the tests from D50582; change half of the predicates to 'uno' so we have coverage for that side too. All of the positive tests can fold to a constant (true/false), so that should happen in instsimplify. llvm-svn: 340276
* NFC: Add loop vectorizer tests showing various control flow within loop that ↵Anna Thomas2018-08-211-0/+169
| | | | | | skip iterations llvm-svn: 340275
* [llvm-mca] Replace use of llvm::any_of with std::any_of.Andrea Di Biagio2018-08-211-2/+3
| | | | | | This should unbreak the buildbots. llvm-svn: 340274
* [llvm-mca] Add method cycleEvent() to class Scheduler. NFCIAndrea Di Biagio2018-08-216-110/+123
| | | | | | | | | | | | | | | | | | | | The goal of this patch is to simplify the Scheduler's interface in preparation for D50929. Some methods in the Scheduler's interface should not be exposed to external users, since their presence makes it hard to both understand, and extend the Scheduler's interface. This patch removes the following two methods from the public Scheduler's API: - reclaimSimulatedResources() - updatePendingQueue() Their logic has been migrated to a new method named 'cycleEvent()'. Methods 'updateIssuedSet()' and 'promoteToReadySet()' still exist. However, they are now private members of class Scheduler. This simplifies the interaction with the Scheduler from the ExecuteStage. llvm-svn: 340273
* [analyzer][UninitializedObjectChecker] Explicit namespace resolution for ↵Kristof Umann2018-08-213-23/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | inherited data members For the following example: struct Base { int x; }; // In a different translation unit struct Derived : public Base { Derived() {} }; For a call to Derived::Derived(), we'll receive a note that this->x is uninitialized. Since x is not a direct field of Derived, it could be a little confusing. This patch aims to fix this, as well as the case when the derived object has a field that has the name as an inherited uninitialized data member: struct Base { int x; // note: uninitialized field 'this->Base::x' }; struct Derived : public Base { int x = 5; Derived() {} }; Differential Revision: https://reviews.llvm.org/D50905 llvm-svn: 340272
* Add missing library dependency to fix build break after rC340247Hiroshi Inoue2018-08-211-0/+1
| | | | llvm-svn: 340271
* [AMDGPU] Allow int types for MUBUF vdataTim Renouf2018-08-216-4/+100
| | | | | | | | | | | | | | | | | Summary: Previously the new llvm.amdgcn.raw/struct.buffer.load/store intrinsics only allowed float types for the data to be loaded or stored, which sometimes meant the frontend needed to generate a bitcast. In this, the new intrinsics copied the old buffer intrinsics. This commit extends the new intrinsics to allow int types as well. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D50315 Change-Id: I8202af2d036455553681dcbb3d7d32ae273f8f85 llvm-svn: 340270
* [AMDGPU] New buffer intrinsicsTim Renouf2018-08-2122-179/+2033
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This commit adds new intrinsics llvm.amdgcn.raw.buffer.load llvm.amdgcn.raw.buffer.load.format llvm.amdgcn.raw.buffer.load.format.d16 llvm.amdgcn.struct.buffer.load llvm.amdgcn.struct.buffer.load.format llvm.amdgcn.struct.buffer.load.format.d16 llvm.amdgcn.raw.buffer.store llvm.amdgcn.raw.buffer.store.format llvm.amdgcn.raw.buffer.store.format.d16 llvm.amdgcn.struct.buffer.store llvm.amdgcn.struct.buffer.store.format llvm.amdgcn.struct.buffer.store.format.d16 llvm.amdgcn.raw.buffer.atomic.* llvm.amdgcn.struct.buffer.atomic.* with the following changes from the llvm.amdgcn.buffer.* intrinsics: * there are separate raw and struct versions: raw does not have an index arg and sets idxen=0 in the instruction, and struct always sets idxen=1 in the instruction even if the index is 0, to allow for the fact that gfx9 does bounds checking differently depending on whether idxen is set; * there is a combined cachepolicy arg (glc+slc) * there are now only two offset args: one for the offset that is included in bounds checking and swizzling, to be split between the instruction's voffset and immoffset fields, and one for the offset that is excluded from bounds checking and swizzling, to go into the instruction's soffset field. The AMDISD::BUFFER_* SD nodes always have an index operand, all three offset operands, combined cachepolicy operand, and an extra idxen operand. The obsolescent llvm.amdgcn.buffer.* intrinsics continue to work. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D50306 Change-Id: If897ea7dc34fcbf4d5496e98cc99a934f62fc205 llvm-svn: 340269
* [AMDGPU] New tbuffer intrinsicsTim Renouf2018-08-2118-106/+971
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This commit adds new intrinsics llvm.amdgcn.raw.tbuffer.load llvm.amdgcn.struct.tbuffer.load llvm.amdgcn.raw.tbuffer.store llvm.amdgcn.struct.tbuffer.store with the following changes from the llvm.amdgcn.tbuffer.* intrinsics: * there are separate raw and struct versions: raw does not have an index arg and sets idxen=0 in the instruction, and struct always sets idxen=1 in the instruction even if the index is 0, to allow for the fact that gfx9 does bounds checking differently depending on whether idxen is set; * there is a combined format arg (dfmt+nfmt) * there is a combined cachepolicy arg (glc+slc) * there are now only two offset args: one for the offset that is included in bounds checking and swizzling, to be split between the instruction's voffset and immoffset fields, and one for the offset that is excluded from bounds checking and swizzling, to go into the instruction's soffset field. The AMDISD::TBUFFER_* SD nodes always have an index operand, all three offset operands, combined format operand, combined cachepolicy operand, and an extra idxen operand. The tbuffer pseudo- and real instructions now also have a combined format operand. The obsolescent llvm.amdgcn.tbuffer.* and llvm.SI.tbuffer.store intrinsics continue to work. V2: Separate raw and struct intrinsics. V3: Moved extract_glc and extract_slc defs to a more sensible place. V4: Rebased on D49995. V5: Only two separate offset args instead of three. V6: Pseudo- and real instructions have joint format operand. V7: Restored optionality of dfmt and nfmt in assembler. V8: Addressed minor review comments. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D49026 Change-Id: If22ad77e349fac3a5d2f72dda53c010377d470d4 llvm-svn: 340268
* Change how finalizeBundle selects debug location for the BUNDLE instructionBjorn Pettersson2018-08-212-1/+69
| | | | | | | | | | | | | | | | | | | | | | Summary: Previously a BUNDLE instruction inherited the DebugLoc from the first instruction in the bundle, even if that DebugLoc had no DILocation. With this commit this is changed into selecting the first DebugLoc that has a DILocation, by searching among the bundled instructions. The idea is to reduce amount of bundles that are lacking debug locations. Reviewers: #debug-info, JDevlieghere Reviewed By: JDevlieghere Subscribers: JDevlieghere, mattd, llvm-commits Differential Revision: https://reviews.llvm.org/D50639 llvm-svn: 340267
* [analyzer][UninitializedObjectChecker] Added documentation to the checker listKristof Umann2018-08-212-12/+112
| | | | | | Differential Revision: https://reviews.llvm.org/D50904 llvm-svn: 340266
* [analyzer][UninitializedObjectChecker] Refactoring p6.: Move dereferencing ↵Kristof Umann2018-08-213-60/+80
| | | | | | | | | | | | to a function Now that it has it's own file, it makes little sense for isPointerOrReferenceUninit to be this large, so I moved dereferencing to a separate function. Differential Revision: https://reviews.llvm.org/D50509 llvm-svn: 340265
* [X86] Add SSE2 sdiv combine testsSimon Pilgrim2018-08-211-651/+1452
| | | | llvm-svn: 340264
* [clangd] NFC: Fix broken buildKirill Bobyrev2018-08-211-6/+6
| | | | llvm-svn: 340263
* [clangd] Allow using experimental Dex indexKirill Bobyrev2018-08-215-13/+40
| | | | | | | | | | | This patch adds hidden Clangd flag ("use-dex-index") which replaces (currently) default `MemIndex` with `DexIndex` for the static index. Reviewed by: ioeric Differential Revision: https://reviews.llvm.org/D50897 llvm-svn: 340262
* [DAGCombiner] Reduce load widths of shifted masksSam Parker2018-08-213-47/+569
| | | | | | | | | | | During combining, ReduceLoadWdith is used to combine AND nodes that mask loads into narrow loads. This patch allows the mask to be a shifted constant. This results in a narrow load which is then left shifted to compensate for the new offset. Differential Revision: https://reviews.llvm.org/D50432 llvm-svn: 340261
* [TargetLowering] Add BuildSDiv support for division by one or negone.Simon Pilgrim2018-08-212-130/+119
| | | | | | This reduces most of the sdiv stages (the MULHS, shifts etc.) to just zero/identity values and use the numerator scale factor to multiply by +1/-1. llvm-svn: 340260
* [LLD][ELF] - Fix BB after r340257.George Rimar2018-08-211-1/+1
| | | | | | Renamed Filecheck->FileCheck. llvm-svn: 340259
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