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* Add "echo" -> "script print".Jim Ingham2012-05-111-0/+24
| | | | llvm-svn: 156624
* [fast-isel] Rather then assert (or segfault in a non-asserts build), fall backChad Rosier2012-05-111-2/+4
| | | | | | | | to selection DAG isel if we're unable to handle a non-double multi-reg retval. rdar://11430407 PR12796 llvm-svn: 156622
* The return type is an unsigned, not a bool.Chad Rosier2012-05-111-1/+1
| | | | llvm-svn: 156621
* Add space before an open parenthesis in control flow statements.Manman Ren2012-05-111-2/+2
| | | | llvm-svn: 156620
* [tsan] run output tests in parallelKostya Serebryany2012-05-111-21/+13
| | | | llvm-svn: 156617
* [tsan] run more kinds of builds as presubmit test (and fix gcc debug build)Kostya Serebryany2012-05-116-16/+24
| | | | llvm-svn: 156616
* Added X86 Atom latencies to X86InstrMMX.td.Preston Gurd2012-05-114-130/+350
| | | | llvm-svn: 156615
* [tsan] a bit more lintKostya Serebryany2012-05-112-2/+2
| | | | llvm-svn: 156614
* PR1255: ConstantRangesSet and CRSBuilder classes moved from include/llvm to ↵Stepan Dyatkovskiy2012-05-112-1/+1
| | | | | | include/llvm/Support. llvm-svn: 156613
* Fix test/CodeGen/X86/tls-pie.ll.Hans Wennborg2012-05-111-1/+1
| | | | llvm-svn: 156612
* Implement initial-exec TLS model for 32-bit PIC x86Hans Wennborg2012-05-115-20/+48
| | | | | | | This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong code here (see the update to test/CodeGen/X86/tls-pie.ll). llvm-svn: 156611
* Added the missing bit definition for the 4th bit of the STR (post reg) ↵Silviu Baranga2012-05-114-0/+72
| | | | | | instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. llvm-svn: 156609
* Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate ↵Silviu Baranga2012-05-113-3/+12
| | | | | | offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate. llvm-svn: 156608
* PR11857: When the wrong number of arguments are provided for a functionRichard Smith2012-05-117-15/+67
| | | | | | | which expects exactly one argument, include the name of the argument in the diagnostic text. Patch by Terry Long! llvm-svn: 156607
* Fix a use after free when the streamer is destroyed. Fixes pr12622.Rafael Espindola2012-05-111-1/+1
| | | | llvm-svn: 156606
* More fixes to "malloc_history".Greg Clayton2012-05-112-64/+90
| | | | llvm-svn: 156605
* Add a test case for going through typedefs until we reach "BOOL", that ↵Argyrios Kyrtzidis2012-05-111-0/+2
| | | | | | NSAPI::isObjCTypedef() is doing. llvm-svn: 156604
* Fix a misleading comment.Akira Hatanaka2012-05-111-1/+1
| | | | llvm-svn: 156603
* Tidy up. Trailing whitespace.Jim Grosbach2012-05-1112-35/+35
| | | | llvm-svn: 156602
* Tidy up. Trailing whitespace.Jim Grosbach2012-05-118-55/+55
| | | | llvm-svn: 156601
* Fix a minor logic mistake transforming compares in instcombine. PR12514.Eli Friedman2012-05-112-1/+16
| | | | llvm-svn: 156600
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-113-27/+162
| | | | | | | | | | | | | | | | | This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 llvm-svn: 156599
* Fix a recent regression with the merging of format attributes.Rafael Espindola2012-05-114-20/+50
| | | | llvm-svn: 156597
* Modified the symbolication.Image object to store its uuid as a uuid.UUID ↵Greg Clayton2012-05-112-27/+44
| | | | | | | | object and made an accessor for getting a normalized UUID value out of the image object. Modified the crashlog darwin module to always create a uuid.UUID object when making the symbolication.Image objects. Also modified it to handle some more types of crash log files and improved the register reading for thread registers of crashed threads. llvm-svn: 156596
* Don't intercept the quit command and override what is was doing. This was ↵Greg Clayton2012-05-111-12/+0
| | | | | | causing the "lldb" command line to deadlock when the quit command was executed sometimes. llvm-svn: 156595
* Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),Dan Gohman2012-05-118-2/+55
| | | | | | but it generates int3 on x86 instead of ud2. llvm-svn: 156593
* For final output files create them with mode 0664 to match otherEric Christopher2012-05-111-1/+2
| | | | | | | | compilers and expected defaults. Part of rdar://11325849 llvm-svn: 156592
* Allow unique_file to take a mode for file permissions, but defaultEric Christopher2012-05-113-7/+10
| | | | | | | | to user only read/write. Part of rdar://11325849 llvm-svn: 156591
* Fix intendation.Chad Rosier2012-05-101-1/+1
| | | | llvm-svn: 156589
* "--stack-history" now works if you have MallocStackLogggingNoCompact defined ↵Greg Clayton2012-05-102-8/+14
| | | | | | in your app's environment. llvm-svn: 156588
* Compute secondary sub-registers.Jakob Stoklund Olesen2012-05-102-3/+161
| | | | | | | | | | | | | | | | | | | | | | The sub-registers explicitly listed in SubRegs in the .td files form a tree. In a complicated register bank, it is possible to have sub-register relationships across sub-trees. For example, the ARM NEON double vector Q0_Q1 is a tree: Q0_Q1 = [Q0, Q1], Q0 = [D0, D1], Q1 = [D2, D3] But we also define the DPair register D1_D2 = [D1, D2] which is fully contained in Q0_Q1. This patch teaches TableGen to find such sub-register relationships, and assign sub-register indices to them. In the example, TableGen will create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a sub-register of Q0_Q1. This will eventually enable the coalescer to handle copies of skewed sub-registers. llvm-svn: 156587
* Fixed a build error.Greg Clayton2012-05-101-2/+2
| | | | llvm-svn: 156586
* objectsize: add support for GEPs with non-constant indexesNuno Lopes2012-05-104-34/+59
| | | | | | add an additional parameter to InstCombiner::EmitGEPOffset() to force it to *not* emit operations with NUW flag llvm-svn: 156585
* Added the ability to get the stack history for a malloc block. This is a ↵Greg Clayton2012-05-102-2/+101
| | | | | | work in progress. Checking this in so I can work on it some more. llvm-svn: 156584
* [objc] When boxing a BOOL/NSInteger/NSUInteger type, use the correspondingArgyrios Kyrtzidis2012-05-106-8/+174
| | | | | | | | numberWithBool:/numberWithInteger:/numberWithUnsignedInteger: NSNumber selectors. rdar://11428703 llvm-svn: 156583
* Include line that was meant to be in my last commit.Ted Kremenek2012-05-101-1/+2
| | | | llvm-svn: 156582
* Make crashlog.py more robust when dealing with the "Version: ..." header ↵Johnny Chen2012-05-101-2/+8
| | | | | | | | from the crash log file. rdar://problem/11428134 llvm-svn: 156581
* Fix insidious RegionStore bug where we (a) didn't handle vector types and ↵Ted Kremenek2012-05-101-10/+68
| | | | | | | | | | | | (b) had a horrible bug in GetLazyBindings where we falsely appended a field suffix when traversing 3 or more layers of lazy bindings. I don't have a reduced test case yet; but I have added the original source to an internal regression test suite. I'll see about coming up with a reduced test case. Fixes <rdar://problem/11405978> (for real). llvm-svn: 156580
* Added X86 Atom latencies for instructions in X86InstrInfo.td.Preston Gurd2012-05-103-223/+426
| | | | llvm-svn: 156579
* [analyzer] Exit early if constraint solver is given a non-integer symbolAnna Zaks2012-05-102-0/+13
| | | | | | | | | | | to reason about. As part of taint propagation, we now allow creation of non-integer symbolic expressions like a cast from int to float. Addresses PR12511 (radar://11215362). llvm-svn: 156578
* Add support for the 'X' inline asm operand modifier.Eric Christopher2012-05-102-4/+31
| | | | | | Patch by Jack Carter. llvm-svn: 156577
* misched: Print machineinstrs with -debug-only=mischedAndrew Trick2012-05-101-0/+2
| | | | llvm-svn: 156576
* misched: tracing register pressure heuristics.Andrew Trick2012-05-101-6/+22
| | | | llvm-svn: 156575
* misched: Add register pressure backoff to ConvergingScheduler.Andrew Trick2012-05-101-38/+144
| | | | | | | | | | | Prioritize the instruction that comes closest to keeping pressure under the target's limit. Then prioritize instructions that avoid increasing the max pressure in the scheduled region. The max pressure heuristic is a tad aggressive. Later I'll fix it to consider the unscheduled pressure as well. WIP: This is mostly functional but untested and not likely to do much good yet. llvm-svn: 156574
* misched: Release only unscheduled nodes into ReadyQ.Andrew Trick2012-05-101-2/+8
| | | | llvm-svn: 156573
* misched: Added ReadyQ container wrapper for Top and Bottom Queues.Andrew Trick2012-05-101-11/+44
| | | | llvm-svn: 156572
* misched: Introducing Top and Bottom register pressure trackers during ↵Andrew Trick2012-05-103-39/+112
| | | | | | scheduling. llvm-svn: 156571
* Updated LLVM/Clang to force the record layout engineSean Callanan2012-05-101-0/+19
| | | | | | | to complete C++ classes before traversing their base classes. llvm-svn: 156570
* Hexagon V5 Support - V5 td file.Sirish Pande2012-05-101-0/+626
| | | | llvm-svn: 156569
* Hexagon V5 FP Support.Sirish Pande2012-05-1029-194/+862
| | | | llvm-svn: 156568
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