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* [Statepoint] Clean up Statepoint.h: clang-format.Sanjoy Das2015-05-061-29/+14
| | | | llvm-svn: 236565
* [Statepoint] Clean up Statepoint.h: accessor names.Sanjoy Das2015-05-068-69/+73
| | | | | | Use getFoo() as accessors consistently and some other naming changes. llvm-svn: 236564
* [StatepointLowering] Don't create temporary instructions. NFCI.Sanjoy Das2015-05-063-75/+109
| | | | | | | | | | | | | | Summary: Instead of creating a temporary call instruction and lowering that, use SelectionDAGBuilder::lowerCallOperands. Reviewers: reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9480 llvm-svn: 236563
* Revert "[analyzer] scan-build: support spaces in compiler path and arguments."Ahmed Bougacha2015-05-061-5/+1
| | | | | | | | This reverts commit r236423 and its followup r236533, as indiscriminate quoting makes for too much quoting (and clang doesn't like both '"-c"' and -D"FOO=bar"). llvm-svn: 236562
* [WinEH] Reset WinEHPrepare::SEHExceptionCodeSlot when we're done.Ahmed Bougacha2015-05-061-0/+1
| | | | | | | This caused a use-after-free on test/CodeGen/X86/win32-eh.ll No functional change intended. llvm-svn: 236561
* Update gdbremote_testcase to accomodate new adb:// scheme.Chaoren Lin2015-05-061-1/+2
| | | | | | | | | | | | Reviewers: chying, ovyalov Reviewed By: chying, ovyalov Subscribers: lldb-commits Differential Revision: http://reviews.llvm.org/D9510 llvm-svn: 236560
* [asan] Fix dynamic-runtime tests.Evgeniy Stepanov2015-05-061-2/+3
| | | | | | | | | | They are not part of check-all :( This change adds sized-delete operators to the version list, and disables the hack that excluded versioned symbols from the dynamic list - this is not an issue in this case. llvm-svn: 236559
* InstrProf: Strip filename prefixes from the names we display for coverageJustin Bogner2015-05-052-1/+29
| | | | | | | For consumers of coverage data, any filename prefixes we store in the profile data are just noise. Strip this prefix if it exists. llvm-svn: 236558
* [X86 fast-isel] Constrain the index reg class to not include SP.Pete Cooper2015-05-052-6/+48
| | | | | | The index reg on instructions with complex address modes is a GPR64_NOSP. Constrain it to appease the machine verifier. llvm-svn: 236557
* [asan] Fix compiler-rt build.Evgeniy Stepanov2015-05-051-1/+4
| | | | | | i386 runtime library was accidentally using the x86_64 version script without a dependency. llvm-svn: 236556
* [SelectionDAG] Make an argument optional in RFV::getCopyToRegs. NFC.Sanjoy Das2015-05-051-5/+6
| | | | | | | | | | | | | | | Summary: We default the value argument to nullptr. The only use of the value is in diagnosePossiblyInvalidConstraint and that seems to be resilient to it being nullptr. Reviewers: atrick, reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9479 llvm-svn: 236555
* [SelectionDAG] Move RegsForValue into SelectionDAGBuilder.h. NFC.Sanjoy Das2015-05-052-85/+90
| | | | | | | | | | | | | | | Summary: The exported class will be used in later change, in StatepointLowering.cpp. It is still internal to SelectionDAG (not exported via include/). Reviewers: reames, atrick Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9478 llvm-svn: 236554
* [SelectionDAG] Pass explicit type to lowerCallOperands. NFC.Sanjoy Das2015-05-052-5/+6
| | | | | | | | | | | | | | Summary: Currently this does not change anything, but change will be used in a later change to StatepointLowering.cpp Reviewers: reames, atrick Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9477 llvm-svn: 236553
* [StatepointLowering] Rename variable, NFC.Sanjoy Das2015-05-051-3/+3
| | | | | | Rename LoweredArgs to LoweredMetaArgs to clarify intent. llvm-svn: 236552
* [asan] Use a version script to limit the symbols exported by the ASan shared ↵Evgeniy Stepanov2015-05-053-5/+55
| | | | | | runtime library. llvm-svn: 236551
* Fix IfConverter to handle regmask machine operands.Pete Cooper2015-05-052-1/+59
| | | | | | | | | | | | | | Note, this is a recommit of r236515 after fixing an error in r236514. The buildbot ran fast enough that it picked up r236514 prior to r236515 and threw an error. r236515 itself ran 'make check' without errors. Original commit message follows: A regmask (typically seen on a call) clobbers the set of registers it lists. The IfConverter, in UpdatePredRedefs, was handling register defs, but not regmasks. These are slightly different to a def in that we need to add both an implicit use and def to appease the machine verifier. Otherwise, uses after the if converted call could think they are reading an undefined register. Reviewed by Matthias Braun and Quentin Colombet. llvm-svn: 236550
* Mark TestMultithreaded.test_sb_api_listener_resume as XFAIL with gcc 4.8 and ↵Oleksiy Vyalov2015-05-051-1/+1
| | | | | | higher. llvm-svn: 236549
* [lib/Fuzzer] on crash print the contents of the crashy input as base64Kostya Serebryany2015-05-053-0/+8
| | | | llvm-svn: 236548
* InstrProf: Don't start or end coverage regions inside of system macrosJustin Bogner2015-05-052-4/+16
| | | | | | | | | | | It doesn't make much sense to try to show coverage inside system macros, and source locations in builtins confuses the coverage mapping. Just avoid doing this. Fixes an assert that fired when a __block storage specifier starts a region. llvm-svn: 236547
* propagate IR-level fast-math-flags to DAG nodes (NFC)Sanjay Patel2015-05-057-99/+109
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds the minimum plumbing necessary to use IR-level fast-math-flags (FMF) in the backend without actually using them for anything yet. This is a follow-on to: http://reviews.llvm.org/rL235997 ...which split the existing nsw / nuw / exact flags and FMF into their own struct. There are 2 structural changes here: 1. The main diff is that we're preparing to extend the optimization flags to affect more than just binary SDNodes. Eg, IR intrinsics ( https://llvm.org/bugs/show_bug.cgi?id=21290 ) or non-binop nodes that don't even exist in IR such as FMA, FNEG, etc. 2. The other change is that we're actually copying the FP fast-math-flags from the IR instructions to SDNodes. Differential Revision: http://reviews.llvm.org/D8900 llvm-svn: 236546
* [asan] fix IsDeadlySignalKostya Serebryany2015-05-051-2/+2
| | | | llvm-svn: 236545
* use range-based for-loop; NFCSanjay Patel2015-05-051-2/+2
| | | | llvm-svn: 236544
* Fix typo. platfrom -> platformChaoren Lin2015-05-052-5/+5
| | | | llvm-svn: 236543
* Update testcase to match r236539David Majnemer2015-05-051-1/+1
| | | | llvm-svn: 236542
* Make sure that the following paths say they are equal:Greg Clayton2015-05-051-0/+2
| | | | | | | | | | | /private/tmp/main.cpp /private/tmp/..//tmp/main.cpp We saw paths like this in makefile generate binaries when someone left an extra '/' on the end of a makefile variable. <rdar://problem/18945972> llvm-svn: 236541
* Added Andrey Churbanov as the owner of the OpenMP runtime library codeAndrey Churbanov2015-05-051-0/+4
| | | | llvm-svn: 236540
* [Inliner] Discard empty COMDAT groupsDavid Majnemer2015-05-052-11/+66
| | | | | | | | | COMDAT groups which have become rendered unused because of inline are discardable if we can prove that we've made the group empty. This fixes PR22285. llvm-svn: 236539
* Refactor UpdatePredRedefs and StepForward to avoid duplication. NFCPete Cooper2015-05-053-33/+36
| | | | | | | | | | Note, this is a reapplication of r236515 with a fix to not assert on non-register operands, but instead only handle them until the subsequent commit. Original commit message follows. The code was basically the same here already. Just added an out parameter for a vector of seen defs so that UpdatePredRedefs can call StepForward first, then do its own post processing on the seen defs. Will be used in the next commit to also handle regmasks. llvm-svn: 236538
* Build ASan runtime library with -z global on Android.Evgeniy Stepanov2015-05-053-2/+28
| | | | llvm-svn: 236537
* Thumb2SizeReduction: Check the correct set of registers for LDMIA.Peter Collingbourne2015-05-052-10/+5
| | | | | | | | | | | | | | | | | The register set for LDMIA begins at offset 3, not 4. We were previously missing the short encoding of this instruction in the case where the base register was the first register in the register set. Also clean up some dead code: - The isARMLowRegister check is redundant with what VerifyLowRegs does; replace with an assert. - Remove handling of LDMDB instruction, which has no short encoding (and does not appear in ReduceTable). Differential Revision: http://reviews.llvm.org/D9485 llvm-svn: 236535
* Integrate libiomp CMake into LLVM CMake build system.Andrey Churbanov2015-05-056-347/+333
| | | | | | | | | | | | | | | This patch integrates the libiomp CMake build system into the LLVM CMake build system so that users can checkout libiomp into the projects directory of llvm and build llvm,clang, and libiomp all together. These changes specifically introduce a new install target which will put libraries and headers into the correct locations when either a standalone build or part of llvm. The copy_recipe() method has been removed in favor of the POST_BUILD method to move headers into the exports subdirectory. And lastly, the MicroTests.cmake file was refactored which led to simpler target dependencies and a new target, make libiomp-micro-tests, which performs the 5 small tests (test-relo, test-touch, etc.) when called. llvm-svn: 236534
* [analyzer] This eliminates regression caused by r236423.Anton Yartsev2015-05-051-1/+5
| | | | | | Wrap an argument with quotes only if it has spaces. llvm-svn: 236533
* [SystemZ] Add support for z13 low-level vector builtinsUlrich Weigand2015-05-055-1/+1257
| | | | | | | | | | | | | | | | | | | | | | | | | This adds low-level builtins to allow access to all of the z13 vector instructions. Note that instructions whose semantics can be described by standard C (including clang extensions) do not get any builtins. For each instructions whose semantics *cannot* (fully) be described, we define a builtin named __builtin_s390_<insn> that directly maps to this instruction. These are intended to be compatible with GCC. For instructions that also set the condition code, the builtin will take an extra argument of type "int *" at the end. The integer pointed to by this argument will be set to the post-instruction CC value. For many instructions, the low-level builtin is mapped to the corresponding LLVM IR intrinsic. However, a number of instructions can be represented in standard LLVM IR without requiring use of a target intrinsic. Some instructions require immediate integer operands within a certain range. Those are verified at the Sema level. Based on a patch by Richard Sandiford. llvm-svn: 236532
* [SystemZ] Add support for z13 and its vector facilityUlrich Weigand2015-05-058-30/+476
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the z13 architecture type. For compatibility with GCC, a pair of options -mvx / -mno-vx can be used to selectively enable/disable use of the vector facility. When the vector facility is present, we default to the new vector ABI. This is characterized by two major differences: - Vector types are passed/returned in vector registers (except for unnamed arguments of a variable-argument list function). - Vector types are at most 8-byte aligned. The reason for the choice of 8-byte vector alignment is that the hardware is able to efficiently load vectors at 8-byte alignment, and the ABI only guarantees 8-byte alignment of the stack pointer, so requiring any higher alignment for vectors would require dynamic stack re-alignment code. However, for compatibility with old code that may use vector types, when *not* using the vector facility, the old alignment rules (vector types are naturally aligned) remain in use. These alignment rules are not only implemented at the C language level, but also at the LLVM IR level. This is done by selecting a different DataLayout string depending on whether the vector ABI is in effect or not. Based on a patch by Richard Sandiford. llvm-svn: 236531
* [DAGCombiner] Account for getVectorIdxTy() when narrowing vector loadUlrich Weigand2015-05-052-2/+18
| | | | | | | | | | | This patch makes ReplaceExtractVectorEltOfLoadWithNarrowedLoad convert the element number from getVectorIdxTy() to PtrTy before doing pointer arithmetic on it. This is needed on z, where element numbers are i32 but pointers are i64. Original patch by Richard Sandiford. llvm-svn: 236530
* [DAGCombiner] Fix ReplaceExtractVectorEltOfLoadWithNarrowedLoad for BEUlrich Weigand2015-05-052-7/+13
| | | | | | | | | | | | | For little-endian, the function would convert (extract_vector_elt (load X), Y) to X + Y*sizeof(elt). For big-endian it would instead use X + sizeof(vec) - Y*sizeof(elt). The big-endian case wasn't right since vector index order always follows memory/array order, even for big-endian. (Note that the current handling has to be wrong for Y==0 since it would access beyond the end of the vector.) Original patch by Richard Sandiford. llvm-svn: 236529
* [LegalizeVectorTypes] Allow single loads and stores for more short vectorsUlrich Weigand2015-05-056-5/+236
| | | | | | | | | | | | | | | | | | When lowering a load or store for TypeWidenVector, the type legalizer would use a single load or store if the associated integer type was legal. E.g. it would load a v4i8 as an i32 if i32 was legal. This patch extends that behavior to promoted integers as well as legal ones. If the integer type for the full vector width is TypePromoteInteger, the element type is going to be TypePromoteInteger too, and it's still better to use a single promoting load or truncating store rather than N individual promoting loads or truncating stores. E.g. if you have a v2i8 on a target where i16 is promoted to i32, it's better to load the v2i8 as an i16 rather than load both i8s individually. Original patch by Richard Sandiford. llvm-svn: 236528
* [SystemZ] Add vector intrinsicsUlrich Weigand2015-05-057-153/+4162
| | | | | | | | | | | | | | | | | | | This adds intrinsics to allow access to all of the z13 vector instructions. Note that instructions whose semantics can be described by standard LLVM IR do not get any intrinsics. For each instructions whose semantics *cannot* (fully) be described, we define an LLVM IR target-specific intrinsic that directly maps to this instruction. For instructions that also set the condition code, the LLVM IR intrinsic returns the post-instruction CC value as a second result. Instruction selection will attempt to detect code that compares that CC value against constants and use the condition code directly instead. Based on a patch by Richard Sandiford. llvm-svn: 236527
* [SystemZ] Mark v1i128 and v1f128 as unsupportedUlrich Weigand2015-05-059-0/+116
| | | | | | | | | | | | The ABI specifies that <1 x i128> and <1 x fp128> are supposed to be passed in vector registers. We do not yet support those types, and some infrastructure is missing before we can do so. In order to prevent accidentally generating code violating the ABI, this patch adds checks to detect those types and error out if user code attempts to use them. llvm-svn: 236526
* [SystemZ] Handle sub-128 vectorsUlrich Weigand2015-05-0520-29/+1175
| | | | | | | | | | | | | | | | | | | | | The ABI allows sub-128 vectors to be passed and returned in registers, with the vector occupying the upper part of a register. We therefore want to legalize those types by widening the vector rather than promoting the elements. The patch includes some simple tests for sub-128 vectors and also tests that we can recognize various pack sequences, some of which use sub-128 vectors as temporary results. One of these forms is based on the pack sequences generated by llvmpipe when no intrinsics are used. Signed unpacks are recognized as BUILD_VECTORs whose elements are individually sign-extended. Unsigned unpacks can have the equivalent form with zero extension, but they also occur as shuffles in which some elements are zero. Based on a patch by Richard Sandiford. llvm-svn: 236525
* [SystemZ] Add CodeGen support for scalar f64 ops in vector registersUlrich Weigand2015-05-0540-80/+1102
| | | | | | | | | | | | The z13 vector facility includes some instructions that operate only on the high f64 in a v2f64, effectively extending the FP register set from 16 to 32 registers. It's still better to use the old instructions if the operands happen to fit though, since the older instructions have a shorter encoding. Based on a patch by Richard Sandiford. llvm-svn: 236524
* [SystemZ] Add CodeGen support for v4f32Ulrich Weigand2015-05-0537-22/+1699
| | | | | | | | | | | | | | | | The architecture doesn't really have any native v4f32 operations except v4f32->v2f64 and v2f64->v4f32 conversions, with only half of the v4f32 elements being used. Even so, using vector registers for <4 x float> and scalarising individual operations is much better than generating completely scalar code, since there's much less register pressure. It's also more efficient to do v4f32 comparisons by extending to 2 v2f64s, comparing those, then packing the result. This particularly helps with llvmpipe. Based on a patch by Richard Sandiford. llvm-svn: 236523
* [SystemZ] Add CodeGen support for v2f64Ulrich Weigand2015-05-0540-39/+1723
| | | | | | | | | This adds ABI and CodeGen support for the v2f64 type, which is natively supported by z13 instructions. Based on a patch by Richard Sandiford. llvm-svn: 236522
* [SystemZ] Add CodeGen support for integer vector typesUlrich Weigand2015-05-0595-146/+10849
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This the first of a series of patches to add CodeGen support exploiting the instructions of the z13 vector facility. This patch adds support for the native integer vector types (v16i8, v8i16, v4i32, v2i64). When the vector facility is present, we default to the new vector ABI. This is characterized by two major differences: - Vector types are passed/returned in vector registers (except for unnamed arguments of a variable-argument list function). - Vector types are at most 8-byte aligned. The reason for the choice of 8-byte vector alignment is that the hardware is able to efficiently load vectors at 8-byte alignment, and the ABI only guarantees 8-byte alignment of the stack pointer, so requiring any higher alignment for vectors would require dynamic stack re-alignment code. However, for compatibility with old code that may use vector types, when *not* using the vector facility, the old alignment rules (vector types are naturally aligned) remain in use. These alignment rules are not only implemented at the C language level (implemented in clang), but also at the LLVM IR level. This is done by selecting a different DataLayout string depending on whether the vector ABI is in effect or not. Based on a patch by Richard Sandiford. llvm-svn: 236521
* [SystemZ] Add z13 vector facility and MC supportUlrich Weigand2015-05-0522-117/+13182
| | | | | | | | | | | | | | | | | | | | | This patch adds support for the z13 processor type and its vector facility, and adds MC support for all new instructions provided by that facilily. Apart from defining the new instructions, the main changes are: - Adding VR128, VR64 and VR32 register classes. - Making FP64 a subclass of VR64 and FP32 a subclass of VR32. - Adding a D(V,B) addressing mode for scatter/gather operations - Adding 1-, 2-, and 3-bit immediate operands for some 4-bit fields. Until now all immediate operands have been the same width as the underlying field (hence the assert->return change in decode[SU]ImmOperand). In addition, sys::getHostCPUName is extended to detect running natively on a z13 machine. Based on a patch by Richard Sandiford. llvm-svn: 236520
* Allow TransformTypos to ignore corrections to a specified VarDecl.Kaelyn Takata2015-05-055-12/+57
| | | | | | | | | | | | | This is needed to prevent a TypoExpr from being corrected to a variable when the TypoExpr is a subexpression of that variable's initializer. Also exclude more keywords from the correction candidate pool when the subsequent token is .* or ->* since keywords like "new" or "return" aren't valid on the left side of those operators. Fixes PR23140. llvm-svn: 236519
* Revert "Refactor UpdatePredRedefs and StepForward to avoid duplication. NFC"Pete Cooper2015-05-053-36/+33
| | | | | | | | This reverts commit 963cdbccf6e5578822836fd9b2ebece0ba9a60b7 (ie r236514) This is to get the bots green while i investigate. llvm-svn: 236518
* Revert "Fix IfConverter to handle regmask machine operands."Pete Cooper2015-05-052-59/+0
| | | | | | | | This reverts commit b27413cbfd78d959c18e713bfa271fb69e6b3303 (ie r236515). This is to get the bots green while i investigate the failures. llvm-svn: 236517
* Fix process launch from Windows host to Android target.Chaoren Lin2015-05-052-2/+3
| | | | | | | | | | | | | | | | Summary: - Denormalized path on Windows host causes bad `A` packet. - Executables copied from Windows host doesn't have executable bits. Reviewers: tberghammer, zturner, ovyalov Reviewed By: ovyalov Subscribers: tberghammer, lldb-commits Differential Revision: http://reviews.llvm.org/D9492 llvm-svn: 236516
* Fix IfConverter to handle regmask machine operands.Pete Cooper2015-05-052-0/+59
| | | | | | | | | | A regmask (typically seen on a call) clobbers the set of registers it lists. The IfConverter, in UpdatePredRedefs, was handling register defs, but not regmasks. These are slightly different to a def in that we need to add both an implicit use and def to appease the machine verifier. Otherwise, uses after the if converted call could think they are reading an undefined register. Reviewed by Matthias Braun and Quentin Colombet. llvm-svn: 236515
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