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* Extend the test coverage in combine-vec-shuffle-2.ll adding some negative tests.Andrea Di Biagio2014-07-101-0/+89
| | | | | | | | | Add test cases where we don't expect to trigger the combine optimizations introduced at revision 212748. No functional change intended. llvm-svn: 212756
* [doc] Fix incorrect reference to clang-format -> clang-tidyTobias Grosser2014-07-101-1/+1
| | | | llvm-svn: 212755
* Remove use of uniform initialization ({}) introduced in r212725 since this ↵David Blaikie2014-07-102-2/+2
| | | | | | isn't supported in MSVC. llvm-svn: 212754
* Avoid definining more GCC specific predefined macros in clang-clEhsan Akhgari2014-07-102-30/+47
| | | | | | | | | | Reviewers: hansw, rnk Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D4419 llvm-svn: 212753
* Quick (attempted) fix for non-asserts builds for a test introduced in r212743.David Blaikie2014-07-101-0/+1
| | | | llvm-svn: 212752
* [Driver/Unittests] Follow up for r212666, add unit test for the newly ↵Argyrios Kyrtzidis2014-07-102-0/+32
| | | | | | exposed getARMCPUForMArch() function. llvm-svn: 212751
* Revert "Revert r212640, "Add trunc (select c, a, b) -> select c (trunc a), ↵Matt Arsenault2014-07-104-2/+58
| | | | | | | | (trunc b) combine."" Don't try to convert the select condition type. llvm-svn: 212750
* [TSan] Fix a bug in libcxx-tsan build conditions spotted by Ryuta SuzukiAlexey Samsonov2014-07-102-2/+2
| | | | llvm-svn: 212749
* [DAG] Further improve the logic in DAGCombiner that folds a pair of shuffles ↵Andrea Di Biagio2014-07-103-15/+218
| | | | | | | | | | | | | | | | | | | | | into a single shuffle if the resulting mask is legal. This patch teaches the DAGCombiner how to fold shuffles according to the following new rules: 1. shuffle(shuffle(x, y), undef) -> x 2. shuffle(shuffle(x, y), undef) -> y 3. shuffle(shuffle(x, y), undef) -> shuffle(x, undef) 4. shuffle(shuffle(x, y), undef) -> shuffle(y, undef) The backend avoids to combine shuffles according to rules 3. and 4. if the resulting shuffle does not have a legal mask. This is to avoid introducing illegal shuffles that are potentially expanded into a sub-optimal sequence of target specific dag nodes during vector legalization. Added test case combine-vec-shuffle-2.ll to verify that we correctly triggers the new rules when combining shuffles. llvm-svn: 212748
* [X86] Mark pseudo instruction TEST8ri_NOEREX as hasSIdeEffects=0.Akira Hatanaka2014-07-103-2/+25
| | | | | | | | | Also, add a case clause in X86InstrInfo::shouldScheduleAdjacent to enable macro-fusion. <rdar://problem/15680770> llvm-svn: 212747
* Add the CSR company and the Kalimba DSP processor to Triple.Eric Christopher2014-07-102-2/+13
| | | | | | Patch by Matthew Gardiner with fixes by me. llvm-svn: 212745
* Make it possible for the Subtarget to change between functionEric Christopher2014-07-109-56/+57
| | | | | | | | passes in the mips back end. This, unfortunately, required a bit of churn in the various predicates to use a pointer rather than a reference. llvm-svn: 212744
* [PowerPC] ABI support for aligned by-value aggregatesUlrich Weigand2014-07-103-2/+187
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for respecting the ABI and type alignment of aggregates passed by value. Currently, all aggregates are aligned at 8 bytes in the parameter save area. This is incorrect for two reasons: - Aggregates that need alignment of 16 bytes or more should be aligned at 16 bytes in the parameter save area. This is implemented by using an appropriate "byval align" attribute in the IR. - Aggregates that need alignment beyond 16 bytes need to be dynamically realigned by the caller. This is implemented by setting the Realign flag of the ABIArgInfo::getIndirect call. In addition, when expanding a va_arg call accessing a type that is aligned at 16 bytes in the argument save area (either one of the aggregate types as above, or a vector type which is already aligned at 16 bytes), code needs to align the va_list pointer accordingly. Reviewed by Hal Finkel. llvm-svn: 212743
* InstCombine: Fix a crash in Descale for multiply-by-zeroDuncan P. N. Exon Smith2014-07-102-0/+27
| | | | | | | | | | Fix a crash in `InstCombiner::Descale()` when a multiply-by-zero gets created as an argument to a GEP partway through an iteration, causing -instcombine to optimize the GEP before the multiply. rdar://problem/17615671 llvm-svn: 212742
* Provide -verify support to match "any" line for diagnostics in included files.Andy Gibbs2014-07-105-23/+70
| | | | | | | | Allow diagnostic checks that originate in included files to be matched without necessarily determining the line number that the diagnostic occurs on. The new syntax replaces the line number with '*'. This extension is limited to diagnostics in included files and may be used where the include file is not part of the test-suite itself. Expected uses are for diagnostics originating in system headers, or for users who use -verify in testing 3rd-party library code where the location of diagnostics in header files may change from revision to revision and their precise location is not important to the success of the test-case. llvm-svn: 212735
* [PowerPC] ABI support for non-Altivec vector typesUlrich Weigand2014-07-102-1/+78
| | | | | | | | | | | | | | | | | | | | | This patch adds support for passing arguments of non-Altivec vector type (i.e. defined via attribute ((vector_size (...)))) on powerpc64-linux. While such types are not mentioned in the formal ABI document, this patch implements a calling convention compatible with GCC: - Vectors of size < 16 bytes are passed in a GPR - Vectors of size > 16 bytes are passed via reference Note that vector types with a number of elements that is not a power of 2 are not supported by GCC, so there is no pre-existing ABI to follow. We choose to pass those (of size < 16) as if widened to the next power of two, so they might end up in a vector register or in a GPR. (Sizes > 16 are always passed via reference as well.) Reviewed by Hal Finkel. llvm-svn: 212734
* Fix clang tests to be compliant with LLVM IR aliasesDavid Majnemer2014-07-102-3/+3
| | | | | | | | | | Comdat IR references were mistakenly printed for aliases when they passed through the IR/AsmWriter code. This makes clang's tests not check for the existance of these wrongly printed comdat references. llvm-svn: 212733
* IR: Aliases don't belong to an explicit comdatDavid Majnemer2014-07-102-5/+3
| | | | | | | | | Aliases inherit their comdat from their aliasee, they don't have an explicit comdat. This fixes PR20279. llvm-svn: 212732
* [analyzer] Check for code testing a variable for 0 after using it as a ↵Jordan Rose2014-07-105-2/+480
| | | | | | | | | | | | | | | | | | | denominator. This new checker, alpha.core.TestAfterDivZero, catches issues like this: int sum = ... int avg = sum / count; // potential division by zero... if (count == 0) { ... } // ...caught here Because the analyzer does not necessarily explore /all/ paths through a program, this check is restricted to only work on zero checks that immediately follow a division operation (/ % /= %=). This could later be expanded to handle checks dominated by a division operation but not necessarily in the same CFG block. Patch by Anders Rönnholm! (with very minor modifications by me) llvm-svn: 212731
* Feeding isSafeToSpeculativelyExecute its DataLayout pointer (in Sink)Hal Finkel2014-07-101-1/+5
| | | | | | | | | | This is the one remaining place I see where passing isSafeToSpeculativelyExecute a DataLayout pointer might matter (at least for loads) -- I think I got the others in r212720. Most of the other remaining callers of isSafeToSpeculativelyExecute only use it for call sites (or otherwise exclude loads). llvm-svn: 212730
* Mips: Silence a -Wcovered-switch-defaultDavid Majnemer2014-07-101-2/+2
| | | | | | | | | Remove a default label which covered no enumerators, replace it with a llvm_unreachable. No functionality changed. llvm-svn: 212729
* [Codestyle][x32] Cosmetic codestyle fix.Zinovy Nis2014-07-101-6/+6
| | | | llvm-svn: 212728
* Support the built-in type-trait support in gcc 4.7 and later. Thanks to ↵Marshall Clow2014-07-101-46/+42
| | | | | | Albert Wong for the patch. llvm-svn: 212727
* [mips] Added FPXX modeless calling convention.Zoran Jovanovic2014-07-107-1/+100
| | | | | | Differential Revision: http://reviews.llvm.org/D4293 llvm-svn: 212726
* [x32] Adding X32 target support to driver, including ↵Zinovy Nis2014-07-1021-28/+153
| | | | | | | | | | TargetInfo,DescriptionString, flags, paths lookup, etc. Cover changes with new tests. The author of the patch is Pavel Chupin (@pavel.v.chupin). The changes enable "hello world" on x32 target (x86_64-*-linux-gnux32). s/isX32/IsX32/ also fixed. Differential Revision: http://reviews.llvm.org/D4180 llvm-svn: 212725
* Add support for BIONIC C library (Android). Patch from Dan AlbertMarshall Clow2014-07-105-12/+217
| | | | llvm-svn: 212724
* Fix warning in test - missing exception specifier for overload of operator newMarshall Clow2014-07-101-1/+1
| | | | llvm-svn: 212723
* [AArch64] Add logical alias instructions to MC AsmParserArnaud A. de Grandmaison2014-07-105-17/+124
| | | | | | | | | | | | | | | | This patch teaches the AsmParser to accept some logical+immediate instructions and convert them as shown: bic Rd, Rn, #imm -> and Rd, Rn, #~imm bics Rd, Rn, #imm -> ands Rd, Rn, #~imm orn Rd, Rn, #imm -> orr Rd, Rn, #~imm eon Rd, Rn, #imm -> eor Rd, Rn, #~imm Those instructions are an alternate syntax available to assembly coders, and are needed in order to support code already compiling with some other assemblers. For example, the bic construct is used by the linux kernel. llvm-svn: 212722
* Reapply typo fix.Bruce Mitchener2014-07-101-1/+1
| | | | | | This was lost in the re-merging of command validation changes. llvm-svn: 212721
* Feeding isSafeToSpeculativelyExecute its DataLayout pointerHal Finkel2014-07-107-36/+52
| | | | | | | | | | | | | | isSafeToSpeculativelyExecute can optionally take a DataLayout pointer. In the past, this was mainly used to make better decisions regarding divisions known not to trap, and so was not all that important for users concerned with "cheap" instructions. However, now it also helps look through bitcasts for dereferencable loads, and will also be important if/when we add a dereferencable pointer attribute. This is some initial work to feed a DataLayout pointer through to callers of isSafeToSpeculativelyExecute, generally where one was already available. llvm-svn: 212720
* [mips][mips64r6] Add support for mips-img-linux-gnu GCC toolchainsDaniel Sanders2014-07-1057-13/+225
| | | | | | | | | | | | | | Summary: * Support the multilib layout used by the mips-img-linux-gnu * Recognize mips{,64}{,el}-img-linux-gnu as being aliases of mips-img-linux-gnu * Use the correct dynamic linker for mips-img-linux-gnu * Make mips32r6/mips64r6 the default CPU for mips-img-linux-gnu Subscribers: mpf Differential Revision: http://reviews.llvm.org/D4436 llvm-svn: 212719
* AArch64: correctly fast-isel i8 & i16 multipliesTim Northover2014-07-102-0/+41
| | | | | | | | We were asking for a register for type i8 or i16 which caused an assert. rdar://problem/17620015 llvm-svn: 212718
* [mips] Add support for -modd-spreg/-mno-odd-spregDaniel Sanders2014-07-1016-98/+462
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When -mno-odd-spreg is in effect, 32-bit floating point values are not permitted in odd FPU registers. The option also prohibits 32-bit and 64-bit floating point comparison results from being written to odd registers. This option has three purposes: * It allows support for certain MIPS implementations such as loongson-3a that do not allow the use of odd registers for single precision arithmetic. * When using -mfpxx, -mno-odd-spreg is the default and this allows us to statically check that code is compliant with the O32 FPXX ABI since mtc1/mfc1 instructions to/from odd registers are guaranteed not to appear for any reason. Once this has been established, the user can then re-enable -modd-spreg to regain the use of all 32 single-precision registers. * When using -mfp64 and -mno-odd-spreg together, an O32 extension named O32 FP64A is used as the ABI. This is intended to provide almost all functionality of an FR=1 processor but can also be executed on a FR=0 core with the assistance of a hardware compatibility mode which emulates FR=0 behaviour on an FR=1 processor. * Added '.module oddspreg' and '.module nooddspreg' each of which update the .MIPS.abiflags section appropriately * Moved setFpABI() call inside emitDirectiveModuleFP() so that the caller doesn't have to remember to do it. * MipsABIFlags now calculates the flags1 and flags2 member on demand rather than trying to maintain them in the same format they will be emitted in. There is one portion of the -mfp64 and -mno-odd-spreg combination that is not implemented yet. Moves to/from odd-numbered double-precision registers must not use mtc1. I will fix this in a follow-up. Differential Revision: http://reviews.llvm.org/D4383 llvm-svn: 212717
* [x32] Add AsmBackend for X32 which uses ELF32 with x86_64 (the author is ↵Zinovy Nis2014-07-101-0/+14
| | | | | | | | | | Pavel Chupin). This is minimal change for backend required to have "hello world" compiled and working on x32 target (x86_64-linux-gnux32). More patches for x32 will follow. Differential Revision: http://reviews.llvm.org/D4181 llvm-svn: 212716
* [msan] Fix performance issue in fast_memset.Evgeniy Stepanov2014-07-101-5/+6
| | | | | | Fast path was never triggered when called from __msan_poison. llvm-svn: 212715
* [x86,SDAG] Introduce any- and sign-extend-vector-inreg nodes analogousChandler Carruth2014-07-109-9/+165
| | | | | | | | | | | | | | | | | | | | to the zero-extend-vector-inreg node introduced previously for the same purpose: manage the type legalization of widened extend operations, especially to support the experimental widening mode for x86. I'm adding both because sign-extend is expanded in terms of any-extend with shifts to propagate the sign bit. This removes the last fundamental scalarization from vec_cast2.ll (a test case that hit many really bad edge cases for widening legalization), although the trunc tests in that file still appear scalarized because the the shuffle legalization is scalarizing. Funny thing, I've been working on that. Some initial experiments with this and SSE2 scenarios is showing moderately good behavior already for sign extension. Still some work to do on the shuffle combining on X86 before we're generating optimal sequences, but avoiding scalarization is a huge step forward. llvm-svn: 212714
* [mach-o]: support -Z option to skip standard library pathsTim Northover2014-07-103-2/+28
| | | | llvm-svn: 212713
* [mach-o]: support user-specified (-L) library search pathsTim Northover2014-07-105-5/+45
| | | | llvm-svn: 212712
* [SystemZ] Use SystemZCallingConv.td to define callee-saved registersRichard Sandiford2014-07-105-16/+23
| | | | | | Just a clean-up. No behavioral change intended. llvm-svn: 212711
* SpecialCaseList.h: Fix -Wdocumentation with \code.NAKAMURA Takumi2014-07-101-0/+2
| | | | llvm-svn: 212710
* llvm/test/CodeGen/X86/shift-parts.ll: FileCheck-ize. (from r212640)NAKAMURA Takumi2014-07-101-1/+3
| | | | llvm-svn: 212709
* Revert r212640, "Add trunc (select c, a, b) -> select c (trunc a), (trunc b) ↵NAKAMURA Takumi2014-07-103-54/+3
| | | | | | | | combine." This caused miscompilation on, at least, x86-64. SExt(i1 cond) confused other optimizations. llvm-svn: 212708
* [SystemZ] Tweak instruction format classificationsRichard Sandiford2014-07-102-53/+43
| | | | | | | | | | There's no real need to have Shift as a separate format type from Binary. The comments for other format types were too specific and in some cases no longer accurate. Just a clean-up, no behavioral change intended. llvm-svn: 212707
* [mach-o]: support -syslibroot and -l optionsTim Northover2014-07-1012-4/+288
| | | | | | | | | | | | | | | | | | | | | | | | | | These behave slightly idiosyncratically in the best of cases, and have additional hacks layered on top of that for compatibility with badly behaved build systems (via ld64). For -lXYZ: + If XYZ is actually XY.o then search all library paths for XY.o + Otherwise search all library paths, first for libXYZ.dylib, then libXYZ.a + By default the library paths are /usr/lib and /usr/local/lib in that order. For -syslibroot: + -syslibroot options apply to absolute paths in the search order. + All -syslibroot prefixes that exist are added to the search path *instead* of the original. + If no -syslibroot prefixed path exists, the original is kept. + Hacks^WExceptions: + If only 1 -syslibroot is given and doesn't contain /usr/lib or /usr/local/lib, that path is dropped entirely. (rdar://problem/6438270). + If the last -syslibroot is "/", all of them are ignored entirely. (rdar://problem/5829579). At least, that's my best interpretation of what ld64 does in buildSearchPaths. llvm-svn: 212706
* [x86] Add another combine that is particularly useful for the new vectorChandler Carruth2014-07-102-3/+52
| | | | | | | | | | shuffle lowering: match shuffle patterns equivalent to an unpcklwd or unpckhwd instruction. This allows us to use generic lowering code for v8i16 shuffles and match the unpack pattern late. llvm-svn: 212705
* [msan] Switch chained origins hash to murmur2.Evgeniy Stepanov2014-07-101-1/+24
| | | | llvm-svn: 212704
* [SystemZ] Add MC support for LEDBRA, LEXBRA and LDXBRARichard Sandiford2014-07-105-0/+172
| | | | | | | These instructions aren't used for codegen since the original L*DB instructions are suitable for fround. llvm-svn: 212703
* [SystemZ] Avoid using i8 constants for immediate fieldsRichard Sandiford2014-07-105-58/+54
| | | | | | | | | | | | Immediate fields that have no natural MVT type tended to use i8 if the field was small enough. This was a bit confusing since i8 isn't a legal type for the target. Fields for short immediates in a 32-bit or 64-bit operation use i32 or i64 instead, so it would be better to do the same for all fields. No behavioral change intended. llvm-svn: 212702
* [SystemZ] Fix FPR dwarf numberingRichard Sandiford2014-07-102-14/+62
| | | | | | | | The dwarf FPR numbers are supposed to have the order F0, F2, F4, F6, F1, F3, F5, F7, F8, etc., which matches the pairing of registers for long doubles. E.g. a long double stored in F0 is paired with F2. llvm-svn: 212701
* [mips] Add support for -modd-spreg/-mno-odd-spregDaniel Sanders2014-07-103-0/+18
| | | | | | Differential Revision: http://reviews.llvm.org/D4432 llvm-svn: 212700
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