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* [ARM] push LR before __gnu_mcount_ncJian Cai2019-08-169-2/+138
| | | | | | | | | Push LR register before calling __gnu_mcount_nc as it expects the value of LR register to be the top value of the stack on ARM32. Differential Revision: https://reviews.llvm.org/D65019 llvm-svn: 369147
* [OPENMP5.0]Diagnose global variables in lambda not marked as declareAlexey Bataev2019-08-163-9/+36
| | | | | | | | target. According to OpenMP 5.0, if a lambda declaration and definition appears between a declare target directive and the matching end declare target directive, all variables that are captured by the lambda expression must also appear in a to clause. llvm-svn: 369146
* Stop abusing SuppressAllDiagnostics when speculatively determiningRichard Smith2019-08-163-17/+15
| | | | | | whether an expression would be valid during error recovery. llvm-svn: 369145
* [Attributor] Towards a more structured deduction patternJohannes Doerfert2019-08-163-118/+257
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is the first commit aiming to structure the attribute deduction. The base idea is that we have default propagation patterns as listed below on top of which we can add specific, e.g., context sensitive, logic. Deduction patterns used in this patch: - argument states are determined from call site argument states, see AAAlignArgument and AAArgumentFromCallSiteArguments. - call site argument states are determined as if they were floating values, see AAAlignCallSiteArgument and AAAlignFloating. - floating value states are determined by traversing the def-use chain and combining the states determined for the leaves, see AAAlignFloating and genericValueTraversal. - call site return states are determined from function return states, see AAAlignCallSiteReturned and AACallSiteReturnedFromReturned. - function return states are determined from returned value states, see AAAlignReturned and AAReturnedFromReturnedValues. Through this strategy all logic for alignment is concentrated in the AAAlignFloating::updateImpl method. Note: This commit works on its own but is part of a larger change that involves "on-demand" creation of abstract attributes that will participate in the fixpoint iteration. Without this part, we sometimes do not have an AAAlign abstract attribute to query, loosing information we determined before. All tests have appropriate FIXMEs and the information will be recovered once we added all parts. Reviewers: sstefan1, uenoku Subscribers: hiraditya, bollu, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66126 llvm-svn: 369144
* [Attributor][NFC] Introduce aliases for call site attributesJohannes Doerfert2019-08-161-7/+40
| | | | | | | | | Until we have call site specific liveness and/or value information there is no need to do call site specific deduction. Though, we need the symbols in follow up patches that make Attributor::getAAFor return a reference. llvm-svn: 369143
* [Attributor] Introduce initialize calls and move code to keep attributes conciseJohannes Doerfert2019-08-161-179/+180
| | | | | | | | | | | | | | | | | | Summary: This patch should not change the behavior except that the added initialize methods might indicate an optimistic fixpoint earlier. The code movement is done to keep the attribute definitions in a single block where it makes sense. No functional changes intended there. Reviewers: uenoku, sstefan1 Subscribers: hiraditya, bollu, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66258 llvm-svn: 369142
* [ORC] Remove some stray debugging output accidentally left in r368707Lang Hames2019-08-161-2/+0
| | | | llvm-svn: 369141
* [InstCombine] canonicalize a scalar-select-of-vectors to vector selectSanjay Patel2019-08-162-4/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This pattern may arise more frequently with an enhancement to SLP vectorization suggested in PR42755: https://bugs.llvm.org/show_bug.cgi?id=42755 ...but we should handle this pattern to make things easier for the backend either way. For all in-tree targets that I looked at, codegen for typical vector sizes looks better when we change to a vector select, so this is safe to do without a cost model (in other words, as a target-independent canonicalization). For example, if the condition of the select is a scalar, we end up with something like this on x86: vpcmpgtd %xmm0, %xmm1, %xmm0 vpextrb $12, %xmm0, %eax testb $1, %al jne LBB0_2 ## %bb.1: vmovaps %xmm3, %xmm2 LBB0_2: vmovaps %xmm2, %xmm0 Rather than the splat-condition variant: vpcmpgtd %xmm0, %xmm1, %xmm0 vpshufd $255, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3] vblendvps %xmm0, %xmm2, %xmm3, %xmm0 Differential Revision: https://reviews.llvm.org/D66095 llvm-svn: 369140
* [clang-doc] Redesign of generated HTML filesDiego Astiazaran2019-08-168-339/+1272
| | | | | | | | | | | | | The new design includes a header (contains the project name), a main section, and a footer. The main section is divided into three subsections. Left, middle, right. The left section contains the general index, the middle contains the info's data, and the right contains the index for the info's content. The CSS has been updated. A flag --project-name is added. The Attributes attribute of the TagNode struct is now a vector of pairs because these attributes should be rendered in the insertion order. The functions (cpp and js) that converts an Index tree structure into HTML were slightly modified; the first ul tag created is now a ol tag. The inner lists are still ul. Differential Revision: https://reviews.llvm.org/D66353 llvm-svn: 369139
* Escape % in printf format string.Evgeniy Stepanov2019-08-161-1/+1
| | | | | | Fixes branch-relax-block-size.mir on the ASan builder. llvm-svn: 369138
* [WebAssembly] Forbid use of EM_ASM with setjmp/longjmpGuanzhong Chen2019-08-161-0/+24
| | | | | | | | | | | | | | | | | | | | | | | Summary: We tried to support EM_ASM with setjmp/longjmp in binaryen. But with dynamic linking thrown into the mix, the code is no longer understandable and cannot be maintained. We also discovered more bugs in the EM_ASM handling code. To ensure maintainability and correctness of the binaryen code, EM_ASM will no longer be supported with setjmp/longjmp. This is probably fine since the support was added recently and haven't be published. Reviewers: tlively, sbc100, jgravelle-google, kripken Reviewed By: tlively, kripken Subscribers: dschuff, hiraditya, aheejin, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66356 llvm-svn: 369137
* [X86] resolveTargetShuffleInputs - add DemandedElts variant. NFCI.Simon Pilgrim2019-08-161-3/+10
| | | | | | Nothing calls this yet, everything still goes through the non (all) DemandedElts wrapper. llvm-svn: 369136
* [AArch64][GlobalISel] Lower G_SHUFFLE_VECTOR with 1 elt src and 1 elt mask.Amara Emerson2019-08-162-1/+43
| | | | | | | | Again, it's weird that these are allowed. Since lowering support was added in r368709 we started crashing on compiling the neon intrinsics test in the test suite. This fixes the lowering to fold the 1 elt src/mask case into copies. llvm-svn: 369135
* [X86] combineExtractWithShuffle - handle extract(truncate(x), 0)Simon Pilgrim2019-08-162-15/+15
| | | | | | Eventually we need to generalize combineExtractWithShuffle to handle all faux shuffles and handle truncate (and X86ISD::VTRUNC etc.) there, but we're not ready yet (still creates nodes on the fly, incomplete DemandedElts support, bad use of recursive Depth limit). llvm-svn: 369134
* [AArch64InstrInfo] Stop getInstSizeInBytes returning non-zero for meta ↵Paul Walker2019-08-162-6/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instructions. Recommit with fixes for mac builders. Summary: AArch64InstrInfo::getInstSizeInBytes is incorrectly treating meta instructions (e.g. CFI_INSTRUCTION) as normal instructions and giving them a size of 4. This results in branch relaxation calculating block sizes wrong. Branch relaxation also considers alignment and thus a single mistake can result in later blocks being incorrectly sized even when they themselves do not contain meta instructions. The net result is we might not relax a branch whose destination is not within range. Reviewers: nickdesaulniers, peter.smith Reviewed By: peter.smith Subscribers: javed.absar, kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66337 > llvm-svn: 369111 llvm-svn: 369133
* Revert [AArch64InstrInfo] Stop getInstSizeInBytes returning non-zero for ↵Paul Walker2019-08-162-84/+6
| | | | | | | | meta instructions. This reverts r369111 (git commit 3ccee5f7c4087ed119dbeba537f3df1b048a4dff) llvm-svn: 369132
* [SLPVectorizer] Make the scheduler aware of the TreeEntry operands.Vasileios Porpodas2019-08-161-79/+171
| | | | | | | | | | | | | | | | | | | | | | Summary: The scheduler's dependence graph gets the use-def dependencies by accessing the operands of the instructions in a bundle. However, buildTree_rec() may change the order of the operands in TreeEntry, and the scheduler is currently not aware of this. This is not causing any functional issues currently, because reordering is restricted to the operands of a single instruction. Once we support operand reordering across multiple TreeEntries, as shown here: http://www.llvm.org/devmtg/2019-04/slides/Poster-Porpodas-Supernode_SLP.pdf , the scheduler will need to get the correct operands from TreeEntry and not from the individual instructions. In short, this patch: - Connects the scheduler's bundle with the corresponding TreeEntry. It introduces new TE and Lane fields in ScheduleData. - Moves the location where the operands of the TreeEntry are initialized. This used to take place in newTreeEntry() setting one operand at a time, but is now moved pre-order just before the recursion of buildTree_rec(). This is required because the scheduler needs to access both operands of the TreeEntry in tryScheduleBundle(). - Updates the scheduler to access the instruction operands through the TreeEntry operands instead of accessing the instruction operands directly. Reviewers: ABataev, RKSimon, dtemirbulatov, Ayal, dorit, hfinkel Reviewed By: ABataev Subscribers: hiraditya, llvm-commits, lebedev.ri, rcorcs Tags: #llvm Differential Revision: https://reviews.llvm.org/D62432 llvm-svn: 369131
* [ADT] Remove llvm::make_unique utility.Jonas Devlieghere2019-08-162-36/+1
| | | | | | | | | | All uses of llvm::make_unique should have been replaced with std::make_unique. This patch represents the last part of the migration and removes the utility from LLVM. Differential revision: https://reviews.llvm.org/D66259 llvm-svn: 369130
* Fix llvm-config support for CMake build-mode-style buildsJordan Rose2019-08-161-5/+8
| | | | | | | | | | | | At some point we and/or CMake changed our build-mode-style builds from $LLVM_OBJ_ROOT/bin/$CMAKE_CFG_INTDIR/ to $LLVM_OBJ_ROOT/$CMAKE_CFG_INTDIR/bin/ which is way easier to use. But no one updated llvm-config. https://reviews.llvm.org/D66326 llvm-svn: 369129
* [ELF][Hexagon] Replace R_HEXAGON_GOT with R_GOTPLTFangrui Song2019-08-164-8/+5
| | | | | | | | | | | R_GOTPLT is relative to .got.plt since D59594. Since R_HEXAGON_GOT relocations always have 0 r_addend, they can use R_GOTPLT instead. Reviewed By: sidneym Differential Revision: https://reviews.llvm.org/D66274 llvm-svn: 369128
* [SLP] add tests for PR16739; NFCSanjay Patel2019-08-161-0/+68
| | | | llvm-svn: 369127
* [X86] Alphabetize pass initialization definitions. NFCI.Simon Pilgrim2019-08-161-1/+1
| | | | llvm-svn: 369126
* [CodeGen/Analysis] Intrinsic llvm.assume should not block tail call optimizationGuozhi Wei2019-08-162-2/+19
| | | | | | | | In function Analysis.cpp:isInTailCallPosition, instructions between call and ret are checked to see if they block tail call optimization. If an instruction is an intrinsic call, only llvm.lifetime_end is allowed and other intrinsic functions block tail call. When compiling tcmalloc, we found llvm.assume between a hot function call and ret, it blocks the optimization. But llvm.assume doesn't generate instructions, it should not block tail call. Differential Revision: https://reviews.llvm.org/D66096 llvm-svn: 369125
* [Hexagon] Generate min/max instructions for 64-bit vectorsKrzysztof Parzyszek2019-08-166-50/+338
| | | | llvm-svn: 369124
* [clang-doc] Fix records in global namespaceDiego Astiazaran2019-08-163-42/+102
| | | | | | | | | | | | | When a Record is declared in the global namespace, clang-doc serializes it as a child of the global namespace, so the global namespace is now one if its parent namespaces. This namespace was not being included in the list of namespaces of the Info causing paths to be incorrect and the index rendered incorrectly. Affected tests have been fixed. Differential revision: https://reviews.llvm.org/D66298 llvm-svn: 369123
* Relanding r368987 [AArch64] Change location of frame-record within ↵Sander de Smalen2019-08-1632-291/+347
| | | | | | | | | | | | | | | | callee-save area. Changes: There was a condition for `!NeedsFrameRecord` missing in the assert. The assert in question has changed to: + assert((!RPI.isPaired() || !NeedsFrameRecord || RPI.Reg2 != AArch64::FP || + RPI.Reg1 == AArch64::LR) && + "FrameRecord must be allocated together with LR"); This addresses PR43016. llvm-svn: 369122
* [lld][Hexagon]Support HEX_32 when building shared objectsSid Manning2019-08-162-3/+29
| | | | | | Differential Revision: https://reviews.llvm.org/D66105 llvm-svn: 369121
* [InstCombine] Simplify pow(2.0, itofp(y)) to ldexp(1.0, y)Evandro Menezes2019-08-162-22/+95
| | | | | | | | Simplify `pow(2.0, itofp(y))` to `ldexp(1.0, y)`. Differential revision: https://reviews.llvm.org/D65979 llvm-svn: 369120
* [TextAPI] Update reader to be supported by lib/ObjectCyndy Ishida2019-08-165-122/+104
| | | | | | | | | | | | | | | | | | | Summary: To be able to use the TextAPI/Reader for tbd file consumption (by libObject) it gets passed a MemoryBufferRef which isn't castable to MemoryBuffer. Updated the tests to expect that input as well. Reviewers: ributzka, steven_wu Reviewed By: steven_wu Subscribers: hiraditya, dexonsmith, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66147 llvm-svn: 369119
* [ARM] MVE sext of a load is freeDavid Green2019-08-162-6/+21
| | | | | | | | | MVE also has some sext of loads, which will be free just as scalar instructions are. Differential Revision: https://reviews.llvm.org/D66008 llvm-svn: 369118
* [InstCombine] Shift amount reassociation in bittest: trunc-of-shl (PR42399)Roman Lebedev2019-08-163-65/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is continuation of D63829 / https://bugs.llvm.org/show_bug.cgi?id=42399 I thought naive pattern would solve my issue, but nope, it involved truncation, thus more folds needed.. This isn't really the fold i'm interested in, i need trunc-of-lshr, but i'we decided to start with `shl` because it's simpler. In this case, no extra legality checks are needed: https://rise4fun.com/Alive/CAb We should be careful about not increasing instruction count, since we need to produce `zext` because `and` is done in wider type. Reviewers: spatel, nikic, xbolva00 Reviewed By: spatel Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66057 llvm-svn: 369117
* [X86][SSE] Add shuffled load tests from PR16739Simon Pilgrim2019-08-161-0/+162
| | | | llvm-svn: 369116
* Revert rL369112 : [X86][SSE] Add shuffled load tests from PR16739Simon Pilgrim2019-08-161-212/+0
| | | | | | I left typos in this from a WIP copy - reverting and I'll recommit. llvm-svn: 369115
* [RISCV] Convert registers from unsigned to RegisterLuis Marques2019-08-1611-78/+82
| | | | | | | | | Only in public interfaces that have not yet been converted should there remain registers with unsigned type. Differential Revision: https://reviews.llvm.org/D66252 llvm-svn: 369114
* [lldb][NFC] Allow for-ranges on StringListRaphael Isemann2019-08-1611-32/+48
| | | | llvm-svn: 369113
* [X86][SSE] Add shuffled load tests from PR16739Simon Pilgrim2019-08-161-0/+212
| | | | llvm-svn: 369112
* [AArch64InstrInfo] Stop getInstSizeInBytes returning non-zero for meta ↵Paul Walker2019-08-162-6/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | instructions. Summary: AArch64InstrInfo::getInstSizeInBytes is incorrectly treating meta instructions (e.g. CFI_INSTRUCTION) as normal instructions and giving them a size of 4. This results in branch relaxation calculating block sizes wrong. Branch relaxation also considers alignment and thus a single mistake can result in later blocks being incorrectly sized even when they themselves do not contain meta instructions. The net result is we might not relax a branch whose destination is not within range. Reviewers: nickdesaulniers, peter.smith Reviewed By: peter.smith Subscribers: javed.absar, kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66337 llvm-svn: 369111
* [X86] Remove unused include. NFCI.Simon Pilgrim2019-08-161-1/+0
| | | | | | We don't use anything from TargetOptions.h directly and its included via TargetLowering.h anyhow. llvm-svn: 369110
* [libcxxabi] __cxa_guard_require: test guard byte with != 0 instead of == 1Fangrui Song2019-08-161-1/+1
| | | | llvm-svn: 369109
* [ARM] Correct register for narrowing and widening MVE loads and stores.David Green2019-08-164-13/+323
| | | | | | | | | | | | | | | | The widening and narrowing MVE instructions like VLDRH.32 are only permitted to use low tGPR registers. This means that if they are used for a stack slot, where the register used is only decided during frame setup, we need to be able to correctly pick a thumb1 register over a normal GPR. This attempts to add the required logic into eliminateFrameIndex and rewriteT2FrameIndex, only picking the FrameReg if it is a valid register for the operands register class, and picking a valid scratch register for the register class. Differential Revision: https://reviews.llvm.org/D66285 llvm-svn: 369108
* [x86] fix fdiv test; NFCSanjay Patel2019-08-161-39/+47
| | | | | | | The test was just added with rL369106, but forgot to update the instruction along with the test name. llvm-svn: 369107
* [x86] add tests for fdiv with variable operands; NFCSanjay Patel2019-08-161-0/+184
| | | | | | | D66050 proposes to change the estimate sequence, but we don't seem to have test coverage for the common case. llvm-svn: 369106
* [clangd] suppress -Wparentheses warning: suggest parentheses around ‘&&’ ↵Haojian Wu2019-08-161-1/+1
| | | | | | within ‘||’ llvm-svn: 369105
* Revert [CodeGen] Do the Simple Early Return in block-placement pass to ↵Florian Hahn2019-08-162-41/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | optimize the blocks This reverts r368997 (git commit 2a903c0b679bae1919f9fc01f78e4bc6cff2add0) It looks like this commit adds invalid predecessors to MBBs. The example below fails the verifier after MachineBlockPlacement (run llc -verify-machineinstrs): @global.4 = external constant i8* declare i32 @zot(...) define i16* @snork.67() personality i8* bitcast (i32 (...)* @zot to i8*) { bb: invoke void undef() to label %bb5 unwind label %bb4 bb4: ; preds = %bb %tmp = landingpad { i8*, i32 } catch i8* null unreachable bb5: ; preds = %bb %tmp6 = load i32, i32* null, align 4 %tmp7 = icmp eq i32 %tmp6, 0 br i1 %tmp7, label %bb14, label %bb8 bb8: ; preds = %bb11, %bb5 invoke void undef() to label %bb9 unwind label %bb11 bb9: ; preds = %bb8 %tmp10 = invoke i16* undef() to label %bb14 unwind label %bb11 bb11: ; preds = %bb9, %bb8 %tmp12 = landingpad { i8*, i32 } cleanup catch i8* bitcast (i8** @global.4 to i8*) %tmp13 = icmp ult i64 undef, undef br i1 %tmp13, label %bb8, label %bb14 bb14: ; preds = %bb11, %bb9, %bb5 %tmp15 = phi i16* [ null, %bb5 ], [ null, %bb11 ], [ %tmp10, %bb9 ] ret i16* %tmp15 } llvm-svn: 369104
* [DAGCombiner] Add simple folds for SMULFIX/UMULFIX/SMULFIXSATBjorn Pettersson2019-08-163-156/+81
| | | | | | | | | | | | | | | | | | | | | | Summary: Add the following DAGCombiner folds for mulfix being one of SMULFIX/UMULFIX/SMULFIXSAT: (mulfix x, undef, scale) -> 0 (mulfix x, 0, scale) -> 0 Also added canonicalization of constants to RHS. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66052 llvm-svn: 369103
* [X86] Add test case for future MULFIX DAG combine folds. NFCBjorn Pettersson2019-08-161-0/+206
| | | | | | | | | | | | | | | | | | | | Add some test cases displaying the lack of DAG combine folds for SMULFIX/UMULFIX/SMULFIXSAT when either multiplicand is undef or zero. It seems like widening vector legalization for X86 can introduce fixed point multiplication of undef values. So that is one way that such operations could appear during ISel. Multiplication with zero is probably more unlikely, and could potentially be handled by InstCombine. But I do not think it would hurt to do such folds in DAGCombiner. This patch only adds the test case. The folds will be added in a follow up patch. llvm-svn: 369102
* [ARM] Don't pretend we know how to generate MVE VLDnDavid Green2019-08-163-1/+423
| | | | | | | | | | We don't yet know how to generate these instructions for MVE. And in the case of VLD3, we don't even have the instruction. For the moment don't tell the vectoriser that we have VLD4, just to end up serialising the results. Differential Revision: https://reviews.llvm.org/D66009 llvm-svn: 369101
* [clangd] Simplify code of ClangdLSPServer::onCommandIlya Biryukov2019-08-161-41/+33
| | | | | | | | | | | | | | | | | | | | Summary: By inlining a complicated lambda into its single call-site. Also ensure we call Reply() exactly once even if tweaks return both ShowMessage and ApplyEdit effects. Reviewers: hokein Reviewed By: hokein Subscribers: MaskRay, jkorous, arphaman, kadircet, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D66343 llvm-svn: 369100
* Fix typos in LibASTImporter.rstGabor Marton2019-08-161-2/+2
| | | | llvm-svn: 369099
* [ASTImporter] Import ctor initializers after setting flags.Balazs Keri2019-08-164-17/+33
| | | | | | | | | | | | | | | | | | | | Summary: Code to import "ctor initializers" at import of functions is moved to be after the flags in the newly created function are imported. This fixes an error when the already created but incomplete (flags are not set) function declaration is accessed. Reviewers: martong, shafik, a_sidorin, a.sidorin Reviewed By: shafik Subscribers: rnkovacs, dkrupp, Szelethus, gamesh411, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D65935 llvm-svn: 369098
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