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* [SLP] Use different flags in tests for reduction ops and extra args.Alexey Bataev2017-02-271-3/+3
| | | | llvm-svn: 296376
* AMDGPU: Don't fold immediate if clamp/omod are setMatt Arsenault2017-02-273-8/+319
| | | | | | | Doesn't fix any practical problems because clamp/omod are currently folded after peephole optimizer. llvm-svn: 296375
* [ubsan] Factor out logic to emit a range check. NFC.Vedant Kumar2017-02-272-29/+50
| | | | | | | This is a readability improvement, but it will also help prep an upcoming patch to detect UB loads from bitfields. llvm-svn: 296374
* enable -flto=thin in clang-clBob Haarman2017-02-274-3/+17
| | | | | | | | | | | | | | Summary: This enables LTO to be used with the clang-cl frontend. Reviewers: rnk, hans Reviewed By: hans Subscribers: pcc, cfe-commits, mehdi_amini, Prazek Differential Revision: https://reviews.llvm.org/D30239 llvm-svn: 296373
* AMDGPU: Fold omod into instructionsMatt Arsenault2017-02-275-8/+723
| | | | llvm-svn: 296372
* [TailDuplicator] Maintain DebugLoc for branch instructionsTaewook Oh2017-02-272-1/+58
| | | | | | | | | | | | | | Summary: Existing implementation of duplicateSimpleBB function drops DebugLoc metadata of branch instructions during the transformation. This patch addresses this issue by making newly created branch instructions to keep the metadata of replaced branch instructions. Reviewers: qcolombet, craig.topper, aprantl, MatzeB, sanjoy, dblaikie Reviewed By: dblaikie Subscribers: dblaikie, llvm-commits Differential Revision: https://reviews.llvm.org/D30026 llvm-svn: 296371
* AMDGPU: Add f16 to shader calling conventionsMatt Arsenault2017-02-272-8/+33
| | | | | | Mostly useful for writing tests for f16 features. llvm-svn: 296370
* [SLP] Modify test to check IR flags propagation for extra args.Alexey Bataev2017-02-271-15/+15
| | | | llvm-svn: 296369
* AMDGPU: Add VOP3P instruction formatMatt Arsenault2017-02-2727-86/+1342
| | | | | | | | Add a few non-VOP3P but instructions related to packed. Includes hack with dummy operands for the benefit of the assembler llvm-svn: 296368
* Refactor xaluo.ll and xmulo.ll tests. NFCAmaury Sechet2017-02-272-493/+1781
| | | | llvm-svn: 296367
* [InlineFunction] add nonnull assumptions based on argument attributesSanjay Patel2017-02-272-23/+41
| | | | | | | | | | | This was suggested in D27855: have the inliner add assumptions, so we don't lose nonnull info provided by argument attributes. This still doesn't solve PR28430 (dyn_cast), but this gets us closer. https://reviews.llvm.org/D29999 llvm-svn: 296366
* [Hexagon] Defs and clobbers can overlapKrzysztof Parzyszek2017-02-271-5/+4
| | | | llvm-svn: 296365
* Fix a bug when unswitching on partial LIV for SwitchInstXin Tong2017-02-272-32/+339
| | | | | | | | | | | | | | Summary: Fix a bug when unswitching on partial LIV for SwitchInst. Reviewers: hfinkel, efriedma, sanjoy Reviewed By: sanjoy Subscribers: david2050, mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D29107 llvm-svn: 296363
* Fix comments. NFC.Rong Xu2017-02-271-1/+1
| | | | | | Change "Thin-LTO" to "ThinLTO" in the comments for consistency. llvm-svn: 296362
* [Cmake] Optionally use a system isl version.Michael Kruse2017-02-275-166/+216
| | | | | | | | | | | | | | | This patch adds an option to build against a version of libisl already installed on the system. The installation is autodetected using the pkg-config file shipped with isl. The detection of the library is in the FindISL.cmake module that creates an imported target. Contributed-by: Philip Pfaffe <philip.pfaffe@gmail.com> Differential Revision: https://reviews.llvm.org/D30043 llvm-svn: 296361
* Support NetBSD Thread ID in lldb-server testsKamil Rytarowski2017-02-272-0/+10
| | | | | | | | | | | | | | | | | | | | | Summary: Native Thread ID is retrieved with _lwp_self() on NetBSD. The returned value is of type int32_t, but for consistency with other Operating Systems cast it to uint64_t. Sponsored by <The NetBSD Foundation> Reviewers: joerg, labath, clayborg, emaste Reviewed By: labath, clayborg Subscribers: #lldb Tags: #lldb Differential Revision: https://reviews.llvm.org/D30374 llvm-svn: 296360
* Fix the project name in the license file.Arnaud A. de Grandmaison2017-02-271-2/+2
| | | | llvm-svn: 296359
* Add libcxxabi's LICENSE.TXT to libunwind.Arnaud A. de Grandmaison2017-02-271-0/+76
| | | | | | | | | | | When libunwind was spinned off libcxxabi, most file were copied from libcxxabi to libunwind. However, libc++abi's toplevel LICENSE.TXT was forgotten in the copying. It's considered a good practice to have the license file at the root of the project, and making linunwind a separate project was not supposed to change its licensing. Besides, several header files refer to the LICENSE.TXT, so copy the one from libc++abi. llvm-svn: 296358
* Fix LLVM module buildSteven Wu2017-02-271-0/+1
| | | | | | Add WasmRelocs/WebAssembly.def to textual include header. llvm-svn: 296356
* [X86] Use APInt instead of SmallBitVector tracking undef elements from ↵Craig Topper2017-02-271-25/+25
| | | | | | | | | | | | | | | | | | | getTargetConstantBitsFromNode and getConstVector. Summary: SmallBitVector uses a malloc for more than 58 bits on a 64-bit target and more than 27 bits on a 32-bit target. Some of the vector types we deal with here use more than those number of elements and therefore cause a malloc. APInt on the other hand supports up to 64 bits without a malloc. That's the maximum number of bits we need here so we can avoid a malloc for all cases by using APInt. Reviewers: RKSimon Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30392 llvm-svn: 296355
* [X86] Use APInt instead of SmallBitVector for tracking Zeroable elements in ↵Craig Topper2017-02-271-63/+57
| | | | | | | | | | | | | | | | | | | shuffle lowering Summary: SmallBitVector uses a malloc for more than 58 bits on a 64-bit target and more than 27 bits on a 32-bit target. Some of the vector types we deal with here use more than those number of elements and therefore cause a malloc. APInt on the other hand supports up to 64 bits without a malloc. That's the maximum number of bits we need here so we can avoid a malloc for all cases by using APInt. Reviewers: RKSimon Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30390 llvm-svn: 296354
* [X86] Fix SmallVector sizes in constant pool shuffle decoding to avoid heap ↵Craig Topper2017-02-271-5/+5
| | | | | | | | | | allocation Some of the vectors are under sized to avoid heap allocation. In one case the vector was oversized. Differential Revision: https://reviews.llvm.org/D30387 llvm-svn: 296353
* [X86] Use APInt instead of SmallBitVector for tracking undef elements in ↵Craig Topper2017-02-271-10/+10
| | | | | | | | | | | | | | | | | | | constant pool shuffle decoding Summary: SmallBitVector uses a malloc for more than 58 bits on a 64-bit target and more than 27 bits on a 32-bit target. Some of the vector types we deal with here use more than those number of elements and therefore cause a malloc. APInt on the other hand supports up to 64 bits without a malloc. That's the maximum number of bits we need here so we can avoid a malloc for all cases by using APInt. This will incur a minor increase in stack usage due to APInt storing the bit count separately from the data bits unlike SmallBitVector, but that should be ok. Reviewers: RKSimon Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30386 llvm-svn: 296352
* Fix LIBCXX_HAS_EXTERNAL_THREAD_API builds. NFC.Asiri Rathnayake2017-02-271-1/+2
| | | | | | Add the missing check in the __config header. llvm-svn: 296351
* Remove an empty line in icmp-illegal.ll . NFCAmaury Sechet2017-02-271-1/+0
| | | | llvm-svn: 296350
* [SLP] A test for a fix of PR32038.Alexey Bataev2017-02-271-0/+124
| | | | llvm-svn: 296349
* [DeLICM] Add nomap regressions tests. NFC.Michael Kruse2017-02-277-0/+547
| | | | | | | | | | | | These verify that some scalars are not mapped because it would be incorrect to do so. For these check we verify that no transformation has been executed from output of the pass's '-analyze'. Adding optimization remarks is not useful as it would result in too many messages, even repeated ones. I avoided checking the '-debug-only=polly-delicm' output which is an antipattern. llvm-svn: 296348
* [DeLICM] Statistics for use in regression tests.Michael Kruse2017-02-271-2/+42
| | | | | | | Print some measurements of the DeLICM transformation at -analyze to be used in regression tests. llvm-svn: 296347
* Fix typo in error message. NFC.Asiri Rathnayake2017-02-271-1/+1
| | | | llvm-svn: 296346
* Loop predication expand both sides of the widened conditionArtur Pilipenko2017-02-272-6/+83
| | | | | | | | | | | | This is a fix for a loop predication bug which resulted in malformed IR generation. Loop invariant side of the widened condition is not guaranteed to be available in the preheader as is, so we need to expand it as well. See added unsigned_loop_0_to_n_hoist_length test for example. Reviewed By: sanjoy, mkazantsev Differential Revision: https://reviews.llvm.org/D30099 llvm-svn: 296345
* Attempt to fix arm-native libcxxabi tests for the no-exceptions variantAsiri Rathnayake2017-02-272-0/+2
| | | | | | | | These tests embed calls to exceptions-related symbols from the abi library, which are absent in the no-exceptions variant. The tests need to be marked as unsupported for the no-exceptions configuration. llvm-svn: 296344
* AArch64InstPrinter: rewrite of printSysAliasSjoerd Meijer2017-02-273-316/+163
| | | | | | | | | | | | | | | | | | This is a cleanup/rewrite of the printSysAlias function. This was not using the tablegen instruction descriptions, but was "manually" decoding the instructions. This has been replaced with calls to lookup_XYZ_ByEncoding tablegen calls. This revealed several problems. First, instruction IVAU had the wrong encoding. This was cancelled out by the parser that incorrectly matched the wrong encoding. Second, instruction CVAP was missing from the SystemOperands tablegen descriptions, so this has been added. And third, the required target features were not captured in the tablegen descriptions, so support for this has also been added. Differential Revision: https://reviews.llvm.org/D30329 llvm-svn: 296343
* [ARM] LSL #0 is an alias of MOVJohn Brawn2017-02-274-12/+206
| | | | | | | | | | | | | | | | | | | | | | | | Currently we handle this correctly in arm, but in thumb we don't which leads to an unpredictable instruction being emitted for LSL #0 in an IT block and SP not being permitted in some cases when it should be. For the thumb2 LSL we can handle this by making LSL #0 an alias of MOV in the .td file, but for thumb1 we need to handle it in checkTargetMatchPredicate to get the IT handling right. We also need to adjust the handling of MOV rd, rn, LSL #0 to avoid generating the 16-bit encoding in an IT block. We should also adjust it to allow SP in the same way that it is allowed in MOV rd, rn, but I haven't done that here because it looks like it would take quite a lot of work to get right. Additionally correct the selection of the 16-bit shift instructions in processInstruction, where it was checking if the two registers were equal when it should have been checking if they were low. It appears that previously this code was never executed and the 16-bit encoding was selected by default, but the other changes I've done here have somehow made it start being used. Differential Revision: https://reviews.llvm.org/D30294 llvm-svn: 296342
* [clang-format] Add a NamespaceEndCommentsFixerKrasimir Georgiev2017-02-2710-3/+590
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds a NamespaceEndCommentsFixer TokenAnalyzer for clang-format, which fixes end namespace comments. It currently supports inserting and updating existing wrong comments. Example source: ``` namespace A { int i; } namespace B { int j; } // namespace A ``` after formatting: ``` namespace A { int i; } // namespace A namespace B { int j; } // namespace B ``` Reviewers: klimek, djasper Reviewed By: djasper Subscribers: klimek, mgorny Differential Revision: https://reviews.llvm.org/D30269 llvm-svn: 296341
* Add a test we already get right.Rafael Espindola2017-02-271-0/+14
| | | | | | It would have found a problem in a patch I am writing. llvm-svn: 296339
* Fix cmake dependency for the external-thread-library variant. NFC.Asiri Rathnayake2017-02-271-1/+1
| | | | llvm-svn: 296338
* [clang-move] Extend clang-move to support moving global variable.Haojian Wu2017-02-275-2/+92
| | | | | | | | | | | | | | Summary: Also support dumping global variables. Reviewers: ioeric Reviewed By: ioeric Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D30337 llvm-svn: 296337
* [DAGCombine] Fix for a load combine bug with non-zero offset patterns on BE ↵Artur Pilipenko2017-02-273-0/+56
| | | | | | | | | | | | | | | | | | targets This pattern is essentially a i16 load from p+1 address: %p1.i16 = bitcast i8* %p to i16* %p2.i8 = getelementptr i8, i8* %p, i64 2 %v1 = load i16, i16* %p1.i16 %v2.i8 = load i8, i8* %p2.i8 %v2 = zext i8 %v2.i8 to i16 %v1.shl = shl i16 %v1, 8 %res = or i16 %v1.shl, %v2 Current implementation would identify %v1 load as the first byte load and would mistakenly emit a i16 load from %p1.i16 address. This patch adds a check that the first byte is loaded from a non-zero offset of the first load address. This way this address can be used as the base address for the combined value. Otherwise just give up combining. llvm-svn: 296336
* Merge Linux and FreeBSD arm register contextsPavel Labath2017-02-278-195/+32
| | | | | | | | | | | | | | Summary: These two register contexts were identical, so this shouldn't cause any regressions, but I'd appreciate it if you can check that this at least compiles. Reviewers: emaste, sas Subscribers: aemerson, rengolin, lldb-commits, mgorny Differential Revision: https://reviews.llvm.org/D27126 llvm-svn: 296335
* Fix MinidumpParserTest on 32-bit archesPavel Labath2017-02-271-2/+3
| | | | | | | | load_size should be 64-bit unconditionally to match the underlying API. This makes sure the MAX value correctly signals to auto-detect the file size when mmap()ing. llvm-svn: 296334
* Remove the callback-based log channel registration mechanismPavel Labath2017-02-273-88/+2
| | | | | | | All the existing channels have beens switched to the new mechanism and this code is now unused. llvm-svn: 296333
* [DAGCombine] NFC. MatchLoadCombine extract MemoryByteOffset lambda helperArtur Pilipenko2017-02-271-9/+13
| | | | | | This refactoring will simplify the upcoming change to fix the bug in folding patterns with non-zero offsets on BE targets. llvm-svn: 296332
* [DAGCombine] NFC. MatchLoadCombine remember the first byte provider, not the ↵Artur Pilipenko2017-02-271-3/+5
| | | | | | | | load node This refactoring will simplify the upcoming change to fix a bug in folding patterns with non-zero offsets on BE targets. llvm-svn: 296331
* clang-format: [JS] whitespace after async in arrow functions.Martin Probst2017-02-272-0/+10
| | | | | | | | | | | | | | | | | | | Summary: Async arrow functions should be marked with a whitespace after the async keyword, before the parameter list: x = async () => foo(); Before: x = async() => foo(); This makes it easier to tell apart an async arrow function from a call to a function called async. Reviewers: bkramer Subscribers: cfe-commits, klimek Differential Revision: https://reviews.llvm.org/D30399 llvm-svn: 296330
* Log: Fix a regression in handling log optionsPavel Labath2017-02-273-3/+19
| | | | | | | | The channel refactor introduced a regression where we were not honoring the log options passed when enabling the channel. Fix that and add a test. llvm-svn: 296329
* Switch SBBreakpoint to storing a weak_ptr of the internal breakpoint objectPavel Labath2017-02-276-277/+253
| | | | | | | | | | | | | | | | | Summary: There is nothing we can do with the breakpoint once the associated target becomes deleted. This will make sure we don't hold on to more resources than we need in this case. In particular, this fixes the case TestStepOverBreakpoint on windows, where a lingering SBBreakpoint object causes us to nor unmap the executable file from memory. Reviewers: clayborg, jingham Subscribers: lldb-commits Differential Revision: https://reviews.llvm.org/D30249 llvm-svn: 296328
* AArch64AsmParser: don't try to parse “[1]” for non-vector register operandsSjoerd Meijer2017-02-271-25/+0
| | | | | | | | | There are no instructions that have "[1]" as part of the assembly string; FMOVXDhighr is out of date. This removes dead code. Differential Revision: https://reviews.llvm.org/D30165 llvm-svn: 296327
* [analyzer] clarify 'result is garbage value' when it is out of boundsDaniel Marjamaki2017-02-272-0/+32
| | | | | | Differential Revision: https://reviews.llvm.org/D28278 llvm-svn: 296326
* Disable the parallel code generation in case of extension nodesRoman Gareev2017-02-271-0/+8
| | | | | | | | | | | We can not perform the dependence analysis and, consequently, the parallel code generation in case the schedule tree contains extension nodes. Reviewed-by: Tobias Grosser <tobias@grosser.es> Differential Revision: https://reviews.llvm.org/D30394 llvm-svn: 296325
* [AMDGPU] Runtime metadata fixes:Konstantin Zhuravlyov2017-02-2710-74/+270
| | | | | | | | | | | - Verify that runtime metadata is actually valid runtime metadata when assembling, otherwise we could accept the following when assembling, but ocl runtime will reject it: .amdgpu_runtime_metadata { amd.MDVersion: [ 2, 1 ], amd.RandomUnknownKey, amd.IsaInfo: ... - Make IsaInfo optional, and always emit it. Differential Revision: https://reviews.llvm.org/D30349 llvm-svn: 296324
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