| Commit message (Collapse) | Author | Age | Files | Lines |
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AMDGPU::SI_SPILL_V96_RESTORE was missing from a switch statement, which
caused the srsrc and soffset register to not be set correctly.
This commit replaces the switch statement with a SITargetInfo query
to make sure all spill instructions are covered.
Differential Revision: http://reviews.llvm.org/D9582
llvm-svn: 237164
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-workers=M is not. Update the docs.
llvm-svn: 237163
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Summary:
GetCurrentDirectory() returns the number of characters copied; 0 is a failure, not a success.
Add implementation for chdir().
Reviewers: zturner
Reviewed By: zturner
Subscribers: lldb-commits
Differential Revision: http://reviews.llvm.org/D9300
llvm-svn: 237162
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Mostly uninteresting, except:
- in __extendXfYf2, when checking if the number is normal, the old
code relied on the unsignedness of src_rep_t, which is a problem
when sizeof(src_rep_t) < sizeof(int): the result gets promoted to
int, the signedness of which breaks the comparison.
I added an explicit cast; it shouldn't affect other types.
- we can't pass __fp16, so src_t and src_rep_t are the same.
- the gnu_*_ieee symbols are simply duplicated definitions, as aliases
are problematic on mach-o (where only weak aliases are supported;
that's not what we want).
Differential Revision: http://reviews.llvm.org/D9693
llvm-svn: 237161
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'Iff' isn't a typo, it's a shorthand for 'if and only if'.
llvm-svn: 237160
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GetOutputStream() owns the stream it returns pointer to and the
pointer should never be freed by us. When we fail to load and exit
early, unique_ptr still holds the pointer and frees it which leads to
compiler crash when CompilerInstance attempts to free it again.
Added regression test for failed bitcode linking.
Differential Revision: http://reviews.llvm.org/D9625
llvm-svn: 237159
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This patch implements SELEQZ and SELNEZ instructions using mapping.
Differential Revision: http://reviews.llvm.org/D8497
llvm-svn: 237158
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llvm-svn: 237157
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Summary:
This patch reimplements heuristic that tries to estimate optimization beneftis
from complete loop unrolling.
In this patch I kept the minimal changes - e.g. I removed code handling
branches and folding compares. That's a promising area, but now there
are too many questions to discuss before we can enable it.
Test Plan: Tests are included in the patch.
Reviewers: hfinkel, chandlerc
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D8816
llvm-svn: 237156
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This implementation was ported from the AMD builtin library
and has been tested with piglit, OpenCV, and the ocl conformance tests.
llvm-svn: 237155
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This implementation was ported from the AMD builtin library
and has been tested with piglit, OpenCV, and the ocl conformance tests.
llvm-svn: 237154
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On Mips, frame pointer points to the same side of the frame as the stack
pointer. This function is used to decide where to put register scavenging
spill slot. So far, it was put on the wrong side of the frame, and thus it
was too far away from $fp when frame was larger than 2^15 bytes.
Patch by Vladimir Radosavljevic.
http://reviews.llvm.org/D8895
llvm-svn: 237153
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Spilling can insert instructions almost anywhere, and this can mess
up control flow lowering in a multitude of ways, due to instruction
reordering. Let's sort this out the easy way: never spill registers
involved with control flow, i.e. saved EXEC masks.
Unfortunately, this does not work at all with optimizations disabled,
as the register allocator ignores spill weights. This should be
addressed in a future commit.
The test was reduced from the "stacks" shader of [1]. Some issues
trigger the machine verifier while another one is checked manually.
[1] http://madebyevan.com/webgl-path-tracing/
v2: only insert pass with optimizations enabled, merge test runs.
Patch by: Grigori Goronzy
llvm-svn: 237152
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details in http://reviews.llvm.org/D9483
goes with llvm checkin r237150
llvm-svn: 237151
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One code change and several test changes to match that
details in http://reviews.llvm.org/D9481
llvm-svn: 237150
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llvm-svn: 237149
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llvm-svn: 237148
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This should finally fix it.
llvm-svn: 237147
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llvm-svn: 237146
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dwarf-4
The DWARF-4 specification added 2 new fields in the CIE header called
address_size and segment_size.
Create these 2 new fields when generating dwarf-4 CIE entries, print out
the new fields when dumping the CIE and update tests
Differential Revision: http://reviews.llvm.org/D9558
llvm-svn: 237145
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llvm-svn: 237144
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We had code to do this in SIRegisterInfo::eliminateFrameIndex(), but
it is easier to just change the definition of SI_SPILL_S32_RESTORE to
only allow numbered sgprs.
llvm-svn: 237143
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It is no longer used.
llvm-svn: 237142
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Instead add m0 as an implicit operand. This helps avoid spills
of the m0 register in some cases.
llvm-svn: 237141
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Instead add m0 as an implicit operand. This helps avoid spills
of the m0 register in some cases.
llvm-svn: 237140
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llvm-svn: 237139
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This implementation was ported from the AMD builtin library
and has been tested with piglit, OpenCV, and the ocl conformance tests.
llvm-svn: 237138
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llvm-svn: 237137
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include the VS directory structure.
llvm-svn: 237136
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llvm-svn: 237135
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We want to make sure that the m0 copies are being cse'd.
llvm-svn: 237134
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Instead add m0 as an implicit operand. This allows us to avoid using
the M0Reg register class and eliminates a number of unnecessary spills
when using s_sendmsg instructions. This impacts one shader in the
shader-db:
SGPRS: 48 -> 40 (-16.67 %)
VGPRS: 112 -> 108 (-3.57 %)
Code Size: 40132 -> 38796 (-3.33 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 2048 -> 0 (-100.00 %) bytes per wave
llvm-svn: 237133
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TRI->getRegClass() takes a register class ID, not a register. We were
using this incorrectly in a few places.
llvm-svn: 237132
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This implementation was ported from the AMD builtin library
and has been tested with piglit, OpenCV, and the ocl conformance tests.
llvm-svn: 237131
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llvm-svn: 237130
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The other changes in the LowerShift() are not functional,
just to make the code more convenient.
So, the functional changes for SKX only.
llvm-svn: 237129
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Updated PlatformLinux::GetSupportedArchitectureAtIndex to call the
PlatformRemoteGdbServer::GetSupportedArchitectureAtIndex if connected remotely.
This should return the correct thing for android (to fix those failing tests),
and is also working for mac to linux.
Test Plan:
./dotest.py $DOTEST_OPTS -t -p TestCallStdStringFunction.py
The above still passes when running mac->linux indicating it successfully
identified PlatformLinux as the target platform and converted the mmap options
correctly.
Differential Revision: http://reviews.llvm.org/D9672
llvm-svn: 237128
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AEABI defines aligned variants of memcpy etc. that can be faster than
the default version due to not having to do alignment checks. When
emitting target code for these functions make use of these aligned
variants if possible. Also convert memset to memclr if possible.
Differential Revision: http://reviews.llvm.org/D8060
llvm-svn: 237127
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According to the documentation in StackMap section for the safepoint we should have:
"The first Location in each pair describes the base pointer for the object. The second is the derived pointer actually being relocated."
But before this change we emitted them in reverse order - derived pointer first, base pointer second.
llvm-svn: 237126
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optionally use added file.
llvm-svn: 237125
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synchronizes runtime/README.txt and www/README.txt, updates the building-with-CMake documentation. This change also changes references of Intel(R) OpenMP Library to LLVM OpenMP Library.
llvm-svn: 237124
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llvm-svn: 237123
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Before revision 171146, function 'PerformTruncateCombine' used to perform
a premature lowering of TRUNCATE dag nodes.
Revision 171146 then moved all the logic implemented by PerformTruncateCombine
to a custom lowering hook. However, that revision forgot to delete
function PerformTruncateCombine from the code.
This patch removes function 'PerformTruncateCombine' since it has no effect
on the SelectionDAG. No functional change intended.
llvm-svn: 237122
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Summary: Allow calls with non legal integer types based on i8 and i16 to be processed by mips fast-isel.
Based on a patch by Reed Kotler.
Test Plan:
"Make check" test forthcoming.
Test-suite passes at O0/O2 and with mips32 r1/r2
Reviewers: rkotler, dsanders
Subscribers: llvm-commits, rfuhler
Differential Revision: http://reviews.llvm.org/D6770
llvm-svn: 237121
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This solves some false negatives at a cost of adding some false positives that
can be fixed easily and (almost) automatically.
llvm-svn: 237120
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Reviewers: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D9635
llvm-svn: 237119
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This patch adds new default flag -fno-builtin which forces gcc to not optimize builtin functions.
For example, without this flag GCC replaces printf("hello\n") -> puts("hello") even if -O0 was specified
Also this patch fixes the MiDataTestCase.test_lldbmi_data_disassemble test on Linux/gcc.
llvm-svn: 237118
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Summary:
Try to compute addresses when the offset from a memory location is a constant
expression.
Based on a patch by Reed Kotler.
Test Plan:
Passes test-suite for -O0/O2 and mips 32 r1/r2
Reviewers: rkotler, dsanders
Subscribers: llvm-commits, aemerson, rfuhler
Differential Revision: http://reviews.llvm.org/D6767
llvm-svn: 237117
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Patch thanks to Vladimir Voskresensky.
llvm-svn: 237116
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Patch thanks to Vladimir Voskresensky.
llvm-svn: 237115
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