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* [gen_ast_dump_json_test.py] Add a --update flagAlex Richardson2019-11-151-12/+21
| | | | | | | | | This will allow updating the JSON tests for new format changes. Instead of simply appending the JSON to the input file, the script will now make a copy of the input file up to the "CHECK lines have been autogenerated" disclaimer and then append the new JSON. See https://reviews.llvm.org/D70119
* DWARFDebugLoc(v4): Add an incremental parsing functionPavel Labath2019-11-1527-197/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This adds a visitLocationList function to the DWARF v4 location lists, similar to what already exists for DWARF v5. It follows the approach outlined in previous patches (D69672), where the parsed form is always stored in the DWARF v5 format, which makes it easier for generic code to be built on top of that. v4 location lists are "upgraded" during parsing, and then this upgrade is undone while dumping. Both "inline" and section-based dumping is rewritten to reuse the existing "generic" location list dumper. This means that the output format is consistent for all location lists (the only thing one needs to implement is the function which prints the "raw" form of a location list), and that debug_loc dumping correctly processes base address selection entries, etc. The previous existing debug_loc functionality (e.g., parseOneLocationList) is rewritten on top of the new API, but it is not removed as there is still code which uses them. This will be done in follow-up patches, after I build the API to access the "interpreted" location lists in a generic way (as that is what those users really want). Reviewers: dblaikie, probinson, JDevlieghere, aprantl, SouraVX Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69847
* [CodeGen] Increase the size of a SmallVectorJay Foad2019-11-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SmallVector reserve() call in MachineInstrExpressionTrait::getHashValue accounted for over 3% of all calls to malloc() when I compiled a bunch of graphics shaders for the AMDGPU target. Its initial size was only enough for machine instructions with up to 7 operands, but for AMDGPU 8 and 10 operands are very common. Here's a histogram of number of operands for each call to getHashValue, gathered from the same collection of shaders: 1 13503 2 254273 3 135781 4 422508 5 614997 6 194953 7 287248 8 1517255 9 31218 10 1191269 11 70731 12 24 13 77 15 84 17 4692 27 16 33 705 49 6 Typical instructions with 8 and 10 operands are floating point arithmetic and multiply-accumulate instructions like: %83:vgpr_32 = V_MUL_F32_e64 0, killed %82:vgpr_32, 0, killed %81:vgpr_32, 0, 0, implicit $exec %330:vgpr_32 = V_MAC_F32_e64 0, killed %327:vgpr_32, 0, killed %329:sgpr_32, 0, %328:vgpr_32(tied-def 0), 0, 0, implicit $exec Differential Revision: https://reviews.llvm.org/D70301
* Revert "[clang] Remove the DIFlagArgumentNotModified debug info flag"Djordje Todorovic2019-11-153-0/+71
| | | | This reverts commit rG1643734741d2 due to LLDB test failure.
* [ARM][MVE] tail-predicationSjoerd Meijer2019-11-152-0/+29
| | | | | | | This is a follow up of d90804d, to also flag fmcp instructions as instructions that we do not support in tail-predicated vector loops. Differential Revision: https://reviews.llvm.org/D70295
* [MIPS GlobalISel] Select andi, ori and xoriPetar Avramovic2019-11-1524-520/+585
| | | | | | | | | | | | | Introduce IntImmLeaf version of PatLeaf immZExt16 for 32-bit immediates. Change immZExt16 with imm32ZExt16 for andi, ori and xori. This keeps same behavior for SDAG and allows for GlobalISel selectImpl to select 'G_CONSTANT imm' + G_AND, G_OR, G_XOR into ANDi, ORi, XORi, respectively, when 32-bit imm satisfies imm32ZExt16 predicate: zero extending 16 low bits of imm is equal to imm. Large number of test changes comes from zero extending of small types which is transformed into 'and' with bitmask in legalizer. Differential Revision:https://reviews.llvm.org/D70185
* [MIPS GlobalISel] Select addiuPetar Avramovic2019-11-154-5/+112
| | | | | | | | | | Introduce IntImmLeaf version of PatLeaf immSExt16 for 32-bit immediates. Change immSExt16 with imm32SExt16 for addiu. This keeps same behavior for SDAG and allows for GlobalISel selectImpl to select 'G_CONSTANT imm' + G_ADD into ADDIu when 32-bit imm satisfies imm32SExt16 predicate: sign extending 16 low bits of imm is equal to imm. Differential Revision: https://reviews.llvm.org/D70184
* [Scalarizer] Treat values from unreachable blocks as undefMikael Holmen2019-11-152-5/+125
| | | | | | | | | | | | | | | | | | | | | | | | Summary: When scalarizing PHI nodes we might try to examine/rewrite InsertElement nodes in predecessors. If those predecessors are unreachable from entry, then the IR in those blocks could have unexpected properties resulting in infinite loops in Scatterer::operator[]. By simply treating values originating from instructions in unreachable blocks as undef we do not need to analyse them further. This fixes PR41723. Reviewers: bjope Reviewed By: bjope Subscribers: bjope, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70171
* [clang] Remove the DIFlagArgumentNotModified debug info flagDjordje Todorovic2019-11-153-71/+0
| | | | | | | | | | It turns out that the ExprMutationAnalyzer can be very slow when AST gets huge in some cases. The idea is to move this analysis to the LLVM back-end level (more precisely, in the LiveDebugValues pass). The new approach will remove the performance regression, simplify the implementation and give us front-end independent implementation. Differential Revision: https://reviews.llvm.org/D68206
* [ARM,MVE] Add intrinsics for vector get/set lane.Simon Tatham2019-11-1514-23/+381
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the `vgetq_lane` and `vsetq_lane` families, to copy between a scalar and a specified lane of a vector. One of the new `vgetq_lane` intrinsics returns a `float16_t`, which causes a compile error if `%clang_cc1` doesn't get the option `-fallow-half-arguments-and-returns`. The driver passes that option to cc1 already, but I've had to edit all the explicit cc1 command lines in the existing MVE intrinsics tests. A couple of fixes are included for the code I wrote up front in MveEmitter to support lane-index immediates (and which nothing has tested until now): the type was wrong (`uint32_t` instead of `int`) and the range was off by one. I've also added a method of bypassing the default promotion to `i32` that is done by the MveEmitter code generation: it's sensible to promote short scalars like `i16` to `i32` if they're going to be passed to custom IR intrinsics representing a machine instruction operating on GPRs, but not if they're going to be passed to standard IR operations like `insertelement` which expect the exact type. Reviewers: ostannard, MarkMurrayARM, dmgreen Reviewed By: dmgreen Subscribers: kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D70188
* [ARM,MVE] Add intrinsics for 'administrative' vector operations.Simon Tatham2019-11-154-17/+1661
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This batch of intrinsics includes lots of things that move vector data around or change its type without really affecting its value very much. It includes the `vreinterpretq` family (cast one vector type to another); `vuninitializedq` (create a vector of a given type with don't-care contents); and `vcreateq` (make a 128-bit vector out of two `uint64_t` halves). These are all implemented using completely standard IR that's already tested in existing LLVM unit tests, so I've just written a clang test to check the IR is correct, and left it at that. I've also added some richer infrastructure to the MveEmitter Tablegen backend, to make it specify the exact integer type of integer arguments passed to IR construction functions, and wrap those arguments in a `static_cast` in the autogenerated C++. That was necessary to prevent an overloading ambiguity when passing the integer literal `0` to `IRBuilder::CreateInsertElement`, because otherwise, it could mean either a null pointer `llvm::Value *` or a zero `uint64_t`. Reviewers: ostannard, MarkMurrayARM, dmgreen Subscribers: kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D70133
* [AST] Use written names instead of `type-param-0-0` in more cases when ↵Sam McCall2019-11-155-43/+44
| | | | | | | | | | | | | | | | | | | printing types and decls. Summary: This doesn't cover decls in diagnostics, which use NamedDecl::getNameForDiagnostic(). (That should also be fixed later I think). This covers some cases of https://github.com/clangd/clangd/issues/76 (hover, but not outline or sighelp) Reviewers: hokein Subscribers: ilya-biryukov, jkorous, arphaman, kadircet, usaxena95, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D70236
* Fix GCC -Wcast-qual warningsHans Wennborg2019-11-151-2/+2
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* GCC 5.3 build fixHans Wennborg2019-11-151-1/+1
| | | | | | | | | | It was failing with llvm/lib/ExecutionEngine/Orc/DebugUtils.cpp:56:10: error: could not convert ‘Obj’ from ‘std::unique_ptr<llvm::MemoryBuffer>’ to ‘llvm::Expected<std::unique_ptr<llvm::MemoryBuffer> >’ return Obj; ^
* AMDGPU: Change boolean content type to 0 or 1Matt Arsenault2019-11-159-21/+33
| | | | | | | | The usage of target boolean checks is overly inflexible, since sext and zext of a compare are equally cheap. The choice is arbitrary, but using 0/1 to some degree is the choice of lower resistance since that's what most targets use. This enables a few combines that don't bother to support ZeroOrNegativeOneBooleanContent.
* AMDGPU: Try to commute sub of boolean extMatt Arsenault2019-11-152-3/+69
| | | | Avoids another regression in a future patch.
* GlobalISel: Lower s1 source G_SITOFP/G_UITOFPMatt Arsenault2019-11-1510-540/+180
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* Unbreak the clang test suite when hexagon-link is not availableDavid Zarzycki2019-11-151-1/+1
| | | | | All of the other tests are of the form {{hexagon-link|ld}} so this probably should be too.
* gn build: Merge 16f38dda292LLVM GN Syncbot2019-11-151-0/+1
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* [ORC] Add a utility to support dumping JIT'd objects to disk for debugging.Lang Hames2019-11-1411-13/+236
| | | | | | | | | Adds a DumpObjects utility that can be used to dump JIT'd objects to disk. Instances of DebugObjects may be used by ObjectTransformLayer as no-op transforms. This patch also adds an ObjectTransformLayer to LLJIT and an example of how to use this utility to dump JIT'd objects in LLJIT.
* [llvm-objcopy][MachO] Implement --remove-sectionSeiya Nuta2019-11-153-5/+142
| | | | | | | | | | | | Reviewers: alexshap, rupprecht, jhenderson Reviewed By: rupprecht, jhenderson Subscribers: jakehehrlich, abrachet, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66282
* Add a test to cover structural match for recursive data typesBruno Cardoso Lopes2019-11-145-0/+27
| | | | | | | This didn't use to work prior to r370639, now that this is supported add a testcase to prevent regressions. rdar://problem/53602368
* [InstCombine] Don't use getFirstNonPHI in FoldIntegerTypedPHIFrancis Visoiu Mistrih2019-11-141-4/+5
| | | | | | | | | | | | | | | | | | | getFirstNonPHI iterates over all the instructions in a block until it finds a non-PHI. Then, the loop starts from the beginning of the block and goes through all the instructions until it reaches the instruction found by getFirstNonPHI. Instead of doing that, just stop when a non-PHI is found. This reduces the compile-time of a test case discussed in https://reviews.llvm.org/D47023 by 13x. Not entirely sure how to come up with a test case for this since it's a compile time issue that would significantly slow down running the tests. Differential Revision: https://reviews.llvm.org/D70016
* [WinEH] Fix the wrong alignment orientation during calculating EH frame.Wang, Pengfei2019-11-152-10/+10
| | | | | | | | | | | | Summary: This is a bug fix for further issues in PR43585. Reviewers: rnk, RKSimon, craig.topper, andrew.w.kaylor Subscribers: hiraditya, llvm-commits, annita.zhang Tags: #llvm Differential Revision: https://reviews.llvm.org/D70224
* [Utility] Remove a dead header [PPC64LE_ehframe_Registers.h]Davide Italiano2019-11-141-193/+0
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* Add missing includes needed to prune LLVMContext.h include, NFCReid Kleckner2019-11-1465-9/+74
| | | | | These are a pre-requisite to removing #include "llvm/Support/Options.h" from LLVMContext.h: https://reviews.llvm.org/D70280
* [libc++] [P0920] [P1661] Update status page.Marek Kurdej2019-11-151-2/+2
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* [LLDB] Fix more -Wdocumentation issues (NFC)Jonas Devlieghere2019-11-147-31/+31
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* [COFF] Avoid CodeView include in headerReid Kleckner2019-11-143-6/+8
| | | | | Most LLD/COFF files don't care about CodeView. Avoid using CodeView types in InputFiles.h.
* Forward declare the DWARFCache to avoid including LLVM DWARF detailsReid Kleckner2019-11-144-2/+6
| | | | | LLD's DWARF.h header leaks a lot of LLVM DWARF includes that LLD doesn't need. For Chunks.cpp, I see a compile time decrease of 3.1s to 2.7s.
* [Reproducer] Enable crash reports for reproducer testsJonas Devlieghere2019-11-141-0/+2
| | | | | | | | | | | | | For some reason the reproducer tests seem really proficient at uncovering structural issues in LLDB related to how we tear down things, but of course only on the bots. The pretty stack trace helps a bit, but what I really want is the crash reports which contain much more information, such as what other threads we doing. Crash reports are automatically suppressed by lit. This patch (temporarily) disables that for the reproducer tests.
* [BPF] Restrict preserve_access_index attribute to C onlyYonghong Song2019-11-143-31/+22
| | | | | | | | | | | | This patch is a follow-up for commit 4e2ce228ae79 [BPF] Add preserve_access_index attribute for record definition to restrict attribute for C only. A new test case is added to check for this restriction. Additional code polishing is done based on Aaron Ballman's suggestion in https://reviews.llvm.org/D69759/new/. Differential Revision: https://reviews.llvm.org/D70257
* [SanitizerCommon] Print the current value of options when printing out help.Dan Liew2019-11-145-5/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Previously it wasn't obvious what the default value of various sanitizer options were. A very close approximation of the "default values" for the options are the current value of the options at the time of printing the help output. In the case that no other options are provided then the current values are the default values (apart from `help`). ``` ASAN_OPTIONS=help=1 ./program ``` This patch causes the current option values to be printed when the `help` output is enabled. The original intention for this patch was to append `(Default: <value>)` to an option's help text. However because this is technically wrong (and misleading) I've opted to append `(Current Value: <value>)` instead. When trying to implement a way of displaying the default value of the options I tried another solution where the default value used in `*.inc` files were used to create compile time strings that where used when printing the help output. This solution was not satisfactory for several reasons: * Stringifying the default values with the preprocessor did not work very well in several cases. Some options contain boolean operators which no amount of macro expansion can get rid of. * It was much more invasive than this patch. Every sanitizer had to be changed. * The settings of `__<sanitizer>_default_options()` are ignored. For those reasons I opted for the solution in this patch. rdar://problem/42567204 Reviewers: kubamracek, yln, kcc, dvyukov, vitalybuka, cryptoad, eugenis, samsonov Subscribers: #sanitizers, llvm-commits Tags: #sanitizers, #llvm Differential Revision: https://reviews.llvm.org/D69546
* [COFF] Don't include llvm/LTO/LTO.h in a headerReid Kleckner2019-11-145-3/+15
| | | | | LLVM's LTO header includes all of llvm/IR, which most of the COFF linker doesn't need.
* Revert "Temporarily Revert:"Alexey Bataev2019-11-1422-506/+1054
| | | | | | | | | | | | This reverts commit e511c4b0dff1692c267addf17dce3cebe8f97faa: Temporarily Revert: "[SLP] Generalization of stores vectorization." "[SLP] Fix -Wunused-variable. NFC" "[SLP] Vectorize jumbled stores." after fixing the problem with compile time.
* [llvm-dis] Fix the disable-output flagMatthew Voss2019-11-141-1/+1
| | | | | | My change in llvmorg-10-init-9872-g141bb5f308f broke this flag. Thanks to @rsmith for the bug.
* [GPGPU] Fix depricated warning.Michael Kruse2019-11-141-1/+1
| | | | | | | setAlignment(unsigned) was deprecated in commit: 0e62011df891d0e7ad904524edf705d07d12d5d4 [Alignment][NFC] Remove dependency on GlobalObject::setAlignment(unsigned)
* [X86] Fix the implementation of __readcr3/__writecr3 to work in 64-bit modeCraig Topper2019-11-142-13/+16
| | | | | | | | | | | | We need to use a 64-bit type in 64-bit mode so a 64-bit register will get used in the generated assembly. I've also changed the constraints to just use "r" intead of "q". "q" forces to a only an a/b/c/d register in 32-bit mode, but I see no reason that would matter here. Fixes Nico's note in PR19301 over 4 years ago. Differential Revision: https://reviews.llvm.org/D70101
* [DebugInfo] Allow spill slots in call site parameter descriptionsVedant Kumar2019-11-143-5/+200
| | | | | | | | | | | | | | | | | | | | | | Allow call site paramter descriptions to reference spill slots. Spill slots are not visible to high-level LLVM IR, so they can safely be referenced during entry value evaluation (as they cannot be clobbered by some other function). This gives a 5% increase in the number of call site parameter DIEs in an LTO x86_64 build of the xnu kernel. This reverts commit eb4c98ca3d2590bad9f6542afbf3a7824d2b53fa ( [DebugInfo] Exclude memory location values as parameter entry values), effectively reintroducing the portion of D60716 which dealt with memory locations (authored by Djordje, Nikola, Ananth, and Ivan). This partially addresses llvm.org/PR43343. However, not all memory operands forwarded to callees live in spill slots. In the xnu build, it may be possible to use an escape analysis to increase the number of call site parameter by another 15% (more details in PR43343). Differential Revision: https://reviews.llvm.org/D70254
* [yaml2obj][COFF] Add support for extended relocation tablesSergey Dmitriev2019-11-142-3/+81
| | | | | | | | | | | | | | | | | Summary: The tool does not correctly handle COFF sections with extended relocation tables (with IMAGE_SCN_LNK_NRELOC_OVFL bit set), this patch fixes this problem. But I have cheated a bit in the test (to make it smaller) because extended relocation table is supposed to be used when the number of relocations exceeds 65534. Otherwise the test size would be pretty big. Reviewers: jhenderson, MaskRay, mstorsjo Reviewed By: mstorsjo Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70251
* [GPGPU] Fix #includes.Michael Kruse2019-11-142-0/+2
| | | | | | Adapt for 05da2fe52162 "Sink all InitializePasses.h includes" which forgot the GPGPU files (presumably because POLLY_ENABLE_GPGPU_CODEGEN is OFF by default).
* [globalisel][irtanslator] The IRTranslator should preserve TBAA informationDaniel Sanders2019-11-142-5/+34
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* [lldb][Editline] Support ctrl+left/right arrow word navigation.Jordan Rupprecht2019-11-142-0/+58
| | | | | | | | | | | | | | | | | Summary: This adds several 5C/5D escape codes that allow moving forward/backward words similar to bash command line navigation. On my terminal, `ctrl+v ctrl+<left arrow>` prints `^[[1;5D`. However, it seems inputrc also maps other escape variants of this to forward/backward word, so I've included those too. Similar for 5C = ctrl+right arrow. Reviewers: JDevlieghere, labath Reviewed By: JDevlieghere, labath Subscribers: merge_guards_bot, lldb-commits Tags: #lldb Differential Revision: https://reviews.llvm.org/D70137
* Fix up lit's tests to run in a multi-config build environment.Paul Robinson2019-11-141-0/+3
| | | | Differential Revision: https://reviews.llvm.org/D70239
* [Pipeliner] Fix an assertion caused by iterator invalidation.Sumanth Gundapaneni2019-11-142-2/+35
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* [Hexagon] Validate the iterators before converting them to mux.Sumanth Gundapaneni2019-11-142-2/+38
| | | | | | The conditional instructions that are translated to mux instructions are deleted and the iterators to these deleted instructions are being used later. This patch fixed this issue.
* [Hexagon] Fix clang driver to parse -mcpu/-mvXX and -march properly.Sumanth Gundapaneni2019-11-142-1/+14
| | | | | | Before this patch if we pass "-mcpu=hexagonv65 -march=hexagon" in this order, the driver fails to figure out the correct cpu version. This patch fixed this issue.
* Update lit infra to detect "MemoryWithOrigins' sanitizer build.Sumanth Gundapaneni2019-11-141-1/+1
| | | | Differential Revision: https://reviews.llvm.org/D68399
* [RISCV] Use addi rather than add x0Sam Elliott2019-11-142-23/+23
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The RISC-V backend used to generate `add <reg>, x0, <reg>` in a few instances. It seems most places no longer generate this sequence. This is semantically equivalent to `addi <reg>, <reg>, 0`, but the latter has the advantage of being noted to be the canonical instruction to be used for moves (which microarchitectures can and should recognise as such). The changed testcases use instruction aliases - `mv <reg>, <reg>` is an alias for `addi <reg>, <reg>, 0`. Reviewers: luismarques Reviewed By: luismarques Subscribers: hiraditya, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, sameer.abuasal, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70124
* Add support for multi-module bitcode files to llvm-disMatthew Voss2019-11-145-51/+92
| | | | | | | | | | | | | | Summary: This change allows llvm-dis to disassemble multi-module bitcode files, including the associated module summary. Reviewers: tejohnson, pcc, mehdi_amini Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70153
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