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* [x86] Update the exact FileCheck syntax of the 256-bit and 512-bitChandler Carruth2014-09-305-1961/+1962
| | | | | | | | | | | shuffle tests to match that used in the script I posted and now used consistently in 128-bit tests. Nothing interesting changing here, just using the label name as the FileCheck label and a slightly more general comment marker consumption strategy. llvm-svn: 218709
* Adjust test case addition in r218702 so as not to fail when the X86 target ↵David Blaikie2014-09-303-2/+5
| | | | | | isn't built. llvm-svn: 218708
* [x86] Rework all of the 128-bit vector shuffle tests with my handy testChandler Carruth2014-09-304-1222/+2541
| | | | | | | | | | | | | | | | | | | | | | | | | updating script so that they are more thorough and consistent. Specific fixes here include: - Actually test VEX-encoded AVX mnemonics. - Actually use an SSE 4.1 run to test SSE 4.1 features! - Correctly check instructions sequences from the start of the function. - Elide the shuffle operands and comment designator in a consistent way. - Test all of the architectures instead of just the ones I was motivated to manually author. I've gone back through and fixed up any egregious issues I spotted. Let me know if I missed something you really dislike. One downside to this is that we're now not as diligently using FileCheck variables for registers. I would be much more concerned with this if we had larger register usage, but there just aren't that interesting of register choices here and most of the registers are constrained by the ABI. Ultimately, I don't think this is likely to be the maintenance burden for these tests and updating them again should be staright forward. llvm-svn: 218707
* [PECOFF] Fix /entry option.Rui Ueyama2014-09-303-3/+22
| | | | | | | | This is yet another edge case of ambiguous name resolution. When a symbol is specified with /entry:SYM, SYM may be resolved to the C++ mangled function name (?SYM@@YAXXZ). llvm-svn: 218706
* [PECOFF] Move helper function out of classRui Ueyama2014-09-303-33/+55
| | | | | | No functionality change intended. llvm-svn: 218705
* [mach-o] add file comment to compact unwind passTim Northover2014-09-301-1/+3
| | | | llvm-svn: 218704
* [mach-o] create __unwind_info section on x86_64Tim Northover2014-09-3017-13/+669
| | | | | | | | | | | This is a minimally useful pass to construct the __unwind_info section in a final object from the various __compact_unwind inputs. Currently it doesn't produce any compressed pages, only works for x86_64 and will fail if any function ends up without __compact_unwind. rdar://problem/18208653 llvm-svn: 218703
* Disable the -gmlt optimization implemented in r218129 under Darwin due to ↵David Blaikie2014-09-303-3/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | issues with dsymutil. r218129 omits DW_TAG_subprograms which have no inlined subroutines when emitting -gmlt data. This makes -gmlt very low cost for -O0 builds. Darwin's dsymutil reasonably considers a CU empty if it has no subprograms (which occurs with the above optimization in -O0 programs without any force_inline function calls) and drops the line table, CU, and everything in this situation, making backtraces impossible. Until dsymutil is modified to account for this, disable this optimization on Darwin to preserve the desired functionality. (see r218545, which should be reverted after this patch, for other discussion/details) Footnote: In the long term, it doesn't look like this scheme (of simplified debug info to describe inlining to enable backtracing) is tenable, it is far too size inefficient for optimized code (the DW_TAG_inlined_subprograms, even once compressed, are nearly twice as large as the line table itself (also compressed)) and we'll be considering things like Cary's two level line table proposal to encode all this information directly in the line table. llvm-svn: 218702
* Use the target-specified iteration count to opt out of any further ↵Sanjay Patel2014-09-301-60/+62
| | | | | | refinement of an estimate. NFC. llvm-svn: 218700
* Not all processes have a Dynamic Loader. Be sure to check that it exists ↵Jim Ingham2014-09-301-1/+4
| | | | | | | | before using it. <rdar://problem/18491391> llvm-svn: 218699
* Split the estimate() interface into separate functions for each type. NFC.Sanjay Patel2014-09-304-34/+61
| | | | | | | | | | | | It was hacky to use an opcode as a switch because it won't always match (rsqrte != sqrte), and it looks like we'll need to add more special casing per arch than I had hoped for. Eg, x86 will prefer a different NR estimate implementation. ARM will want to use it's 'step' instructions. There also don't appear to be any new estimate instructions in any arch in a long, long time. Altivec vloge and vexpte may have been the first and last in that field... llvm-svn: 218698
* InstrProf: Remove an unused member (NFC)Justin Bogner2014-09-301-6/+3
| | | | llvm-svn: 218697
* [PECOFF] Allow /export:<symbol>,PRTVATE.Rui Ueyama2014-09-302-4/+8
| | | | | | PRIVATE option is also an undocumented feature. llvm-svn: 218696
* [PECOFF] Fix /export option.Rui Ueyama2014-09-302-3/+24
| | | | | | | | | | | MSDN doesn't say about /export:foo=bar style option, but it turned out MSVC link.exe actually accepts that. So we need that too. It also means that the export directive in the module definition file and /export command line option are functionally equivalent. llvm-svn: 218695
* Avoid a crash after loading an #undef'd macro in code completionBen Langmuir2014-09-305-2/+18
| | | | | | | | | | | In code-completion, don't assume there is a MacroInfo for everything, since we aren't serializing the def corresponding to a later #undef in the same module. Also setup the HadMacro bit correctly for undefs to avoid an assertion failure. rdar://18416901 llvm-svn: 218694
* Recommit r218010 [FastISel][AArch64] Fold bit test and branch into TBZ and TBNZ.Juergen Ributzka2014-09-302-54/+241
| | | | | | | | | | | | | | Note: This version fixed an issue with the TBZ/TBNZ instructions that were generated in FastISel. The issue was that the 64bit version of TBZ (TBZX) automagically sets the upper bit of the immediate field that is used to specify the bit we want to test. To test for any of the lower 32bits we have to first extract the subregister and use the 32bit version of the TBZ instruction (TBZW). Original commit message: Teach selectBranch to fold bit test and branch into a single instruction (TBZ or TBNZ). llvm-svn: 218693
* R600/SI: Fix printing of clamp and omodMatt Arsenault2014-09-309-32/+70
| | | | | | | | No tests for omod since nothing uses it yet, but this should get rid of the remaining annoying trailing zeros after some instructions. llvm-svn: 218692
* R600/SI: Update VOP3b to not include obsolete operandsMatt Arsenault2014-09-303-15/+16
| | | | | | abs / neg are now part of the srcN_modifiers operands llvm-svn: 218691
* [PECOFF] Fix __imp_ prefix on x64.Rui Ueyama2014-09-302-12/+20
| | | | | | | | "__imp_" prefix always starts with double underscores. When I was writing the original code I misunderstood that it's "_imp_" on x64. llvm-svn: 218690
* clang-format: [JS] Support AllowShortFunctionsOnASingleLine.Daniel Jasper2014-09-303-3/+73
| | | | | | | | | Specifically, this also counts for stuff like (with style "inline"): var x = function() { return 1; }; llvm-svn: 218689
* CUDA: mark the target of implicit intrinsics properlyEli Bendersky2014-09-302-0/+16
| | | | | | | | | | | | | r218624 implemented target inference for implicit special members. However, other entities can be implicit - for example intrinsics. These can not have inference running on them, so they should be marked host device as before. This is the safest and most flexible setting, since by construction these functions don't invoke anything, and we'd like them to be invokable from both host and device code. LLVM's intrinsics definitions (where these intrinsics come from in the case of CUDA/NVPTX) have no notion of target, so both host and device intrinsics can be supported this way. llvm-svn: 218688
* Add SBThreadPlan to this CMakeLists.txt as well.Jim Ingham2014-09-301-0/+1
| | | | llvm-svn: 218687
* thread state coordinator: add additional assert missing from previous test ↵Todd Fiala2014-09-301-0/+1
| | | | | | check-in. llvm-svn: 218686
* Fix FreeBSD build.Zachary Turner2014-09-301-6/+6
| | | | llvm-svn: 218685
* Fixup some minor issues with HostProcess.Zachary Turner2014-09-303-0/+12
| | | | llvm-svn: 218684
* thread state coordinator: add test to be explicit about resume behavior in ↵Todd Fiala2014-09-303-9/+137
| | | | | | | | | | | | | | | | | | | | presence of deferred stop notification still pending. There is a state transition that seems potentially buggy that I am capturing and logging here, and including an explicit test to demonstrate expected behavior. See new test for detailed description. Added logging around this area since, if we hit it, we may have a usage bug, or a new state transition we really need to investigate. This is around this scenario: Thread C deferred stop notification awaiting thread A and thread B to stop. Thread A stops. Thread A requests resume. Thread B stops. Here we will explicitly signal the deferred stop notification after thread B stops even though thread A is now resumed. Copious logging happens here. llvm-svn: 218683
* Extend C disassembler API to allow specifying target featuresBradley Smith2014-09-304-26/+66
| | | | llvm-svn: 218682
* Add numeric extend, trunctate to mips fast-iselReed Kotler2014-09-303-5/+368
| | | | | | | | | | | | | | | | | | | | | Summary: Add numeric extend, trunctate to mips fast-isel Reactivates D4827 Test Plan: fpext.ll loadstoreconv.ll Reviewers: dsanders Subscribers: mcrosier Differential Revision: http://reviews.llvm.org/D5251 llvm-svn: 218681
* [AArch64] Remove unnecessary whitespace. (Test commit)Tom Coxon2014-09-301-2/+2
| | | | llvm-svn: 218680
* Fix cmake build for new thread plan files.Todd Fiala2014-09-302-0/+2
| | | | llvm-svn: 218679
* [DAG] Check in advance if a build_vector has a legal type before attempting ↵Andrea Di Biagio2014-09-301-4/+4
| | | | | | | | | | | | | | to convert it into a shuffle. Currently, the DAG Combiner only tries to convert type-legal build_vector nodes into shuffles. This patch simply moves the logic that checks if a build_vector has a legal value type up before we even start analyzing the operands. This allows to early exit immediately from method 'visitBUILD_VECTOR' if the node type is known to be illegal. No functional change intended. llvm-svn: 218677
* Revert r218673 'llvm-cov: add test for report's function & file association.'Alex Lorenz2014-09-304-32/+0
| | | | | | Test causes buildbot failures. llvm-svn: 218676
* [UBsan] Disable summary.cpp on Darwin. The test requires ubsan-asan, which ↵Alexander Potapenko2014-09-301-0/+2
| | | | | | does not work yet. llvm-svn: 218675
* [asan] XFAIL one test on Android.Evgeniy Stepanov2014-09-301-0/+3
| | | | | | And add a missing return in main, just in case. llvm-svn: 218674
* llvm-cov: add test for report's function & file association.Alex Lorenz2014-09-304-0/+32
| | | | | | | | This commit adds a test which checks that the functions defined in header files will get associated with the header files rather than the source files in the reports. Differential Revision: http://reviews.llvm.org/D5489 llvm-svn: 218673
* llvm-cov: Use the number of executed functions for the function coverage metric.Alex Lorenz2014-09-309-24/+57
| | | | | | | | This commit fixes llvm-cov's function coverage metric by using the number of executed functions instead of the number of fully covered functions. Differential Revision: http://reviews.llvm.org/D5196 llvm-svn: 218672
* Introduce support for custom wrappers for vararg functions.Lorenzo Martignoni2014-09-302-13/+28
| | | | | | Differential Revision: http://reviews.llvm.org/D5412 llvm-svn: 218671
* [AVX512] Added intrinsics for 128-, 256- and 512-bit versions of VCMPGT{BWDQ}.Robert Khasanov2014-09-306-0/+242
| | | | | | Patch by Sergey Lisitsyn <sergey.lisitsyn@intel.com> llvm-svn: 218670
* [AVX512] Added intrinsics for 128- and 256-bit versions of VCMPEQ{BWDQ}Robert Khasanov2014-09-306-7/+214
| | | | | | | | | | | | | | Fixed lowering of this intrinsics in case when mask is v2i1 and v4i1. Now cmp intrinsics lower in the following way: (i8 (int_x86_avx512_mask_pcmpeq_q_128 (v2i64 %a), (v2i64 %b), (i8 %mask))) -> (i8 (bitcast (v8i1 (insert_subvector undef, (v2i1 (and (PCMPEQM %a, %b), (extract_subvector (v8i1 (bitcast %mask)), 0))), 0)))) llvm-svn: 218669
* [AVX512] Added intrinsics for VPCMPEQB and VPCMPEQW.Robert Khasanov2014-09-306-44/+96
| | | | | | Added new operand type for intrinsics (IIT_V64) llvm-svn: 218668
* [AVX512] Enabled intrinsics for VPCMPEQD and VPCMPEQQ.Robert Khasanov2014-09-303-4/+63
| | | | | | Added CMP_MASK intrinsic type llvm-svn: 218667
* Make sure aggregates are properly alligned on MSP430.Job Noorman2014-09-302-2/+2
| | | | llvm-svn: 218666
* Make sure aggregates are properly alligned on MSP430.Job Noorman2014-09-301-1/+1
| | | | llvm-svn: 218665
* [asan] Run tests with the default compiler on Android.Evgeniy Stepanov2014-09-301-1/+1
| | | | llvm-svn: 218664
* [asan] Re-enable lsan_annotations test on Android.Evgeniy Stepanov2014-09-301-3/+0
| | | | | | Was fixed by r218605. llvm-svn: 218663
* [UBSan] Use <machine/endian.h> on Darwin.Alexander Potapenko2014-09-301-3/+13
| | | | llvm-svn: 218662
* MS ABI: Correct layout for empty recordsDavid Majnemer2014-09-303-3/+79
| | | | | | | | Empty records do not always have size equivalent to their alignment. They only do so when their alignment is at least as large as the minimum empty struct size: 1 byte in C++ and 4 bytes in C. llvm-svn: 218661
* [OPENMP] Codegen of the ‘aligned’ clause for the ‘omp simd’ directive.Alexander Musman2014-09-309-16/+91
| | | | | | Differential Revision: http://reviews.llvm.org/D5499 llvm-svn: 218660
* [IndVarSimplify] Widen loop unsigned compares.Chad Rosier2014-09-302-6/+30
| | | | | | | This patch extends r217953 to handle unsigned comparison. Phabricator revision: http://reviews.llvm.org/D5526 llvm-svn: 218659
* [x86] Revert r218588, r218589, and r218600. These patches were pursuingChandler Carruth2014-09-306-169/+297
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a flawed direction and causing miscompiles. Read on for details. Fundamentally, the premise of this patch series was to map VECTOR_SHUFFLE DAG nodes into VSELECT DAG nodes for all blends because we are going to *have* to lower to VSELECT nodes for some blends to trigger the instruction selection patterns of variable blend instructions. This doesn't actually work out so well. In order to match performance with the existing VECTOR_SHUFFLE lowering code, we would need to re-slice the blend in order to fit it into either the integer or floating point blends available on the ISA. When coming from VECTOR_SHUFFLE (or other vNi1 style VSELECT sources) this works well because the X86 backend ensures that these types of operands to VSELECT get sign extended into '-1' and '0' for true and false, allowing us to re-slice the bits in whatever granularity without changing semantics. However, if the VSELECT condition comes from some other source, for example code lowering vector comparisons, it will likely only have the required bit set -- the high bit. We can't blindly slice up this style of VSELECT. Reid found some code using Halide that triggers this and I'm hopeful to eventually get a test case, but I don't need it to understand why this is A Bad Idea. There is another aspect that makes this approach flawed. When in VECTOR_SHUFFLE form, we have very distilled information that represents the *constant* blend mask. Converting back to a VSELECT form actually can lose this information, and so I think now that it is better to treat this as VECTOR_SHUFFLE until the very last moment and only use VSELECT nodes for instruction selection purposes. My plan is to: 1) Clean up and formalize the target pre-legalization DAG combine that converts a VSELECT with a constant condition operand into a VECTOR_SHUFFLE. 2) Remove any fancy lowering from VSELECT during *legalization* relying entirely on the DAG combine to catch cases where we can match to an immediate-controlled blend instruction. One additional step that I'm not planning on but would be interested in others' opinions on: we could add an X86ISD::VSELECT or X86ISD::BLENDV which encodes a fully legalized VSELECT node. Then it would be easy to write isel patterns only in terms of this to ensure VECTOR_SHUFFLE legalization only ever forms the fully legalized construct and we can't cycle between it and VSELECT combining. llvm-svn: 218658
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