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* gn build: Merge r362196Nico Weber2019-05-311-0/+2
| | | | llvm-svn: 362222
* gn build: Merge r362190Nico Weber2019-05-311-0/+2
| | | | llvm-svn: 362221
* [ELF] Delete GotEntrySize and GotPltEntrySizeFangrui Song2019-05-3112-35/+14
| | | | | | | | | | | | | GotEntrySize and GotPltEntrySize were added in D22288. Later, with the introduction of wordsize() (then Config->Wordsize), they become redundant, because there is no target that sets GotEntrySize or GotPltEntrySize to a number different from Config->Wordsize. Reviewed By: grimar, ruiu Differential Revision: https://reviews.llvm.org/D62727 llvm-svn: 362220
* ftime-trace: Trace loop passesRussell Gallop2019-05-311-0/+3
| | | | | | | | | | These can take a significant amount of time in some builds. Suggested by Andrea Di Biagio. Differential Revision: https://reviews.llvm.org/D62666 llvm-svn: 362219
* [ELF] Replace a dead test in getSymVA() with assert()Fangrui Song2019-05-311-7/+1
| | | | | | | | | | | | Symbols relative to discarded comdat sections are Undefined instead of Defined now (after D59649 and D61583). The `== &InputSection::Discarded` test becomes dead. I cannot find a test related to this behavior. Reviewed By: ruiu Differential Revision: https://reviews.llvm.org/D62725 llvm-svn: 362218
* [InstCombine] 'C-(C2-X) --> X+(C-C2)' constant-foldRoman Lebedev2019-05-312-3/+8
| | | | | | | | | | It looks this fold was already partially happening, indirectly via some other folds, but with one-use limitation. No other fold here has that restriction. https://rise4fun.com/Alive/ftR llvm-svn: 362217
* [InstCombine] 'add (sub C1, X), C2 --> sub (add C1, C2), X' constant-foldRoman Lebedev2019-05-312-19/+18
| | | | | | https://rise4fun.com/Alive/qJQ llvm-svn: 362216
* [AArch64][SVE2] Asm: support WHILE instructionsCullen Rhodes2019-05-3114-0/+543
| | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: * WHILEGE, WHILEGT, WHILEHS, WHILEHI, WHILEWR, WHILERW The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62601 llvm-svn: 362215
* [AArch64][SVE2] Asm: support TBL/TBX instructionsCullen Rhodes2019-05-316-7/+181
| | | | | | | | | | | | | | | | | Summary: A three sources variant of the TBL instruction is added to the existing SVE instruction in SVE2. This is implemented with minor changes to the existing TableGen class. TBX is a new instruction with its own definition. The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62600 llvm-svn: 362214
* [AArch64][SVE2] Asm: support SVE2 store instructionsCullen Rhodes2019-05-3111-2/+661
| | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: * STNT1B, STNT1H, STNT1S, STNT1D The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62599 llvm-svn: 362213
* [MIPS GlobalISel] Add detailed tests for lower callPetar Avramovic2019-05-312-5/+298
| | | | | | | | | | | | | | | | Test different operand types of callee and their behavior whether relocation model is pic or not. Possible operand types are: Register (function pointer), External symbol (used for libcalls e.g. __udivdi3 or memcpy), Global address. Global address has different handling depending on relocation model and linkage type. Register and external symbol do not. Differential Revision: https://reviews.llvm.org/D62590 llvm-svn: 362212
* Follow up and fix for rL362064Sjoerd Meijer2019-05-311-1/+2
| | | | | | | | Fix the misleadingly indentation introduced in rL362064. This will get rid of the compiler warning, and it was actually a bug. This change will be used and tested in D62669. llvm-svn: 362211
* [MIPS GlobalISel] Handle position independent code Petar Avramovic2019-05-319-19/+451
| | | | | | | | | | | | | Handle position independent code for MIPS32. When callee is global address, lower call will emit callee as G_GLOBAL_VALUE and add target flag if needed. Support $gp in getRegBankFromRegClass(). Select G_GLOBAL_VALUE, specially handle case when there are target flags attached by lowerCall. Differential Revision: https://reviews.llvm.org/D62589 llvm-svn: 362210
* [NFC][InstCombine] Copy add/sub constant-folding tests from codegenRoman Lebedev2019-05-311-0/+536
| | | | | | Last three patterns are missed. llvm-svn: 362209
* [NFC][Codegen] Add/sub constant-folding: add scalar tests tooRoman Lebedev2019-05-312-182/+953
| | | | | | Just for completeness. llvm-svn: 362208
* [ELF][test] Restore linkerscript/symbol-location.s to test ↵Fangrui Song2019-05-311-0/+16
| | | | | | | | | | | | getLinkerScriptLocation() The test (the only test that checks getLinkerScriptLocation()) deleted by r358652 can be restored by replacing R_X86_64_PLT32 with R_X86_64_PC32, and changing -pie to -shared (preemptable). Then, the symbol will not be a link-time constant and a -fPIC error will be issued. llvm-svn: 362207
* [mips] Move initGlobalBaseReg to MipsFunctionInfo. NFCPetar Avramovic2019-05-314-94/+93
| | | | | | | | | | | Move initGlobalBaseReg from MipsSEDAGToDAGISel to MipsFunctionInfo. This way functions used for handling position independent code during instruction selection, getGlobalBaseReg and initGlobalBaseReg, end up in same class. Differential Revision: https://reviews.llvm.org/D62586 llvm-svn: 362206
* [InstructionSimplify] Add missing implementation of llvm::SimplifyUnOp. NFCCraig Topper2019-05-311-0/+4
| | | | | | | There are no callers currently, but the function is declared so we should at least implement it. llvm-svn: 362205
* [MIPS GlobalISel] Lower call for callee that is registerPetar Avramovic2019-05-312-6/+28
| | | | | | | | | Lower call for callee that is register for MIPS32. Register should contain callee function address. Differential Revision: https://reviews.llvm.org/D62585 llvm-svn: 362204
* [X86] Remove patterns for X86VSintToFP/X86VUintToFP+loadv4f32 to v2f64.Craig Topper2019-05-316-77/+36
| | | | | | | | | | | | | | These patterns can incorrectly narrow a volatile load from 128-bits to 64-bits. Similar to PR42079. Switch to using (v4i32 (bitcast (v2i64 (scalar_to_vector (loadi64))))) as the load pattern used in the instructions. This probably still has issues in 32-bit mode where loadi64 isn't legal. Maybe we should use VZMOVL for widened loads even when we don't need the upper bits as zeroes? llvm-svn: 362203
* [X86] Add test cases for failure to use 128-bit masked vcvtdq2pd when load ↵Craig Topper2019-05-312-0/+212
| | | | | | starts as v2i32. llvm-svn: 362202
* [X86] Add test cases for a volatile load shrinking bug involving cvtdq2pd. NFCCraig Topper2019-05-312-276/+308
| | | | | | Similar to PR42079 llvm-svn: 362201
* [X86] Copy a test case from avx512-cvt.ll to avx512-cvt-widen.ll. NFCCraig Topper2019-05-311-0/+23
| | | | llvm-svn: 362200
* [X86] Remove avx512 isel patterns for fpextend+load. Prefer to only match fp ↵Craig Topper2019-05-313-16/+62
| | | | | | | | | | | | | | | | | extloads instead. DAG combine will usually fold fpextend+load to an fp extload anyway. So the 256 and 512 patterns were probably unnecessary. The 128 bit pattern was special in that it looked for a v4f32 load, but then used it in an instruction that only loads 64-bits. This is bad if the load happens to be volatile. We could probably make the patterns volatile aware, but that's more work for something that's probably rare. The peephole pass might kick in and save us anyway. We might also be able to fix this with some additional DAG combines. This also adds patterns for vselect+extload to enabled masked vcvtps2pd to be used. Previously we looked for the unlikely vselect+fpextend+load. llvm-svn: 362199
* [X86] Add test to show missed opportunity to use masked vcvtps2pd for ↵Craig Topper2019-05-311-0/+24
| | | | | | vselect+extload. llvm-svn: 362198
* [X86] Add test case for PR42079. NFCCraig Topper2019-05-311-0/+45
| | | | llvm-svn: 362197
* [X86] Add VP2INTERSECT instructionsPengfei Wang2019-05-3115-3/+343
| | | | | | | | | | Support intel AVX512 VP2INTERSECT instructions in clang Patch by Xiang Zhang (xiangzhangllvm) Differential Revision: https://reviews.llvm.org/D62367 llvm-svn: 362196
* [MIR-Canon] Skip the first N vreg names lazily.Puyan Lotfi2019-05-312-9/+10
| | | | | | | | | | | | | | | This consolidates the vreg skip code into one function (SkipVRegs()). SkipVRegs() now knows if it should skip as if it is the first initialization or subsequent skips. The first skip is also done the first time createVirtualRegister is called by the cursor instead of by the cursor's constructor. This prevents verifier errors on machine functions that have no vregs (where the verifier will complain that there are vregs when the function uses none). Differential Revision: https://reviews.llvm.org/D62717 llvm-svn: 362195
* Fix problem with r362192Richard Trieu2019-05-311-5/+8
| | | | | | | The string returned only sometimes ends in NULL. Explicitly check for the NULL and pop off the NULL if it is there. llvm-svn: 362194
* [X86] Correct the ins operand order for MASKPAIR16STORE to match other store ↵Craig Topper2019-05-312-6/+6
| | | | | | | | | | | | | | | | | | instructions. This makes the 5 address operands come first. And the data operand comes last. This matches the operand order the instruction is created with. It's also the expected order in X86MCInstLower. So everything appeared to work, but the operands didn't match their declared type. Fixes a -verify-machineinstrs failure. Also remove the isel patterns from these instructions since they should only be used for stack spills and reloads. I'm not even sure what types the patterns were looking for to match. llvm-svn: 362193
* Fix off-by-one error.Richard Trieu2019-05-311-1/+1
| | | | | | | The created string is one char too large, so it pulls the terminating NULL as the last character of the string. This later causes SocketTest.cpp to fail. llvm-svn: 362192
* [MIR-Canon] Hardening propagateLocalCopies.Puyan Lotfi2019-05-312-6/+19
| | | | | | | | | | This is am almost NFC, it does the following: - If there is no register class for a COPY's src or dst, bail. - Fixes uses iterator invalidation bug. Differential Revision: https://reviews.llvm.org/D62713 llvm-svn: 362191
* re-commit r361928: [PowerPC] [Clang] Port SSE intrinsics to PowerPCZi Xuan Wu2019-05-3110-17/+4160
| | | | | | | | | | | | | | | Port xmmintrin.h which include Intel SSE intrinsics implementation to PowerPC platform (using Altivec). The new headers containing those implemenations are located into a directory named ppc_wrappers which has higher priority when the platform is PowerPC on Linux. They are mainly developed by Steven Munroe, with contributions from Paul Clarke, Bill Schmidt, Jinsong Ji and Zixuan Wu. Patched by: Qiu Chaofan <qiucf@cn.ibm.com> Reviewed By: Jinsong Ji Differential Revision: https://reviews.llvm.org/D62121 llvm-svn: 362190
* Fix bad go bindings test.Richard Trieu2019-05-311-1/+0
| | | | | | | After r362128, the "byval" attribute has a stricter check and will cause an assertion. Remove the "byval" test case for now. llvm-svn: 362189
* [X86] Add VP2INTERSECT instructionsPengfei Wang2019-05-3139-1/+2816
| | | | | | | | | | Support Intel AVX512 VP2INTERSECT instructions in llvm Patch by Xiang Zhang (xiangzhangllvm) Differential Revision: https://reviews.llvm.org/D62366 llvm-svn: 362188
* Redirect test output to /dev/nullRichard Trieu2019-05-311-5/+5
| | | | llvm-svn: 362187
* Revert "[X86] Fix i386 struct and union parameter alignment"Pengfei Wang2019-05-313-48/+14
| | | | | | | | | | This reverts commit d61cb749f4ac2c90244906d756e80a5c4a7ffa89 (SVN: 361934). According to James suggestion, revert this change. Please ref: https://reviews.llvm.org/D60748 llvm-svn: 362186
* [CMake] Provide an option to use relative paths in debug infoPetr Hosek2019-05-314-0/+21
| | | | | | | | | | | | | | | | | CMake always uses absolute file paths in the generated compiler invocation which results in absolute file paths being embedded in debug info. This is undesirable when building a toolchain e.g. on bots as the debug info may embed the bot source checkout path which is meaningless anywhere else. This change introduces the LLVM_USE_RELATIVE_PATHS_IN_DEBUG_INFO which uses -fdebug-prefix-map (where supported) options to rewrite paths embedded into debug info with relative ones. Additionally, LLVM_SOURCE_PREFIX can be used to override the path to source directory with a different one. Differential Revision: https://reviews.llvm.org/D62622 llvm-svn: 362185
* PR39728: When completing a class, complete the destructor first.Richard Smith2019-05-312-39/+69
| | | | | | | | | We need to know whether the destructor is trivial in order to tell whether other parts of the class are valid (in particular, this affects whether the type is a literal type, which affects whether defaulted special members can be declared constexpr or are implicitly constexpr). llvm-svn: 362184
* Fix the predefined exponent limit macros for the 16-bit IEEE format.John McCall2019-05-313-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The magnitude range of normalized _Float16 is 2^-14 (~6e-5) to (2-2^-10)*2^15 (65504). You might think, then, that the code is correct to defne FLT16_MIN_EXP and FLT16_MAX_EXP to be -14 and 15 respectively. However, for some reason the C specification actually specifies a bias for these macros: C11 5.2.4.2.2: - minimum negative integer such that FLT_RADIX raised to one less than that power is a normalized floating-point number, e_min: FLT_MIN_EXP DBL_MIN_EXP LDBL_MIN_EXP - maximum integer such that FLT_RADIX raised to one less than that power is a representable finite floating-point number, e_max: FLT_MAX_EXP DBL_MAX_EXP LDBL_MAX_EXP FLT16_MIN_EXP and FLT16_MAX_EXP should clearly be biased the same way, and other compilers do in fact do so, as do our OpenCL headers for `half`. Additionally, FLT16_MIN_10_EXP is just wrong. llvm-svn: 362183
* Defer building 'this' captures until we have left the capturing regionRichard Smith2019-05-319-67/+46
| | | | | | | | | | and returned to the context in which 'this' should be captured. This means we now always mark 'this' referenced from the context in which it's actually referenced, rather than potentially from some context nested within that. llvm-svn: 362182
* [CMake][Fuchsia] Use libc++ ABI v2 on Darwin as wellPetr Hosek2019-05-311-0/+1
| | | | | | | | | Since we share headers between host and target builds, we need to use the same version for both. Differential Revision: https://reviews.llvm.org/D62712 llvm-svn: 362181
* Fix -DBUILD_SHARED_LIBS=ON build after rL362160Sam Clegg2019-05-314-0/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D62709 llvm-svn: 362180
* Defer capture initialization for captured regions until after we've leftRichard Smith2019-05-318-71/+145
| | | | | | | | | | | | | | | | the captured region scope. This removes a case where we would build expressions (and mark declarations odr-used) in the wrong scope. Remove the now-unused 'capture initializer' field on sema::Capture (except for 'this' captures, which still need to be cleaned up). No functionality change intended (except that we now very slightly more precisely determine whether we need to use a capture or not when another captured region encloses an OpenMP captured region). llvm-svn: 362179
* Defer capture initialization for blocks until after we've left theRichard Smith2019-05-317-87/+130
| | | | | | | | | function scope. This removes one of the last few cases where we build expressions in the wrong function scope context. No functionality change intended. llvm-svn: 362178
* Make CPlusPlusNameParser robust against nullptr StringRefs.Adrian Prantl2019-05-312-0/+8
| | | | | | | | | | There is likely also an underlying bug in all code that calls CPlusPlusNameParser with nullptrs, but this patch can also stand for itself. rdar://problem/49072829 llvm-svn: 362177
* [clangd] clang-format SymbolCollector.cppNathan Ridge2019-05-301-4/+3
| | | | llvm-svn: 362176
* [X86] Remove result type constraints from the ↵Craig Topper2019-05-301-3/+3
| | | | | | | | | | extloadv2f32/extloadv4f32/extloadv8f32 PatFrags. NFC The result types aren't mentioned in the pattern name so really shouldn't be in the PatFrags. The users of these either have their own type constraint or rely on the type constranit system to realize the only legal extend would be to f64. llvm-svn: 362175
* MISched: Fix -misched-regpressure=0 if subreg liveness enabledMatt Arsenault2019-05-301-1/+3
| | | | | | | Test is waiting on fixing several more crashes in the AMDGPU scheduler implementation with this. llvm-svn: 362174
* Make ConnectionFileDescription work with all socketsAntonio Afonso2019-05-3010-19/+125
| | | | | | | | | | | | | | | | | | | | | Summary: My main goal here is to make lldb-server work with Android Studio. This is currently not the case because lldb-server is started in platform mode listening on a domain socket. When Android Studio connects to it lldb-server crashes because even though it's listening on a domain socket as soon as it gets a connection it asserts that it's a TCP connection, which will obviously fails for any non-tcp connection. To do this I came up with a new method called GetConnectURI() in Socket that returns the URI needed to connect to the connected portion of the socket. Reviewers: labath, clayborg, xiaobai Reviewed By: labath Subscribers: mgorny, jfb, lldb-commits Tags: #lldb Differential Revision: https://reviews.llvm.org/D62089 llvm-svn: 362173
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