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* Don't search for module resources at all if the setting is set to "false". Greg Clayton2014-08-182-4/+6
| | | | llvm-svn: 215936
* [CMake] clang-rename: Optimize libdeps.NAKAMURA Takumi2014-08-181-9/+0
| | | | llvm-svn: 215935
* Add trailing linefeed.NAKAMURA Takumi2014-08-181-1/+1
| | | | llvm-svn: 215934
* profile: Improve error messages on bad GCDA filesJustin Bogner2014-08-181-4/+12
| | | | llvm-svn: 215933
* sanitizer_printf.cc: guard the va_copy hack on _MSC_VERHans Wennborg2014-08-181-1/+2
| | | | llvm-svn: 215932
* Make llvm-objdump handle both arm and thumb disassembly from the same Mach-OKevin Enderby2014-08-185-13/+185
| | | | | | | | | | file with -macho, the Mach-O specific object file parser option. After some discussion I chose to do this implementation contained in the logic of llvm-objdump’s MachODump.cpp using a second disassembler for thumb when needed and with updates mostly contained in the MachOObjectFile class. llvm-svn: 215931
* Revert "[ASan/Win] Remove a hack that seems not to be required with VS2013 ↵Hans Wennborg2014-08-181-0/+4
| | | | | | | | anymore" (r215708) This is still needed for VS2012. llvm-svn: 215930
* Fix the rececl chain for redeclarations of predefined declsBen Langmuir2014-08-183-0/+14
| | | | | | | | | Predefined decls like 'Protocol' in objc are not loaded from AST files, so we cannot rely on loading the canonical decl to complete the redecl chain for redeclarations of these decls. The broken redecl chain was non-circular, so looping over redecls() would hang. llvm-svn: 215929
* Store std::unique_ptr in InMemoryBuffers. NFC.Rafael Espindola2014-08-184-28/+35
| | | | llvm-svn: 215928
* return a std::unique_ptr from getMainBufferWithPrecompiledPreamble. NFC.Rafael Espindola2014-08-182-24/+26
| | | | llvm-svn: 215927
* Use std::unique_ptr to simplify this code a bit.Rafael Espindola2014-08-182-13/+9
| | | | llvm-svn: 215926
* Inline function into only use.Rafael Espindola2014-08-182-7/+2
| | | | llvm-svn: 215925
* [X86][Haswell][SchedModel] Tidy up.Quentin Colombet2014-08-181-56/+63
| | | | | | <rdar://problem/15607571> llvm-svn: 215924
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+30
| | | | | | | | | Group: Floating Point XMM and YMM instructions. Sub-group: Other instructions. <rdar://problem/15607571> llvm-svn: 215923
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+9
| | | | | | | | | Group: Floating Point XMM and YMM instructions. Sub-group: Logic instructions. <rdar://problem/15607571> llvm-svn: 215922
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+68
| | | | | | | | | Group: Floating Point XMM and YMM instructions. Sub-group: Math instructions. <rdar://problem/15607571> llvm-svn: 215921
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+170
| | | | | | | | | Group: Floating Point XMM and YMM instructions. Sub-group: Arithmetic instructions. <rdar://problem/15607571> llvm-svn: 215920
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+170
| | | | | | | | | Group: Floating Point XMM and YMM instructions. Sub-group: Conversion instructions. <rdar://problem/15607571> llvm-svn: 215919
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+144
| | | | | | | | | Group: Floating Point XMM and YMM instructions. Sub-group: Move instructions. <rdar://problem/15607571> llvm-svn: 215918
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+9
| | | | | | | | | Group: Integer MMX and XMM instructions. Sub-group: Other instructions. <rdar://problem/15607571> llvm-svn: 215917
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+31
| | | | | | | | | Group: Integer MMX and XMM instructions. Sub-group: Logic instructions. <rdar://problem/15607571> llvm-svn: 215916
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+63
| | | | | | | | | Group: Integer MMX and XMM instructions. Sub-group: Arithmetic instructions. <rdar://problem/15607571> llvm-svn: 215915
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+251
| | | | | | | | | Group: Integer MMX and XMM instructions. Sub-group: Move instructions. <rdar://problem/15607571> llvm-svn: 215914
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+16
| | | | | | | | | Group: Floating Point x87 instructions. Sub-group: Math instructions. <rdar://problem/15607571> llvm-svn: 215913
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+70
| | | | | | | | | Group: Floating Point x87 instructions. Sub-group: Arithmetic instructions. <rdar://problem/15607571> llvm-svn: 215912
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+126
| | | | | | | | | Group: Floating Point x87 instructions. Sub-group: Move instructions. <rdar://problem/15607571> llvm-svn: 215911
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+37
| | | | | | | | | Group: Integer instructions. Sub-group: Other instructions. <rdar://problem/15607571> llvm-svn: 215910
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+26
| | | | | | | | | Group: Integer instructions. Sub-group: Synchronization instructions. <rdar://problem/15607571> llvm-svn: 215909
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+42
| | | | | | | | | Group: Integer instructions. Sub-group: String instructions. <rdar://problem/15607571> llvm-svn: 215908
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+60
| | | | | | | | | Group: Integer instructions. Sub-group: Control transfer instructions. <rdar://problem/15607571> llvm-svn: 215907
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+216
| | | | | | | | | Group: Integer instructions. Sub-group: Logic instructions. <rdar://problem/15607571> llvm-svn: 215906
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+192
| | | | | | | | | Group: Integer instructions. Sub-group: Arithmetic instructions. <rdar://problem/15607571> llvm-svn: 215905
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+145
| | | | | | | | | Group: Integer instructions. Sub-group: Move instructions. <rdar://problem/15607571> llvm-svn: 215904
* Added newline at end of file to avoid compiler warning.Greg Clayton2014-08-181-1/+1
| | | | llvm-svn: 215903
* Make use of isAtLeastRelease/Acquire in the ARM/AArch64 backendsRobin Morisset2014-08-184-15/+10
| | | | | | | | | | | | | | | | | Summary: Make use of isAtLeastRelease/Acquire in the ARM/AArch64 backends These helper functions are introduced in D4844. Depends D4844 Test Plan: make check-all passes Reviewers: jfb Subscribers: aemerson, llvm-commits, mcrosier, reames Differential Revision: http://reviews.llvm.org/D4937 llvm-svn: 215902
* Fix an issue with source file groupings in the CMake build.Zachary Turner2014-08-181-1/+1
| | | | llvm-svn: 215901
* Simplify ASTUnit::Parse a bit by passing a std::unique_ptr to it.Rafael Espindola2014-08-182-29/+20
| | | | llvm-svn: 215900
* [x32] Handle -m64/-m32 switches by Driver in x32 modePavel Chupin2014-08-182-4/+41
| | | | | | | | | | | | | | | | | Summary: Adding remaining 2 cases handling: * from x32 to 32 via -m32 * from x32 to 64 via -m64 Test Plan: linux-ld test updated Reviewers: chandlerc, atanasyan Subscribers: cfe-commits, zinovy.nis Differential Revision: http://reviews.llvm.org/D4930 llvm-svn: 215899
* Fix a memory leak in one of the test unit. Silent coverity warning CID 1095912Sylvestre Ledru2014-08-181-0/+1
| | | | llvm-svn: 215898
* Add the break in the switch case (even if there is llvm_unreachable. It will ↵Sylvestre Ledru2014-08-181-1/+1
| | | | | | silent coverity warning CID 1231654 llvm-svn: 215897
* Update the call to llvm::sys::fs::UniqueID to match the definition: ↵Sylvestre Ledru2014-08-181-1/+1
| | | | | | | | UniqueID(uint64_t Device, uint64_t File) Fixes CID 1095247 llvm-svn: 215896
* Disabling an MSVC warning ('var' : definition from the for loop is ignored; ↵Aaron Ballman2014-08-181-0/+1
| | | | | | the definition from the enclosing scope is used) which will trigger false positives more than true positives. llvm-svn: 215895
* add missing break. Fix CID 1229446 & 1203680Sylvestre Ledru2014-08-181-3/+5
| | | | llvm-svn: 215894
* Fix the missleading indentation. Fix CID 1096332Sylvestre Ledru2014-08-181-1/+1
| | | | llvm-svn: 215893
* Fix the missleading indentation. Fix CID 1096300Sylvestre Ledru2014-08-181-3/+3
| | | | llvm-svn: 215892
* Teach the AArch64 backend to handle f16Oliver Stannard2014-08-183-0/+121
| | | | | | | This allows the AArch64 backend to handle fadd, fsub, fmul and fdiv operations on f16 (half-precision) types by promoting to f32. llvm-svn: 215891
* [ARM,AArch64] Do not tail-call to an externally-defined function with weak ↵Oliver Stannard2014-08-184-0/+47
| | | | | | | | | | | | | linkage Externally-defined functions with weak linkage should not be tail-called on ARM or AArch64, as the AAELF spec requires normal calls to undefined weak functions to be replaced with a NOP or jump to the next instruction. The behaviour of branch instructions in this situation (as used for tail calls) is implementation-defined, so we cannot rely on the linker replacing the tail call with a return. llvm-svn: 215890
* AVX-512: Fixed a bug in emitting compare for MVT:i1 type.Elena Demikhovsky2014-08-185-12/+44
| | | | | | Added a test. llvm-svn: 215889
* Silencing an MSVC warning about loop variable conflicting with a variable ↵Aaron Ballman2014-08-181-1/+1
| | | | | | from an outer scope. NFC. llvm-svn: 215888
* TableGen: allow use of uint64_t for available features mask.Tim Northover2014-08-1810-62/+64
| | | | | | | | | | ARM in particular is getting dangerously close to exceeding 32 bits worth of possible subtarget features. When this happens, various parts of MC start to fail inexplicably as masks get truncated to "unsigned". Mostly just refactoring at present, and there's probably no way to test. llvm-svn: 215887
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